Proc. of Int. Conf. on Control, Communication and Power Engineering 2010
Multi Frequency Operation of Buck Converter for Processor S. Sivaram, K. Sundararaman, M. Gopalakrishnan Department of Electrical and Electronics Engineering Sri Venkateswara College of Engineering Sriperumbudur, India. sivaram21_eee@yahoo.co.in. Abstract—Future generations of microprocessors are expected to exhibit much heavier loads and hence their power management becomes more and more complex. Improving the efficiency and dynamics of buck converter is a concerned tradeoff in VRM. The increase of switching frequency can improve the dynamics of buck converter, but efficiency may be degraded. A multi frequency buck converter addresses this concern. This topology exhibited improved steady state and transient response with low switching losses. The control and dynamics of this configuration has been improved and in this paper the performance of this topology has been evaluated for a load current of 100A. Index Terms— Buck converter, Voltage regulator module (VRM), Current programmed module
I. INTRODUCTION In order to improve the environmental impact and to enhance energy efficiency computer processors of the current generations are capable of modulating their power consumption according to the data processing load level. The lowest power consumption mode is referred to as ‘sleep mode’ which is a common function in today’s desktop computers. In this mode, computer consumes the minimum power needed to maintain some critical components that will enable the system to come back to full function in a very short time. The current that the processor demands in ‘sleep mode’ can be as low as 0.1 A for the Pentium series processor from INTEL. The full load current for the processor can exceed 100 A. The processor power supply is also expected to keep the steady state ripple to within 1% of its dc voltage. To improve the steady state and transient response of buck converter and to enhance power density, high switching frequency is an effective method. However, switching frequency rise causes higher switching losses and greater electromagnetic interference [1]. This in turn limits the increase of switching frequency and hinders the improvement of system performance. Multiphase interleaved buck converter is the most popular topology for voltage regulator module design because of its low cost [2]. However when the load current increases, more phases would be required. Eventually it will become more complex and will no longer be cost effective. Moreover it has an extremely narrow duty cycle for very low output voltage. For such narrow duty cycle the efficiency and transient response deteriorate. It also reduces the effectiveness of current ripple cancellation.
To solve the above mentioned problem, several new topologies have been proposed. The topology proposed in [3] uses coupled inductors or transformers to extend the duty. Coupling helps in improving steady state ripple. During transients, the small leakage inductor determines the response. However, the performance depends on the extent of coupling and the leakage inductor. Another drawback is the voltage stress of the MOSFET switch is higher than the input voltage, so an auxiliary circuit is necessary to limit the voltage stress on the switches. A stepping inductance topology is introduced [4] which has a higher inductance in steady state and lower inductance during transient operations. However such a stepping inductance topology has problems of higher voltage swings under inductor current recovery and sudden interruption of inductor current without any freewheeling action. High di/dt during sudden interruption of inductor current and the resulting over voltage spikes leads to increased electromagnetic interference problems. To overcome these, additional circuitry is required to clamp the voltage overshoots, resulting in higher losses. Thus this method cannot be directly used for high slew rate applications. The performance of the converters can further be improved by operating the converter with the combination of a high frequency and low frequency cell [5].The current flowing through the high frequency cell is diverted by the low frequency cell, which also processes the majority of the converter power. This current decreases rapidly so that the high frequency cell can work at very high frequency to improve the dynamic response. Furthermore the efficiency is enhanced due to the low current processing requirement of the high frequency cell. Moreover it is not required to detect the load transient event for control. However this topology was discussed only for a load current up to 5 A and for low slew rates. For processor loads, load currents are high (of the order of 100 A) and slew rates are of the order of 160 A / µS. In this work this topology is adapted for these load conditions and performance of the converter has been analyzed. II. CHOSEN CONVERTER The configuration of the chosen converter for voltage regulator module and its analysis is discussed below: Fig.1 shows the circuit of multi frequency buck converter.
181 © 2009 ACEEE