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Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

Multi Frequency Operation of Buck Converter for Processor S. Sivaram, K. Sundararaman, M. Gopalakrishnan Department of Electrical and Electronics Engineering Sri Venkateswara College of Engineering Sriperumbudur, India. sivaram21_eee@yahoo.co.in. Abstract—Future generations of microprocessors are expected to exhibit much heavier loads and hence their power management becomes more and more complex. Improving the efficiency and dynamics of buck converter is a concerned tradeoff in VRM. The increase of switching frequency can improve the dynamics of buck converter, but efficiency may be degraded. A multi frequency buck converter addresses this concern. This topology exhibited improved steady state and transient response with low switching losses. The control and dynamics of this configuration has been improved and in this paper the performance of this topology has been evaluated for a load current of 100A. Index Terms— Buck converter, Voltage regulator module (VRM), Current programmed module

I. INTRODUCTION In order to improve the environmental impact and to enhance energy efficiency computer processors of the current generations are capable of modulating their power consumption according to the data processing load level. The lowest power consumption mode is referred to as ‘sleep mode’ which is a common function in today’s desktop computers. In this mode, computer consumes the minimum power needed to maintain some critical components that will enable the system to come back to full function in a very short time. The current that the processor demands in ‘sleep mode’ can be as low as 0.1 A for the Pentium series processor from INTEL. The full load current for the processor can exceed 100 A. The processor power supply is also expected to keep the steady state ripple to within 1% of its dc voltage. To improve the steady state and transient response of buck converter and to enhance power density, high switching frequency is an effective method. However, switching frequency rise causes higher switching losses and greater electromagnetic interference [1]. This in turn limits the increase of switching frequency and hinders the improvement of system performance. Multiphase interleaved buck converter is the most popular topology for voltage regulator module design because of its low cost [2]. However when the load current increases, more phases would be required. Eventually it will become more complex and will no longer be cost effective. Moreover it has an extremely narrow duty cycle for very low output voltage. For such narrow duty cycle the efficiency and transient response deteriorate. It also reduces the effectiveness of current ripple cancellation.

To solve the above mentioned problem, several new topologies have been proposed. The topology proposed in [3] uses coupled inductors or transformers to extend the duty. Coupling helps in improving steady state ripple. During transients, the small leakage inductor determines the response. However, the performance depends on the extent of coupling and the leakage inductor. Another drawback is the voltage stress of the MOSFET switch is higher than the input voltage, so an auxiliary circuit is necessary to limit the voltage stress on the switches. A stepping inductance topology is introduced [4] which has a higher inductance in steady state and lower inductance during transient operations. However such a stepping inductance topology has problems of higher voltage swings under inductor current recovery and sudden interruption of inductor current without any freewheeling action. High di/dt during sudden interruption of inductor current and the resulting over voltage spikes leads to increased electromagnetic interference problems. To overcome these, additional circuitry is required to clamp the voltage overshoots, resulting in higher losses. Thus this method cannot be directly used for high slew rate applications. The performance of the converters can further be improved by operating the converter with the combination of a high frequency and low frequency cell [5].The current flowing through the high frequency cell is diverted by the low frequency cell, which also processes the majority of the converter power. This current decreases rapidly so that the high frequency cell can work at very high frequency to improve the dynamic response. Furthermore the efficiency is enhanced due to the low current processing requirement of the high frequency cell. Moreover it is not required to detect the load transient event for control. However this topology was discussed only for a load current up to 5 A and for low slew rates. For processor loads, load currents are high (of the order of 100 A) and slew rates are of the order of 160 A / µS. In this work this topology is adapted for these load conditions and performance of the converter has been analyzed. II. CHOSEN CONVERTER The configuration of the chosen converter for voltage regulator module and its analysis is discussed below: Fig.1 shows the circuit of multi frequency buck converter.

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

Figure 1.Multi frequency buck converter.

The cell containing L, S and SD works at higher frequency and is called the high frequency buck cell. Another cell containing La, Sa and Da works at lower frequency, and is called low frequency buck cell. The high frequency cell is to enhance the output performance, and low frequency buck cell to improve the converter efficiency. An active switch, instead of a diode as in the conventional buck converter, is employed to realize SD in the high frequency buck cell. This active switch transfers the energy stored in the low frequency cell to the source during the transient stage of load step down. It works complementarily with high frequency cell switch S, and improves the transient response. The switch S is controlled to operate at high frequency fh, and the corresponding switching period is Tsh. On the other hand, the switch Sa is controlled to work at a low frequency fl, and the corresponding switching period is Tsl. Assume that high frequency is a multiple of low frequency, i.e., fh = M fl.

to the controller and the output of the controller is given to the inverting terminal of the comparator. The currents flowing through inductors L and La are sensed and given to the non inverting terminal. The output of the comparator is high when the positive input is higher than the negative input. When the positive input is lower, the output is zero. If the two input are equal, the output is undefined and it will keep the previous value. The output is given to the SR flip flop along with clock pulse to generate triggering pulse for switches. This control circuit does not need additional load transient information and hence the complexity of the control circuit is reduced. Fig.3 shows the voltage and current waveforms of main and auxiliary inductor. In the conduction mode of low-frequency switch, the voltage across the lowfrequency inductor La alternates between zero and Vdc. Thus, the equivalent slope of the current ILa is positive. At the switch-off interval, VLa varies from zero to −Vdc, the equivalent slope of ILa becomes negative. As a result, if we employ proper control method, the low-frequency inductor can be controlled to follow the output inductor current.

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III. SIMULATION

Figure 3(a). Voltage and current waveforms of main inductor.

Figure 2. Multi frequency converter with control circuit.

The current programmed mode control circuit used to control the proposed converter is shown in Fig.2. In the control circuit diagram the output voltage is fed back and compared with reference voltage. This error signal is fed

Figure 3(b). Voltage and current waveforms of auxiliary inductor.

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

A. Steady-State Performance Fig.4 shows the steady state response of multi frequency buck converter.

Fig.6 shows the step down transient response of proposed converter. The load current steps down from 100 A to 20A and so is the low-frequency inductor current iLa. At this moment, iLa can freewheel through SD when the switch S is off. When S is on, the energy stored in La can be fed back to the source via the switch S. C. Efficiency Analysis This section investigates the efficiency response of the proposed converter.

Figure 4. Steady state output voltage.

B. Transient Performance Analysis This section investigates the transient response of the proposed converter. Figure 7. Switch currents.

Figure 5. Load step up voltage and current waveforms.

Fig.5 shows the step up transient response of proposed converter. Here the load current jumps from 20 A to 100 A abruptly. Since the currents through inductor L and La cannot change suddenly, at this transient instant, the output voltage decreases due to the increased load current that is partially supplied by the output capacitor. The feedback control loop regulates the duty ratio of each buck cell to control the current of inductor L, iL, and the current of La, iLa. It increases the duty ratio of the high frequency switch so that iL rises. Then, iLa rises too. Moreover, the current through the high-frequency switch increases momentarily, but soon comes back to the steady state level due to the current feedback loop.

Figure 6. Load step down voltage and current waveforms.

The effect of switch current diversion of the highfrequency cell and the low-frequency cell is shown in Fig.7. The waveform with large magnitude denotes the current flowing through the low-frequency switch Isa, and the small magnitude is the current of the highfrequency switch is. A major portion of the increased load current is diverted to the low-frequency buck cell, while the current through the high-frequency switch remains the same. The current diversion enables the reduction of switching loss in high frequency buck cell and improves the efficiency. CONCLUSION This paper has presented a topology of Multi frequency buck converter for voltage regulator module for large loads and slew rates. The simulation of the Multi frequency buck converter module has been done and from the results it can be inferred that the efficiency is increased and also steady state and transient response voltage tolerance are within limits. REFERENCES [1] U. Borup, F. Blaabjerg, and P. Enjeti, “Sharing of nonlinear load in parallel-connected three-phase converters,” IEEE Trans. Ind. Appl., vol. 37, no. 6, pp. 1817–1823, Nov./Dec. 2001. [2] X. Zhou, P.-L. Wong, P. Xu, F. C. Lee, and A. Q. Huang, “Investigation of candidate VRM topologies for future microprocessors,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1172–1182, Nov. 2000. [3] P. Xu, J. Wei, and F. C. Lee, “The active-clamp coupleBuck converter-a novel high efficiency voltage regulator modules,” IEEE Appl. Power Electron. Conf. (APEC) 2001, Mar. 2001, vol. 1, pp. 252–257. [4] N. K. Poon, C. P. Liu, and M. H. Poon, “A low cost dc–dc stepping inductance voltage regulator with fast transient loading response,” IEEE APEC, 2001, pp. 268–272. [5] Xiong Du, Luowei Zhou, Heng-Ming Tai, “DoubleFrequency Buck Converter,” IEEE Trans.On Industrial Electronics 2009, vol. 56, no. 5,pp. 1690 – 1698.