Proc. of Int. Conf. on Recent Trends in Information, Telecommunication and Computing, ITC
Design and Performance Analysis of Low Power RF Operational Amplifier using CMOS and BiCMOS Technology A. Baishya1, Trupa Sarkar2, P. P. Sahu1 and M. K. Naskar3 1
Dept of ECE, Tezpur University, Assam, India. Email: anukul@tezu.ernet.in. 2 GDC Kamalpur, Dept of ETCE, Tripura, India. Email: trupa.sarkar@gmail.com. 3 Dept of ETCE, Jadavpur University, Kolkata, India
Abstract— This paper presents the design and performance comparison of a two stage operational amplifier topology using CMOS and BiCMOS technology. This conventional op amp circuit was designed by using RF model of BSIM3V3 in 0.6 µm CMOS technology and 0.35 µm BiCMOS technology. Both the op amp circuits were designed and simulated, analyzed and performance parameters are compared. The performance parameters such as gain, phase margin, CMRR, PSRR, power consumption etc achieved are compared. Finally, we conclude the suitability of CMOS technology over BiCMOS technology for low power RF design. Index Terms— RF CMOS, frequency response, unity gain, unity gain bandwidth, gain margin, phase margin.
I. INTRODUCTION The growing demand in low power and at the same time high performance design plays an important role and creates a challenging task in modern analog and mixed signal systems that are expected to operate at low supply voltages. Many low power applications require high performance op amp which is considered to be one of the most widely used circuit blocks. To design an op amp with wide input common mode range at low supply voltage, complementary differential pairs are usually required and the minimum supply voltage in this case is given by 4 + + | |. Potentially increasing requirement for reduced cost, less chip area, reduced power consumption and improved performance demand integration of mixed signal systems on the same die. Effort towards integration of this versatile circuit block started way back in 1960 [1], the µA 709 being the first integrated op amp. The power supply requirement for digital circuits is less compared to analog circuits and can be achieved by voltage scaling. Since threshold voltage ( ) does not scale down at the same rate as ( ), it results in reduced common mode range, output swing and linearity of the op amp. As the supply voltage decreases, it becomes increasingly challenging to maintain the transistors in saturation [2]. Therefore, the designers need to opt for low power design techniques to integrate analog circuit blocks along with digital circuits on a single chip using standard CMOS technology. Operational amplifiers based on CMOS technology with different levels of complexity are used to understand functions like dc bias generation, high speed DOI: 02.ITC.2014.5.72 © Association of Computer Electronics and Electrical Engineers, 2014