A 32-Stage 15-b b Digital Time Time-Delay Delay Integration Linear CMOS Image Sensor With Data Prediction Switching Technique
Abstract: This paper presents a 512-column column linear CMOS image sensor (CIS) with 32-stage 32 digital time-delay delay integration (TDI) operation. A signal processing architecture consists of analog-front-ends, ends, analog analog-to-digital digital converters (ADCs), and digital accumulators (DAs)) are designed with optimization of timing, area, and power efficiency. An eight-column column-shared 10-b b successive approximation register ADC with data prediction switching technique and 11 11-b b DA are proposed to achieve a data depth of 15 b after 32 32-stage TDI. The achieved signal-to-noise noise ratio boost is 14.84 dB after 32-stage stage TDI operation. The proposed linear TDI sensor is implemented in 0.11-μm μm TSMC backside illumination CIS technology with a line time of 104 μs, a pixel pitch of 7.5 μm, and a power consumption consumpti of 153.2 μW/column.