A 6-mW, 70.1-dB dB SNDR, and 20 20-MHz BW Continuous-Time Time Sigma-Delta Sigma Modulator Using Low Low-Noise High-Linearity Linearity Feedback DAC
Abstract: A 4-bit, third-order, order, continuous continuous-time time ÎŁA modulator is presented for use in wireless communications systems. Based on small small-signal signal noise models, analyses for reducing noise in the feedback digital digital-to-analog analog converter (DAC) are presented in detail. This enables les easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit circuit- and layout-level level design techniques for minimizing switching time mismatch mismatches es among and inside the DAC unit elements are presented. As a result, glitch glitch-induced induced harmonic distortion is greatly reduced, requiring only a simple data data-weighted weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to impl implement ement active-RC active integrators, the presented techniques make it feasible to design a highhigh performance ÎŁA modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm nm CMO CMOS technology, achieves a 72.6-dB dB dynamic range, a 70.7-dB dB peak SNR, and a 70.1 70.1-dB peak signal-to-noise noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 11 and 1.4-V V supply, of which analog and digital circu circuits its dissipate 4.5 and 1.5 mW, 2 respectively. The total active area is 0.058 mm .