GATE SOLUTIONS E L E C T R O N I C S AN D C O M M U N I CAT I O N
From (1987 - 2018)
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IES MASTER PUBLICATION F-126, (Lower Basement), Katwaria Sarai, New Delhi-110016 Phone : 011-26522064, Mobile : 8130909220, 9711853908 E-mail : info@iesmasterpublications.com, info@iesmaster.org Web : iesmasterpublications.com, iesmaster.org
All rights reserved. Copyright Š 2018, by IES MASTER Publications. No part of this booklet may be reproduced, or distributed in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without the prior permission of IES MASTER, New Delhi. Violates are liable to be legally prosecuted.
First Edition
:
2016
Second Edition :
2017
Third Edition
2018
:
Typeset at : IES Master Publication, New Delhi-110016
PREFACE It is an immense pleasure to present topic wise previous years solved paper of GATE Exam. This booklet has come out after long observation and detailed interaction with the students preparing for GATE exam and includes detailed explanation to all questions. The approach has been to provide explanation in such a way that just by going through the solutions, students will be able to understand the basic concepts and will apply these concepts in solving other questions that might be asked in future exams. GATE exam now a days has become more important because it not only opens the door for higher education in institutes like IIT, IISC, NIT's but also many of the PSUs have started inducting students on the basis of GATE score. In PSU’s, which are not inducting through GATE route, the questions in their exams are asked from GATE previous year papers. Thus, availability of authentic solutions to the students is the need of the day. Towards this end this booklet becomes indispensable. I am thankful to IES master team without whose support, I don't think, this book could have been flawlessly produced. Every care has been taken to bring an error free book. However comments for future improvement are most welcome.
Mr. Kanchan Kumar Thakur Director Ex-IES
CONTENTS 1.
Network Theory .......................................................................................... 01–126
2.
Signal and Systems .................................................................................. 127–230
3.
Electronic Devices ................................................................................... 231–310
4.
Analog Electronics .................................................................................... 311–448
5.
Digital Circuits .......................................................................................... 449–556
6.
Microprocessor ........................................................................................ 557–582
7.
Control Systems ....................................................................................... 583–706
8.
Communications ...................................................................................... 707–840
9.
Electromagnetics ..................................................................................... 841–972
10. Mathematics ........................................................................................... 973–1036 11. General Aptitude................................................................................... 1037–1074
1 Network Theory
UNIT
Syllabus Network solution methods : nodal and mesh analysis; Network theorem; superposition, Thevenin and Norton’s, maximum power transfer; Wye-Delta transformation; Steady state sinusoidal analysis using phasors; Time domain analysis of simple linear circuits; solution of network equations using Laplace transform; Frequency domain analysis of RLC circuits; Linear 2-port network parameters: driving point and transfer functions; State equations for network
CONTENTS 1.
Basics of Network Analysis ------------------------------------------------------ 01–26
2.
DC Transients and Steady State Response --------------------------------- 27–68
3.
Resonance ---------------------------------------------------------------------------- 69–77
4.
Network Theorems ----------------------------------------------------------------- 78–97
5.
Two Port Networks ---------------------------------------------------------------- 98–116
6.
Network Functions and Network Synthesis ----------------------------- 117–122
7.
Network Graphs ----------------------------------------------------------------- 123–126
1
Chapter
Basics of Network Analysis 4 I
1.
+ V2 –
A connection is made consisting of resistance A in series with a parallel combination of resistances B and C. Three resistors of the value 10 , 5 , 2 are provided. Consider all possible permutations of the given resistors into the positions A, B, C, and identify the configurations with maximum possible overall resistance, and also the ones with minimum possible overall resistance. The ratio of maximum to minimum value of the resistances (upto second decimal place) is __________
4.
R
R R
Rab
R
R
R R
R
R
(c) 15V, 35V
(d) 0V, 20V
In the circuit shown, the switch SW is thrown from position A to position B at time t = 0. The energy in J taken from the 3V source to charge the 0.1 F capacitor from 0V to 3V is SW
A
0.1F
(a) 0.3
(b) 0.45
(c) 0.9
(d) 3 [GATE 2015]
R=300 R
5.
In the circuit shown, the average value of the voltage Vab (in Volts) in steady state condition is _____
b
1k
[GATE 2015] 3.
B
120
R R
R
(b) 10V, 30V
t=0
a R
+ V1 –
(a) 5V, 25V
+3V
In the network shown in the figure, all resistors are identical with R 300 . The resistance Rab (in ) of the network is _____.
R
4
[GATE 2015]
[GATE 2017] 2.
2I 4
5A
In the given circuit, the values of V1 and V2 respectively are
+ –
b
1F Vab
5sin(5000t )
a
1mH
2k + –
5V
[GATE 2015]
NETWORK THEORY 6.
3
At very high frequencies, the peak output voltage V0(in Volts) is _____
(c) Data is sufficient to conclude that the supposed currents are impossible. (d) Data is insufficient to identify the currents i2, i3 and i6. [GATE 2014]
100 F +
1k
100 F
+ –
1.0sin(t)V
10.
V0
1k
In the figure shown, the value of the current I (in Amperes) is ______.
–
5
5 I
1k
1k
5V
100 F
1A
10
[GATE 2014]
[GATE 2015] 7.
In the circuit shown, the voltage Vx (in Volts) is _____
11.
The circuit shown in the figure represents a
0.5V X
Ii
A1Ii
R
10 +
VX 20 –
A
8
(a) voltage controlled voltage source
0.25VX
(b) voltage controlled current source [GATE 2015]
8.
(c) current controlled current source
The magnitude of current (in mA) through the resistor R2 in the figure shown is ____.
(d) current controlled voltage source [GATE 2014]
R2
12.
1k R1
10mA
R 3 4k
2k
2mA
R4 3k
Consider a delta connection of resistors and its equivalent star connection as shown below. If all elements of the delta connection are scaled by a factor k, k > 0, the elements of the corresponding star equivalent will be scaled by a factor of
[GATE 2014] 9.
Rb
RA
i2 R
i1
(a) k2
(b) k
(c) 1/k
(d)
k
[GATE 2013]
i3
R
i4
RB
Rc
i5
R
RC
Ra
Consider the configuration in the figure which is a portion of a larger electrical network.
13. i6
For R 1 and currents i1 2 A , i4 = –1 A,
The average power delivered to an impedance 4 j3 by a current 5cos 100t 100 A is
i5 = –4A, which one of the following is TRUE ?
(a) 44.2 W
(b) 50 W
(a) i6 = 5 A
(c) 62.5 W
(d) 125 W [GATE 2012]
(b) i3 = –4A Regd. office : F-126, (Upper Basement), Katwaria Sarai, New Delhi-110016 Mob. : 8010009955, 9711853908
Phone : 011-41013406
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NETWORK THEORY
11
22.
(a)
13.
(2.618)
(2.14)
23.
(b)
14.
(c)
(100)
24.
(c)
15.
(d)
3.
(a)
25.
(b)
16.
(c)
4.
(c)
26.
(a) (d)
(a)
(5)
27.
17.
5.
(a)
(a)
(0.5)
28.
18.
6. 7.
(8)
29.
(d)
19.
(c)
8.
(2.8)
30.
(a & d)
20.
(b)
9.
(a)
2 Marks
21.
(a)
10.
(0.5)
1.
(8.00)
22.
(None of these)
11.
(c)
2.
(a)
23.
(d)
12.
(b)
3.
(1)
24.
(d)
13.
(b)
4.
(d)
25.
(d)
14.
(a)
5.
(5) (–1A)
(d)
(c)
6.
26.
15. 16.
(a)
7.
(1.5)
27.
(b)
17.
(d)
8.
(20)
28.
(b)
18.
(a)
9.
(29.09)
29.
(d)
19.
(c)
10.
(2.504)
30.
(a)
20.
(a)
11.
(10)
(d)
12.
(0.4083)
1 Mark 1. 2.
21.
3 Marks 1.
(c)
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12
GATE SOLVED PAPER 1987-2018
Solutions [Here, branch ‘pqrs’ is removed as no current flows through it, because it forms a balanced bridge]
Sol–1:
Req = 2R 2R R R
A
= R R R Sol–3: B
(a)
C
4
x
+ V2
Resistor are 2, 5 and 10 For maximum resistance B = 2, C = 5, A = 10
Rmax (80 / 7) = Rmin (16 / 3)
V1 5 4 V2 = 0
(100) R R
R R
R
Sol–4:
R
R R
x 4I
x V1
Now,V1 = 5V
= 2.14
R eq
R
R
R
[KVL in the outermost loop] V2 = 5 + 5 × 4 = 25 V (c) Initially capacitor is uncharged. For t > 0, the circuit will be :
R
120 3V
(R=300 )
i(t)
R C
R R eq
R/2 R
R
p
R
R/2
s
R
R/2
Current in RC circuit while charging is given by : i(t) =
R eq
2R
R
R
0.1 F
R
R/2 R r
q
V1 –
x x 2I 4 4 2x x 2 5 = 4 4 x = 5
16 3
RR
4 2I
4
5 =
A = 2, B = 5, C = 10
R
5A
+
(1)
Applying nodal analysis at node (1), we get
80 7 for minimum resistance,
Sol–2:
I
–
Rmax =
Rmin =
R = 100 3
2R
V0 t/RC e where V0 = 3V R
Power delivered by the source = P = 3i(t)
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NETWORK THEORY
13 t
By voltage division rule
t
Also, Energy = Pdt 3i t dt 0
0
Capacitor gets fully charged at steady state i.e t . V0 t/RC dt E = 3. e R 0 3V0 1 t/RC = R 1 RC e 0
0.5 V 0.5 0.5
V0 =
V 2
V0 =
1 1.0sin t 2
V0 = 0.5sin t
0
V0 =
= 3V0C e e = 3 3 0.1 0 1J
V0 peak Sol–7:
= 0.5 Volts
(8)
E = 0.9 J Sol–5:
0.5V X
(5) • For AC input voltage 5 sin 5000t , voltage across capacitor (C) at steady state is also sinusoidal, whose average value is zero. • For DC voltage = 5V, at steady state capacitor behaves as open circuit and inductor behaves as short circuit, therefore circuit is b
1K
8 0.25VX
Apply KCL at point P Vx Vx 0.25Vx 0.5Vx 5 20 10
1 75 1 Vx 5 20 1000 2
5V
Vab=5V
Sol–6:
20
–
2K
Average value of voltage across capacitor is Vab = 5V. (0.5) At very high frequencies, capacitor behaves as short-circuit. 1 XC = jC When , X C 0[short circuit] When all capacitors are replaced by short-circuit.
VX
5A
a
–V + ab
1K
10
P +
3 1 1 Vx 5 20 40 2 2 3 20 Vx 5 40
Sol–8:
1 K V0
5 Vx 5 8 Vx = 8 Volts (2.8) Transforming current sources into voltage sources, we get 1k
1.0sin(t) 1K
2k
1K
20V + – 0.5 K V0
4k i
8V
3k
1.0sin( t) V
i =
0.5K
20 8 = 2.8 mA 2 1 4 3 k
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