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ISSN (ONLINE): 2454-9762 ISSN (PRINT): 2454-9762 Available online at www.ijarmate.com

International Journal of Advanced Research in Management, Architecture, Technology and Engineering (IJARMATE) Vol. 2, Issue 3, March 2016

Implementation of Congestion Aware Routing Algorithm Using For NoC Benila Arockia Selvi. A1, Sugapriya. R2 P.G.SCholar, Department of ECE, Vandayar Engineering College, Thanjavur, India1 Assistant professor, Department of ECE, Vandayar Engineering College, Thanjavur, India 2 3

Abstract— The process variation (PV) on delay is a major reason to collapsed the performance in advanced technologies. The performance of different routing algorithms is determined with/without PV for various traffic patterns. The saturation throughput, congestion and average message delay are used as performance metrics to evaluate the throughput. PV increases the average message delay by up to 90% and decreases the saturation throughput by up to 29% compared with nominal characteristics of different routing algorithms. Global routing algorithm is proposed for asynchronous network-on-chip design. Global routing is adaptive, low cost, and scalable. The global routing algorithm outperforms different adaptive routing algorithms in the average delay and congestion for various traffic patterns. Global routing can achieve up to 12%–32% average message delay lower than that of other routing algorithms. Moreover, the proposed scheme yields improvements in saturation throughput by up to 11%–82% compared with PDCR routing algorithms.

Index Terms— Asynchronous design, PDCR Algorithm, congestion, delay, network on chip (NoC), process variation (PV), global routing algorithms

I. INTRODUCTION International Technology Roadmap for Semiconductors presents the process variation (PV) parameters as a critical challenge for IC manufacture [1]. Systematic and random variations are two sources for PV [2]. With technology scaling down, random variation becomes significantly larger than systematic variation [3]. Random variation appears in logic gates and interconnects. The impact of random PV emerged on

low and high levels of designs. One of the key factors of designing network on chip (NoC) is the routing algorithm. An efficient routing algorithm is required to achieve high performance. Hence, ignoring the impact of PV during the design of any routing algorithm results in unexpected average message delay and saturation throughput. Average message delay and saturation through-put are used as two metrics to evaluate the performance of a routing algorithm. The saturation throughput occurs when no additional messages can be injected successfully to the network [4].

However, the average message delay increases exponentially beyond the network saturation [4], [5]. As a hardware solution, a new router design is proposed to mitigate PV impact [6]. In [7], a variation-adaptive variable-cycle router configures its cycle latency adaptively corresponding to the spatial PV to increase the network frequency in the synchronous network. Adaptive routing algorithm for multicore NoC architectures is presented in [8] to reduce saturation bandwidth degradation caused by PVs. In [9], source routing algorithm is introduced to enhance the speed of the communication in a NoC based on the PV.

Fig. 1. Asynchronous design with the RCU block.

To the best of our knowledge, the work presented in this paper is the first work to investigate the impact of PV on different routing algorithms. Moreover, an adaptive routing algorithm that is aware of the PV and congestion for asynchronous NoC designs is introduced in this paper. In this paper, a novel adaptive routing algorithm is proposed for asynchronous NoC designs to reduce the effect of PV. The presented algorithm is applicable with any source of PV. The technique is insensitive to the source of the variation. The novel routing algorithm uses the PV and congestion information as metrics to select the suitable output port (OP), as shown in Fig. 1. This paper is organized as follows. In Section II, PV in asynchronous NoC design is determined. The novel routing algorithm is described in Section III. Circuit-level implementation for asynchronous routers is used to analyze the delay of NoC router with/without PV as described in Section IV. In Section V, simulation results are provided. Some conclusions are demonstrated in Section VI.

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