Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
D-Flip Flop Layout: Efficient in Terms of Area and Power Vaishali Kamboj Department of ECE, National Institute of Technical Teachers’ Training & Research Chandigarh, India kamboj.vaishali06@gmail.com
Abstract: Flip flop forms the very basic element for the sequential circuits which are synchronous. This paper talks about D-Flip flop, which has been made area and power efficient with the aid of software tools DSCH 3.1 and Microwind 3.1. D-flip flop is implemented through Nand gates. Layout of DFF designed through auto generated and semi custom is compared, analyses and finally the results are computed showing 57% improvement in area and approximately 2 % reduction in power. CMOS 90nm technology has been used and efforts are made to reduce area and power.
DFF is an interesting device used extensively for data storage. Edge triggered DFF loads on the edge of the clock waveform, usually the rising edge and locks out the effects of any further changes at the D-input until the next rising edge [6]. That is why it is commonly named as delay FF. they can be interpreted as a delay line or zero order hold [7]
Keywords: Flip Flop, layout, CMOS technology
1. INTRODUCTION Due to intensive use of memory storage elements and sequential logic in modern electronics, there is a need for high performance and low area implementation of basic memory components. One of the most important state holding devices is D-Flip Flop or DFF [1]. Incase of CMOS technology, area, power dissipation and speed are vital elements regarding clocked storage elements for high speed and low energy designs like portable batteries and microprocessors [2]. Power in a CMOS VLSI circuits is consumed during switching (during transistor being switched), short circuit power (during short circuit of transistor while switching) and static power (due to static and leakage currents flowing to keep the circuit in stable state) [3]. CMOS technologies such as 90nm and 45nm have shown that half of the power consumption is due to leakage currents and incase of 90nm, leakage power is 35 % of chip power. So, it becomes necessary to reduce power if it is to be used for portable devices [4]. Implementing designs with reduced area is also a prior requirement of modern world scenario. As the area of silicon chip increases so, is the cost. Reduction in area results lesser power consumed due to fewer components on chip. There are various technologies like NOC (network on chip) needs to be implemented with lesser area. NOC is a general purpose on chip communication concept [5]. There is a need for area and power reduction. So, comparison between auto generated and semi custom layout designs will be made. CMOS 90 nm technology is used. . 2. D- FLIP FLOP NITTTR, Chandigarh
EDIT -2015
Fig 1. D-Flip Flop
D input of the FF must get settle by some setup time (tsetup) before the rising edge of the clock and should not change again until a hold time (thold) after the clock edge [8]. DFF have two inputs namely D and a clock, followed by two outputs Q and Q bar as shown in Fig1. Table 1-DFF truth table D
CLOCK
Q
Q bar
X
0
No change
No change
0
1
1
0
0 1
↑ ↑
Truth table of DFF is shown in Table 1, where X represents a don’t care. Output is produced only on the rising edge of the clock. Whenever there is no clock, there is no change in the output.
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Fig 2. DFF Schematic
The schematic shown above in Fig 2 requires switches and LED’s for input and output respectively. For hardware implementation, it requires four 2-input NAND gate and one inverter.
Fig.4- DFF output
Above Fig 4 shows the input and output waveform of DFF. Here, clk1 is taken as D while clk2 is used as clock. It is edge triggered. 3. Layout Design and Simulation For the layout, DFF is auto generated. After simulation in DSCH 3.1, Verilog file is automatically generated and is further used in Microwind 3.1 for layout generation and we get an auto generated DFF.
Fig.3- DFF using CMOS
Fig.5- Auto generated layout of DFF
The circuit is implemented using CMOS, using N-MOS and P-MOS; it has been shown in Fig 3. Again switches and LED’s are used for inputs and output respectively. This circuit is designed in DSCH 3.1. DSCH 3.1 provides a user friendly environment for logic design and fast simulation, which allows the validation of logic structures. DSCH 3.1 software has been used to design CMOS logic structure of DFF and simulate it too.
Area occupied by auto generated DFF is 146.3 µm2, where width and height of layout is 20.9 µm and 7.0 µm respectively and it is shown in Fig 6. Power consumed is 12.567 µW. Semi custom layout of DFF is designed. Microwind 3.1 is a tool for designing and simulating circuits at layout level. With the help of already available libraries, a semi custom DFF is designed. Efforts are made to compact the design so that it is area efficient and takes less power.
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NITTTR, Chandigarh
EDIT-2015
Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Area
146.3µm 2
62.6µm 2
Power
12.567µW
12.337µw
Analysis shows that semi custom generated DFF is area and power efficient. 5. CONCLUSION DFF has been a basic device of almost all circuits used to implement low and high level logic functions. These are data storage elements which operate only with the clock. There is a need for the implementation of DFF efficiently in terms of area and power, as most of the modern devices are potable and battery operated. With the semi custom design of DFF there has been almost 57% reduction in area and lesser decrease in power with approximately 2 % decrease. Semi custom DFF layout design is more preferable.
Fig.6- Semicustom layout of DFF
REFERENCES The above Fig 6 layout is designed in Microwind 3.1. area consumed by above circuit is 62.6 µm2 having width and height as 6.5 µm and 9.7 µm respectively. In terms of area above circuit has advantage over auto generated. Power consumed is 12.337µW.
Fig.7- Waveform of DFF for semicustom design
Now the comparison between the two technologies used is made and shown in the tabular form. Table 2- Comparison in terms of Power and Area Layout/ Parameters
Auto generated
NITTTR, Chandigarh
Semi custom
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[1] Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner, “An Efficient Implementation Of D-Flip-Flop Using The Gdi Technique”, IEEE Circuits and systems, Vol. 2, pp. II - 673-6, May 2004. [2] R. Uma, “Flip-Flop Circuit Families:Comparison of Layout and Topology for Low Power VLSI Circuits”, International Journal Of Engineering Research and Applications, Vol. 1, Issue 4, pp.19711982, Nov-Dec 2011. [3] Amit Grover, Sumer Singh, “D Flip Flop with Different Technologies”, Natural Sciences Publishing, Advanced Engineering And Technology, Vol 3, No. 1, pp 1-6, January, 2014. [4] Kavita Mehta, Neha Arora, Prof B. P singh, “Low Power Efficient D Flip Flop Circuit”, International Journal of computer Application, Number 8, pp. 16-19, October 2011. [5] Sudhir N. Shelke, Pramod B. Patil, “Power & Area Efficient Router in 2-D Mesh Network-on-Chip Using Low Power Methodology Clock Gating Techniques”, International Journal of Hybrid Information Technology, Vol. 5, No. 3, pp. 105-122, July 2012. [6] William I. Fletcher, “An Engineering Approach to Digital Design”, Pearson Education, (1980). [7] M.Arunlakshman, “Power and Delay Analysis of Double Edge Triggered D-Flip Flop based Shift Registers in 16nm MOSFET Technology”, Vol. 3, Issue 4, pp. 8560- 68, April 2014. [8] Neil H. E. Westie, David Harris, AAyan Banerjee, “CMOS VLSI Design: A Circuits and Systems Perspective, 3 rd Edition”, Pearson Education, (2005).
Author Vaishali Kamboj is currently pursuing ME in Electronics & Communication from National Institute of Technical Teachers’ Training & Research, Panjab University, Chandigarh. She has completed B.tech degree in Electronics & Communication from Government Women Engineering College, Ajmer, Rajasthan India in 2014.
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