IJIRST –International Journal for Innovative Research in Science & Technology| Volume 4 | Issue 1 | June 2017 ISSN (online): 2349-6010
Comparative Analysis of Proposed Parallel Digital Multiplier with Dadda and other Popular Multipliers Vikas Kaushik M. Tech. Scholar Department of Electronics and Communication Engineering Deenbandhu Chhotu Ram Univ. of Science and Technology, Murthal
Himanshi Saini Assistant Professor Department of Electronics and Communication Engineering DCRUST, Murthal
Abstract There are mainly four series of Parallel Digital-Multipliers: Array, Vedic, Booth and Wallace series of multipliers. In this paper, a multiplier is proposed. This proposed multiplier has better performance than the other four types of series of multipliers. The proposed multiplier is actually a modified version of Wallace and Dadda multipliers. This paper presents a comparison of the proposed multiplier with these four types of series of multipliers. From each series, one multiplier which is the best among its series is selected for comparison by doing literature review of that series of multiplier. The comparison is in terms of delay, power and area. The selected multipliers with the proposed multiplier are implemented on front-end modeling using Verilog-HDL. For simulation, Modelsim is used and for synthesis and implementation Vivado is used. The target technology used for implementation is the FPGA, Z-board (xc7z020clg484-1). Keywords: Digital Multiplier, Parallel Multiplier, Dadda Modification, Wallace Modification, FPGA Implementation, Multiplier Comparison, Array, Vedic, Booth _______________________________________________________________________________________________________ I.
INTRODUCTION
Parallel multipliers have more speed than serial multipliers [9]. By doing literature review, it is obvious that followings are the best multipliers among their particular series of multipliers: 1) Vedic multiplier using look ahead carry adder, 2) Booth radix4 multiplier, 3) Reduced Complexity Wallace and 4) Dadda multiplier. The Array multiplier is selected for reference purposes. A multiplier with novel technique of partial products reduction is proposed here. This multiplier with the other five multipliers is simulated on Modelsim and it is synthesized and implemented on Vivado with a target FPGA Z-board. The parameters for comparison are 1) total power (dynamic and static) consumed, 2) maximum delay taken by the slowest path and 3) number of hardware units used by the implemented design. This comparison provides an idea about a suitable selection of a multiplier for a particular task. Array Multiplier It is a conventional multiplier and having the most regular structure [6]. The partial products are generated by ANDing each bit of multiplier number with the all bits of multiplicand number. However, the process of generating and shifting partial products is the same in most of the multipliers. After generating partial products and arranging them by one place left shift according to the place value of multiplier number-bit which is used for ANDing operation, there is a need of summation of these partial products which is done by any of the Carry propagation adder [6]. However, in this paper, the most simple array multiplier is selected that is array multiplier with ripple carry adder. Fig.1 shows the simple arrangement of the partial products in 4x4 multiplications. Vedic Multiplier These multipliers are based on ancient Vedic mathematics. Urdhava Trigbhyam sutra is one of the sixteen sutras in Vedic mathematics [3]. In vedic multiplication as the size increases, delay and area will not increases directly proportional but with lesser rate in Urdhava multiplication as compared to the other technique mentioned in vedic math [3]. The multiplier in this paper is the Urdhava with carry look-ahead adder. Booth Radix4 multiplier Booth multiplier can be use uniformly for positive as well as negative numbers multiplication [1]. It is a multiplier with powerful algorithm for signed multiplication. An n-bit binary number can be represented as n/2 or n/3 or n/4 and so on. For n/2 representation radix4 and for n/3 radix8 multiplier is made. For signed multiplication there is variable number of shift and add operations which makes designing of parallel multipliers difficult. The radix4 multiplier eliminates all these difficulties [1][2]. The radix4 booth
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Comparative Analysis of Proposed Parallel Digital Multiplier with Dadda and other Popular Multipliers (IJIRST/ Volume 4 / Issue 1/ 040)
multiplier has better values to the desired parameters than that other multipliers have. For example, it has less delay, less power consumption and less area in comparison to others [8]. Reduced Complexity Wallace Multiplier Among various designing techniques for multipliers the wallace tree technique is superior [5]. The RC Wallace multiplier is the modification in Conventional Wallace multiplier. The number of half adders is greatly reduced in this multiplier. The reduction technique is similar to the conventional Wallace except few points; for example, partial products are arranged in inverted pyramid and half adders are used only where there is a need of reduction of number of bits in column and the remaining bits in that column are only two [4]. This technique of partial product reduction is shown in fig.2(a). Dadda Multiplier Dadda multiplier is also a tree multiplier and uses same number of stages as in Wallace multiplier [7]. However there is difference between the two because Dadda’s algorithm focuses in doing minimum reduction which are necessary at a level. The general assumption about Dadda and Wallace multiplier was that they are equally fast. But Dadda multiplier is slightly faster and has less area than that of Wallace multiplier [7]. The detailed of this technique for partial product reduction is shown in fig.2(b).
Fig. 1: General Multiplication scheme
Fig. 2: (a) RC Wallace Tree Reduction
Fig. 2: (b) Dadda reduction
Fig. 2: RC Wallace and Dadda techniques for partial products reduction
CPA= Carry Propagation Adder
Half adder
full adder
bit
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Comparative Analysis of Proposed Parallel Digital Multiplier with Dadda and other Popular Multipliers (IJIRST/ Volume 4 / Issue 1/ 040)
II. THE PROPOSED MULTIPLIER The proposed multiplier is the hybrid structure of Dadda and Wallace multiplier and it shows improvement in terms of delay, power and area on post-synthesis analysis. The main difference lies in the partial products reduction technique. The partial products first are arranged in reverse pyramid structure. After that the reduction rules should be applied. In this technique of partial product reduction, the main rules are 1) Count the number of bits in a column and use full adders to reduce the number of bits as much as possible. This rule will apply only on a column which has more than two bits. Because it is a condition for the use of the full adder that there will be at least three bits in a column. 2) Use of half adders should be only in two following conditions: ď€ To reduce right most column having two bits only and ď€ To maintain number of bits in a column according to Wallace table, where only two bits are remaining for further reduction. The final CPA(carry propagation adder) plays a very important role in determining the area, power and especially delay taken by a multiplier to give final output. The proposed multiplier uses the least size of CPA that is of 4 bit. Table1 is clearly showing that the dadda and RC wallace multipliers use 6 bit final CPA. This is one of the main advantage of the proposed multiplier. The detailed pictorial arrangement of this technique is shown in fig.3.
Fig.3 Proposed Partial Product Reduction Technique
4x4 multipliers Size of final CPA
Table - 1 Size of Final Carry Propagation Adder RC Wallace multiplier Dadda multiplier 6 bit 6 bit
Proposed multiplier 4 bit
III. RESULTS AND DISCUSSION The six multipliers are modeled by using Verilog-HDL. These are simulated on software Modelsim. After that synthesis is done on software Vivado. The final step is the implementation of the multipliers on the target technology. The target technology here is the FPGA Z-board, xc7z020clg484-1. The measurement of parameters of implemented designs has been done. There are mainly three parameters which are analyzed here: (1) total power (dynamic and static) consumed, (2) maximum delay taken by the slowest path and (3) number of hardware units used by the implemented design. The detailed results are tabulated in the table 2. RCA=> ripple carry adder, CLA=> carry look-ahead adder, RC Wallace=> Reduced Complexity Wallace. 4x4 multipliers Array Multiplier using RCA Vedic Multiplier using CLA Booth Radix4
Table - 2 FPGA implementation results for various multipliers AREA Power-Area Product(PA) DELAY (ns) POWER (W) Slice LUTs
Delay-Area Product (DA)
10.935
5.305
26
137.93
284.310
8.978
4.014
19
76.266
170.582
8.458
3.729
21
78.309
177.618
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Comparative Analysis of Proposed Parallel Digital Multiplier with Dadda and other Popular Multipliers (IJIRST/ Volume 4 / Issue 1/ 040)
Multiplier R C Wallace Multiplier Dadda Multiplier Proposed Multiplier
9.399
4.193
18
75.474
169.182
9.442
4.099
17
69.683
160.514
9.340
3.919
17
66.623
158.78
As it is clear from the above table that however the Vedic and Booth multipliers have less delay and less power consumption but area is large. For the low area and moderate levels of delay and power consumption, the proposed multiplier is the most suitable among these. This conclusion can be made on the basis of power-area and delay-area product values in the table. IV. CONCLUSION The proposed multiplier is the best by taking overall performance into account. The reason for this improvement in the performance of the proposed multiplier lies in these facts: different reduction technique for the partial products reduction before the final sum and the reduced size of final sum adder. This comparison also provides a detail to take decision about the choice of the particular multiplier for a task. For future work, this multiplier can be used in bigger calculating units to improve the performance of these units. REFERENCES [1] [2] [3]
[4] [5]
[6] [7] [8] [9]
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