Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology by IJMTST-International Journal for Modern Trends in Science and Technology (ISSN:2455-3778)

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International Journal for Modern Trends in Science and Technology ISSN: 2455-3778 :: Volume: 03, Issue No: 10, October 2017

Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology V.Sree Vani1 | V.Lavanya2 1Assistant

Professor, Department of ECE, Godavari Institute of Engineering and Technology, Rajahmundry, Andhra Pradesh, India. 2PG Scholar, Department of ECE, Godavari Institute of Engineering and Technology, Rajahmundry, Andhra Pradesh, India. To Cite this Article V.Sree Vani and V.Lavanya, “Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology”, International Journal for Modern Trends in Science and Technology, Vol. 03, Issue 10, October 2017, pp: 145-151.

ABSTRACT The use of XOR–XNOR circuits has been the topic of numerous reports in the form of full adder circuits, compressors, parity checkers and comparators. In most of these systems, XOR/XNOR gates constitute a part of the critical path of the system, which significantly affects the overall performance of the system. An optimized design is desired to avoid any degradation on the output voltage, consume less power, and have a less number of transistors to implement the circuit. Two different designs for 3-input exclusive-OR (XOR) function at transistor level with a systematic cell design methodology (SCDM) are proposed in this paper. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. The proposed designs have low dynamic and short-circuit power consumption and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. These designs are used to improve the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. In this paper, we designed three input XOR/XNOR circuits by using MICROWIND/DSCH 180 nm technology and simulation results obtained by using HSPICE 180 nm technology. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and transistor count with respect to other designs. Keywords — 3-input XOR/XNOR circuits, power consumption, propagation delay, SCDM Copyright © 2017 International Journal for Modern Trends in Science and Technology All rights reserved. I. INTRODUCTION Circuit realization for low power and low area has become a paramount issue with the magnification of integrated circuit towards very high integration density and high operating frequencies. Due to the paramount role played by XOR and XNOR gate in different circuits especially in arithmetic circuits, optimized design of XOR and XNOR circuit to achieve low power, small size and delay is needed. The primary concern to design XORX/NOR circuit is to acquire full yield output voltage swing and low

number of transistors to execute it. This paper makes use of the concept of SCDM technique for the designs of three input XOR/XNOR gate. [1]The SCDM considers circuit optimization based on our target in three steps: 1) wise selection of the basic cell; 2) wise selection of the amend mechanisms; and 3) transistor sizing. It should be noted that BDD can be utilized for EBC generation of other three-input functions. It stands as a fair performance metric, precisely involving portable electronic system targets. The motivation to use this methodology is the presence of some unique

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V.Sree Vani and V.Lavanya : Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology features and the ability to produce some efficient circuits that enjoy all these advantages. 1) The SCDM divides a circuit structure into a main structure and optimization-correction mechanisms. In the main structure, it considers features including the least number of transistors in critical path, fairly balanced outputs, being power ground-free, and symmetry. The mechanisms have the duty of completing the functionality of the circuits, avoiding any degradation on the output voltage, and increasing the driving capability. 2) The least number of transistors in critical path increases the chances of the circuit to have better characteristics, as experimental results have shown an average saving of 10% –50% and 27%–77% in terms of delay and Energy-Delay Product (EDP), respectively. 3) The dynamic consumption optimization comes from the fact of well-balanced propagation delay. This feature is advantageous for applications in which the skew between arriving signals is critical for proper operation, and for cascaded applications to reduce the chance of making glitches [3]. 4) Power-ground-free main structure leads to power reduction. 5) Symmetrical structure, high modularity, and regular arrangement of designs give rise to sharing more wells of connected transistors and in turn reducing the occupied area about 26% –32%. 6) The degradation in all output voltage swing can thus be completely removed, which makes the design sustainable in low VDD operations and low static power dissipation. The well-organized systematic methodology leads to automated flow, which can reduce design time and costs, provide consistency in the cell library generation process, increase the range of simulation capabilities at the characteristics step, as well as minimize the risk of errors [12], [13]. In this paper, we propose new designs of XOR-XNOR gate. The paper is organized as follows: in Section II, previous work is reviewed. Subsequently, in section III, the proposed design of XOR-XNOR gate is presented. In section IV, the simulation results are given and discussed. Finally a conclusion will be made in the last section. II. PREVIOUS WORKS [1]In this section, the methodology for three-input XOR/XNORs is presented according to the flowchart shown in Fig. 1(a). The design path is started by EBC systematic generation. In this step, general design goals are considered that the most

distinctive ones are generating fairly balanced outputs, symmetric and power-ground-free structure, fewer transistors in the critical path, as well as sharing common sub circuit. Systematic generation process of EBC in details is discussed in Section II-A. In the remaining steps, the methodology offers opportunity to strive toward an assigned design target. Two of these steps include wisely selection of mechanisms and basic cells from PDP point of view. An in-depth analysis for the selection in terms of PDP is presented in section II-B. In the last step, in order to put the resultant circuits in proper state, a sizing algorithm consistent with the methodology is indispensable. In this line, SEA algorithm that is simple exact algorithm with the capability of determining goal is picked [1].

Fig.1 (a) SCDM process for designing efficient three-input XOR/XNORs. (b) BDT representation of three-input XOR/XNOR function. (c) Applying reduction rules. (d) Substitution and disjointing. (e) EBC.[1]

A. Elementary Basic Cell Systematic Generation In order to generate the EBC of three-input XOR/XNOR circuits, four steps is taken. The process has been shown in Fig. 1(b)–(e). Initially, three-input XOR and its complement are represented by one binary decision tree (BDT)[1] in order to share common sub circuits. The BDT is achieved by some cascaded 2 × 1 MUX blocks, which are denoted by simplified symbol controlled with input variables at each correspondent level. This construction simply implements the min-terms of the three-input XOR/XNOR function, as shown in Fig. 1(b). The step is followed by applying reduction rules to simplify the BDT representation. These include elimination, merging, and coupling rules. The major task of the coupling rule, in simple terms, is to obtain all the possible equivalent trees by interchanging the order of the controls. The trees are acquired by

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V.Sree Vani and V.Lavanya : Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology impacting the state matrix on the corresponding control matrix where the multiply and add operators operate as follows:

The result of applying the reduction rules to the tree is shown in Fig. 1(c). Afterward, as the inputs into the ﬁrst level are 0‘s and 1‘s of the function‘s truth table, the 0 and 1 can be replaced by the Y and Y‘, respectively. Finally, the simpliﬁed symbol can be divided into two distinct symbols: 1) the plus sign with the x input control and 2) the minus sign with the x‘ input control. The result of applying steps 3 and 4 is shown in Fig. 1(d). The EBC, which is extracted from the above procedure, has been presented in Fig. 1(e). This cell has eight elements, deciding two outputs. We refer to the pins of the central section (IN1–IN4 and G1–G4) as A or C, or their complements. We also assume that pins of the external section G5–G8 can also be B or its complement. B. Wisely Selection of Mechanisms and Cells Based on Design Target By replacing the elements with pass transistors or transmission gates and the control inputs with input signals in combination with optimization and correction mechanisms, a huge circuit library is achieved as each circuit can be appropriate for specific applications. The selection is meditated to determine dominant mechanisms and cells, in terms of PDP, power, and delay when the optimization goal is PDP. The results are used to produce Circuits for high-performance portable electronic applications. Mechanisms include optimization mechanisms to resolve non-full swing [inverter (I) and feedback (F)], correction mechanisms to resolve high impedance [pull up-down network (P) and feedback (F)], or the combinations of them [bootstrap-pull (BP) up-down, feedback pull (FP) up-down, bootstrap-feedback (BF), inverter-feedback (IF), and inverter-pull (IP) up-down]. The cells are divided into three categories: 1) cells with both NMOS and PMOS in EBC structure (C1); 2) only NMOS (C2); and 3) only PMOS (C3). To reduce complexity, we have also considered the central part of EBC and to achieve real results, the circuits have been simulated in the chain test bench [8]. By using this method three 3 input XOR/XNOR circuits are designed using HSPICE simulation based on TSMC 0.13-µm technology. Which are shown below.

Fig. 2 three input XOR/XNOR circuit

This circuit consist of two parts one is central part and another one is external part. Central part consists of four transmission gates which is connected in such a way that it gives the XOR/XNOR output of two inputs. And the external circuit consist of four transmission gates. This part takes the output of central part output as one input and the other one is direct input. The total output of the circuit can collect at external part which is three input XOR/XNOR output. As XO4 was designed using transmission gate technology for both external and internal part. It doesn‘t show any voltage degradation in their output.

Fig. 3 three input XOR/XNOR circuit

This circuit is similar to the XO4 but the difference in external part i.e., instead of transmission gates here we are used PMOS and NMOS transistors. As same in XO4 we can collect the output at external part which is three input XOR/XNOR output. As XO7 was designed using transmission gate technology for internal part and Pull-up, pull-down network technology for external part. It shows some voltage degradation in their output.

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V.Sree Vani and V.Lavanya : Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology

Fig. 4 three input XOR/XNOR circuit

Here also the difference is same as XO7 i.e., the mechanism of the external part. Here we can collect the output at external part. As XO10 was designed using transmission gate technology for internal part and Pull-up, pull-down network technology for external part. It shows some voltage degradation in their output. In this design, XOR operation is performed for two input data and the output of the resultant output is fed to similar circuit resulting into output of two input XOR gate and third input by which the final output will be three input XOR gate. In the above design PMOS and NMOS are connected such that the total numbers of transistors used are less compared with a conventional design. Despite the saving in transistor count, the output voltage level is degraded at certain input combinations. And also due to irregular arrangement of CMOS devices the power drawn is comparatively high. And also Critical path is very high such that power consumption is generally high. The reduction in voltage swing, on one hand, is beneficial to power consumption. On the other hand, this may lead to slow switching in the case of cascaded operation. The performance of the complex logic circuits is affected by the individual performance of the XOR/XNOR circuits that are included in them. Therefore careful design and analysis is required for XOR/XNOR circuits to obtain full output voltage swing, lesser power consumption and delay in the critical path. And also, the design should have a lesser number of transistors to implement XOR/XNOR circuits. To meet above characteristics, we propose and compare new three input XOR/XNOR circuit designs with the use of SCDM technology. Which produce the XOR/XNOR outputs simultaneously with full output voltage swing. The proposed designs have the better performance than the existing three input XOR/XNOR circuits.

III PROPOSED METHOD We propose two different designs for three input XOR/XNOR circuits. a) One design gives full output voltage swing operation for all input combinations using HSPICE simulation based on TSMC 0.18 µm technology. b) Another design gives minimum transistor count compared to previous circuits and also full output voltage swing using MICROWIND based on 0.18 µm technology. a) New circuit design for full output voltage swing: Initially, the design starts with the main structure of three input XOR gate logic. First, we design 2 input XOR gate. Y=A ⊕ B Then we add extension to this logic. Y= (A ⊕ B) ⊕ C Y= A ⊕B ⊕C To this structure an inverter is added to get XNOR Y= A ⊕ B ⊕C In this type of design, main structure is reusable. The following design shows three input XOR/XNOR circuit of proposed method.

Fig. 5 Three input XOR/XNOR circuit diagram.

In this proposed method we can use two 2-input XOR Gates and two inverters. This Figure consists of A, B and C inputs and Y and Y1 outputs. In this figure, we can use two outputs i.e. Y output indicates 3-input XNOR gate and Y1 output indicates 3-input XOR gate. We will explain the operation of block diagram through truth table of 3-input XOR/XNOR Gate.

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Y 1

0 0 0 0 1 1

0 0 1 1 0 0

0 1 0 1 0 1

1 0 0 1 0 1

0 1 1 0 1 0

V.Sree Vani and V.Lavanya : Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology 1 1

1 1

0 1

1 0

0 1

Table: 1 Truth table of 3-input XOR/XNOR Gate is Seen in table.

The table-1 mainly tales about basic operation of 3-input XOR/XNOR Gate. By using truth table, The basic operation of 3-input XOR Gate output is ‗1‘ when we can apply the odd number of input ones and output is ‗0‘ when we can apply the even number input ones and the basic operation of 3-input XNOR Gate output is ‗0‘ When we can apply odd number input ones and output is ‗1‘ when we can apply even number of input ones. Fig: 6

If we use this structure, we can use 16 transistors, in this 8 NMOS and 8 PMOS transistors. So in this method, numbers of transistors are more. So we can reduce transistor count in another method. But this method gives full swing output voltage. b) New circuit design with less number of transistors: In this proposed method we can design 3-input XOR/XNOR Gate by using 8 transistors so compare to existing method we reduce to half of the transistors. In Fig: 5. we can use two outputs Y and Y1.Y is the output of 3-input XOR Gate and Y1 is output of 3-input XNOR Gate. The circuit diagram of proposed is illustrated in fig: 5.

two-input XOR Gate

The circuit diagram of 2-input XOR Gate is illustrated in fig 5.

Fig: 7 three-input XOR/XNOR Gate

See the table: 2 mainly this explains how operate the circuit depends on input sequence.

OFF

Table: 2 proposed method Transistor ON/OFF conditions depend on input.

IV SIMULATION RESULTS This section describes performance of the proposed design using MICROWIND/DSCH tool on 0.18µm CMOS technology and simulation results using HSPICE tool on 0.18µm technology. The simulated output of 3 input XOR/XNOR gate as shown in figures

a) Simulation Results of three input XOR/XNOR for first method.

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V.Sree Vani and V.Lavanya : Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology This brief has favoured SCDM with the wise selection of the circuit components for the PDP target. The new circuits enjoy higher driving capability, transistor density, noise immunity with low-voltage operation, and the least probability to produce glitches. As a unique feature, the critical path of the presented designs consists of only two transistors, which causes low propagation delay REFERENCES

B)Schematic diagram for first method

c)Simulation results for three input XOR/XNOR for second method

e)Schematic diagram for second method

f)Layout for second method

V CONCLUSION SCDM serves as a design methodology for three-input XOR/XNOR, which is one of the most complex and competitive as well as all-purpose three-input basic gates in arithmetic circuits. The methodology puts emphasis on doing all the steps in a completely systematic way. It also enjoys high flexibility in design target, while it follows the same procedure to obtain the state-of-the-art designs.

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V.Sree Vani and V.Lavanya : Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology [11] A. Eshra and A. El-Sayed, ―An odd parity checker prototype using DNAzyme finite state machine,‖ IEEE/ACM Trans. Comput. Biol. Bioinf., vol. 11, no. 2, pp. 316–324, Mar.0/Apr. 2014. [12] R. Roy, D. Bhattacharya, and V. Boppana, ―Transistor-level optimization of digital designs with flex cells,‖ Computer, vol. 38, no. 2, pp. 53–61, Feb. 2005. [13] M. Rahman, R. Afonso, H. Tennakoon, and C. Sechen, ―Design automation tools and libraries for low power digital design,‖ in Proc. IEEE Dallas Circuits Syst. Workshop (DCAS), Oct. 2010, pp. 1–4.

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