Paper id 2620142

International Journal of Research in Advent Technology, Vol.2, No.6, June 2014 E-ISSN: 2321-9637

Matlab Simulation of Cascaded H-Bridge Inverter with Unequal DC Voltages Paras Arora1 Bharat Modi2 Department of Electrical Engineering1, 2 Swami Keshvanand Institute of Technology, Jaipur1, 2 Email: parasaroraee@gmail.com1

Abstract- In recent years, multi-level inverter (MLI) are extensively used in high power industrial applications.

Multilevel inverters proves that they are very promising topology that offers many benefits for high power applications. This gives a comparison between asymmetrical and symmetrical MLI using multi carrier pulse width modulation technique. This paper mainly focuses on asymmetrical MLI with reduced number of dc sources. In 7 level asymmetrical CHB use only 2H bridges and in 7 level symmetrical CHB uses 3H bridges. In this paper a MATLAB prototype of tow cell seven level CHB has been built to verify the simulation results.

Keywords: CHB, asymmetrical CHB, MATLAB. 1. INTRODUCTION Multilevel inverter (MLI) offers a number of advantages when compared to the conventional twolevel inverter in terms of improved DC link utilization and harmonic spectrum. Multilevel inverter achieves high voltage switching by means of a series of voltage steps, each of which lies within the rating of the individual power devices. Several topologies for multilevel inverter have been reported in the literature [5], [7].

The different types of MLI are diode clamped, flying capacitor, cascaded MLI. Diode clamped requires more no of diodes and flying capacitor has capacitor balancing problem. The cascade H-bridge (CHB) inverter having more no of advantages such as modular structure compare to other topologies and less no of components it is one of the topologies proposed for drive applications which meet the requirements such as high power rating with reduced THD and switching losses. This paper focuses on the cascaded H-bridge inverter with unequal dc voltages. The symmetrical topology that uses equal DC sources and the asymmetrical topology which employs unequal DC sources. The asymmetric MLI reduces the number of input DC sources required and increases the number the number of levels in the output.

This paper is organized as follows: CHB topology in presented in section II. Section III, discuss the CHB with unequal dc voltages. The MATLAB model is

presented in IV. The results are discussed in V. And conclusion is presented in VI. And finally references in VII. 2. CHB MLI TOPOLOGY Cascade H-bridge (CHB) multilevel inverter is one of the popular converter topologies used in high-power medium voltage drives [1][2][4]. It is composed of a multiple units of single phase H-bridge power cell. The H-bridge cell is normally connected in cascade on their ac side to achieve required voltage level for operation and low harmonic distortion. A single H-bridge cell is shown in Fig.1.

Fig. 1.: Single-Phase H-Bridge Inverter.

The Cascaded H-Bridge inverter has two topologies •

Symmetrical CHB inverter or CHB with Equal dc voltage

1

International Journal of Research in Advent Technology, Vol.2, No.6, June 2014 E-ISSN: 2321-9637 •

Asymmetric CHB inverter or CHB Unequal dc voltages

with

A seven level symmetric H-bridge multilevel inverter has three H-bridges. The DC source for the three Hbridges H1, H2 and H3 is V dc. Therefore the output voltage of the inverter can have the values 3V, 2V, V, 0, -1V, -2V and -3V which gives a seven level output voltages.

-E -2E -3E

0 1 1 1 0 0 1 0

0 1 1 0 1 1 1 0

1 0 1 0 1 0 0 0

1 0 1 1 1 0 1 1

0 0 0 E -E -E 0 0

0 0 0 -2E 0 0 -2E -2E

0

1

0

1

E

-2E

3. ASYMMETRICAL CHB MLI TOPOLOGY In asymmetrical CHB the dc power supply selected for each bridge cell can be different. With unequal dc voltages, the number of voltage levels can be increased without necessarily increasing the number of H-bridge cells in cascade. This allows more voltage steps in the inverter output voltage waveform for a given number of power cells [6],[3].

Fig 2,shows seven level Asymmetrical MLI inverter topologies, where the dc voltage for the H-bridge cells are not equal. In the seven level topology, the dc voltage for H1 and H2 are E and 2E, respectively. The two cell inverter leg is able to produce seven voltage levels: 3E, 2E, E, 0, -E, -2E, and -3E.The relationship between the voltage levels and their corresponding switching states is summarized in table 1.

Fig. 3.: Per Phase Diagram of a Nine level CHB inverter with Unequal DC Voltage.

Fig. 3, shows the two cell nine level asymmetrical CHB inverter. In the nine level topology, the dc voltage of H2 is three times that of H1. All the nine voltage levels can be obtained by replacing the H2 output Fig. 2: Per Phase Diagram of a Seven level CHB inverter with Unequal DC Voltage.

TABLE1.:voltage leveland switching stateof two cell seven level CHB inverter with unequal dc source.

Output CHB cell Switching States Voltage voltage

v AN 3E 2E E 0

S11 1 1 0 1 1 0 0

S31 0 1 0 0 0 1 0

S12 1 1 1 1 0 1 0

S32 0 0 0 1 0 0 0

vH1

vH 2

E 0 0 E E -E 0

2E 2E 2E 0 0 2E 0

4. MATLAB MODEL of CHB MATLAB Simulink model of a seven level asymmetrical H-bridge inverter is shown in Fig. 4. It is clear from the model that for the same level it requires less number of H-bridge modules, i.e. only two for each phase. So it requires six H-bridge modules for three phase model. Where as in symmetrical H-bridge requires nine such modules. And also it requires less number of DC source, i.e. only six.

The control circuit for the same is shown in Fig. 5. To generate gate pulses for each bridge unit three carrier signal are compare against one reference signal and the XOR of these comparisons taken to generate the signal.

2

International Journal of Research in Advent Technology, Vol.2, No.6, June 2014 E-ISSN: 2321-9637 Fig 6.shows the parameters for repeating sequence block. Repeating sequence is used to generate carrier signals. Fig.7, shows the carrier and reference signal arrangement. Fig. 8, shows the gate pulses for the asymmetrical seven level cascaded H-bridge inverter.

Here in this modulation index is 1, reference frequency is 50 Hz, carrier frequency is 100 Hz and load parameter are R=10 ohm and L=0.03 H and FFT parameters are start time is 0.01 sec, number of cycle taken is 1.

Fig.6: Repeating sequence block parameters.

Fig.4.: 7 level Asymmetrical CHB.

Fig. 7:Carrier waves for 7 level asymmetrical CHB.

Fig. 5: control circuit of one phase leg of 7 level asymmetrical CHB.

Fig. 8: Firing pulses for asymmetrical 7 levelCHB.

3

International Journal of Research in Advent Technology, Vol.2, No.6, June 2014 E-ISSN: 2321-9637 5. RESULT DISCUSSION Fig. 9 and Fig. 10, shows the line and phase voltage of asymmetrical 7 level CHB respectively. Fig. 11 shows the FFT analysis of asymmetrical 7 level CHB. THD of a two cell seven level asymmetrical CHB is 10.35%

switches. THD component is also very less. In future to design proper control circuit for 9 level, 11 level asymmetrical CHB inverter and reduce the THD with less number of switches.

REFRENCES

Fig. 9: line voltage Vab of asymmetrical 7 level CHB.

Fig. 10: phase voltages of 7 level asymmetrical CHB.

[1]. Hammond,P. W. (1997): A New Approach to Enhance Power Quality for Medium Voltage ACDrives, IEEE Transactions on Industry Applications, Vol. 33, No. 1, pp. 202–208.

[2]. Hill, W.A.; and Harbourt,C.D. (1999): Performance of Medium Voltage Multilevel Inverters,IEEE Industry Applications Society (IAS) Conference, Vol. 2, pp. 1186–1192.

[3] Manjrekar, M.D.; Steimer, P.K. (2000): Hybrid Multilevel Power Conversion System: ACompetitive Solution for High Power Applications, IEEE Transactions on Industry Applications, Vol. 36, No. 3, pp. 834–841.

[4]. Osman, R.H. (1999): A Medium Voltage Drive Utilizing Series-Cell Multilevel Topology forOutstanding Power Quality, IEEE Industry Applications Society (IAS) Conference, pp.2662– 2669.

[5]. Ruderman; Schlosberg, A.; Sam (2008):A Hybrid asymmetric cascaded multilevel inverter comprising high resolution and symmetric low resolution parts, Electrical and Electronics Engineers in Israel, IEEEI 2008. IEEE 25th Convention , pp: 021-025.

[6] Wheeler, P.W.; Empringham, L. (2000): Improved Output Waveform Quality for Multi-level HBridge Chain Converters Using Unequal Cell Voltages, IEE Power Electronicsand Variable Speed Drives Conference, pp. 536–540.

[7]. Zhong Du; Tolbert. L.M.; Chiasson.J.N.; Ozpineci.

B. (2006): A cascade multilevel inverter using a single DC source, Applied Power Electronics Conference and Exposition, APEC apos;06.

Twenty-First Annual IEEE Volume , Issue 19-23 ,pp: 426-430

Fig. 11: FFT of asymmetrical 7 level CHB.

6. CONCLUSION Cascaded H-bridge with unequal dc voltage is a very impressive topology. It requires less number of component as compared to other topologies to generate same number of levels. A symmetrical CHB uses 3 H bridges and 12 switches, whereas asymmetrical CHB uses 2 H bridges and only 8 switches to generate 7 voltage levels. And to generate 9 levels asymmetrical CHB requires 2 H-bridges and 8 switches whereas symmetrical CHB requires 4 H-bridges and 16

4