Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL

IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 10, 2015 | ISSN (online): 2321-0613

Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL Ajay Basavraj Dhulkhedkar1 Prof. G.P. Jain2 1,2 Department of Electronics Engineering 1,2 Walchand Institute of Technology, Solapur - 413 006, Maharashtra, India Abstract— All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.

Key words: Area-efficient, CSLA, low power, binary to excess one convertor (BEC), simple ripple carry adder (RCA) I. INTRODUCTION The enormous research has been carried out in VLSI system design with area and power-efficient high speed data path logic system. Addition speed is based upon the time required to propagate a carry through the adder. The addition of each bit position in a basic adder is generated sequentially only after the previous bit position has been added and a carry is propagated into the next position [1].

In the full adder circuit, the carry has been moved from one state to another state. The carry of Last state is needed for the present state to perform the addition operation. So, the propagation delay and delay of each stage increases with increase in size of adder i.e. the number of bits to be added. Now we can avoid the delay occurred in transmitting carry by predicting the carry occured at every stage.

There is a necessity of improving the speed for design by developing reduced gate architecture. As day-byday computers speed is upgrading very fast in term of GHz. Carry Select Adder (CSLA) has a more balanced delay and acquires lower power and area [3]. The CSLA is used in many Processors to improve by predicting multiple carries independently and then select a carry to produce the sum [2]. As CSLA uses two Ripple Carry Adders (RCA) for each stage to generate partial sum and carry by considering carry input Cin=0 and Cin=1, Then the final sum and carry are selected by the multiplexers which are considered to be area inefficient [3].

A. BEC As stated above the modified architecture consisting BEC instead of the RCA with C = 1 in order to reduce the area and power consumption of the regular CSLA. Instead of the n-bit RCA, an n+1 bit BEC is required. A structure of a 4-bit BEC is shown in Fig. 1.

Fig .1: 4-bit BEC

The basic purpose of the CSLA is obtained by using the 4-bit BEC along with the multiplexer. One input of the 8:4 multiplexer is from RCA (B3, B2, B1, and B0) and another input of the mux is the BEC output [1]. This generates the two possible results and the multiplexer is used to select either the BEC output or the direct inputs from RCA according to the carry signal Cin. The significance of the BEC logic stems from the large silicon area reduction when the CSLA with great number of bits are designed.[7] The Boolean expressions for 4-bit BEC is as follows.

X0 = B0 X1 = B0B1 X2 = B2 (B0 B1) X3 = B3 (B0 B1 B2)

Fig. 2: Architecture of 4-Bit BEC B[3:0] X[3:0] 0000

0001

0001

0010

0010

0011

1110

1111

Table 1: Input and Output of 4-bit BEC Similarly the remaining groups will be selected depending on the Cout from the earlier groups.

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Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL (IJSRD/Vol. 3/Issue 10/2015/081)

II. METHODOLOGY: A. ARCHITECTURE OF MODIFIED 64-BIT SQRT CSLA

number of gates in the longest path of a logic block that contributes to the maximum delay. The area assessment is done by calculating the total number of AOI gates necessary for each logic block. Based on this approach, the CSLA adder blocks of 2:1 mux, Half Adder (HA), and Full Adder (FA) are evaluated and listed in Table II.

Fig. 4. Delay and area evaluation of XOR gate Adder blocks Area Delay

Fig 3: Architecture of 64 bit CSLA This architecture is analogous to regular 64-bit SQRT CSLA, the only change is that, we replace RCA with Cin=1 among the two available RCAs in a each group with a BEC. This BEC has a feature that it can perform the similar operation as that of the replaced RCA with Cin=1. Fig 3 shows the Modified block diagram of 64-bit SQRT CSLA. The number of output bits for BEC logic is 1 bit more than the RCA bits. The modified block diagram is also divided into different groups of variable sizes of bits. Each group is having the ripple carry adders, BEC and equivalent mux. As shown in the Fig.3, Group 0 include one RCA only which is having input of lower significant bit and Cin bit and creates result of sum [1:0] and Cout which is connected to selection line of mux for the next group, likewise the process continues for upper groups but they includes BEC logic instead of RCA with Cin=1.Based on the consideration of delay values, the appearance time of selection input C1 of 8:3 mux is appear in advance than the sum of RCA and BEC. For remaining groups the selection input arrival is later than the RCA and BEC. Thus, the sum1 and c1 (output from mux) are depending on mux and results obtained by RCA and BEC respectively. The sum2 depends on c1 and mux. For the remaining groups the appearance time of mux selection input is always larger than the arrival time of data inputs from the BEC’s. Thus, the delay of the remaining MUX based on the arrival time of mux selection input and the mux delay. The implementation code for Full Adder and Multiplexers of 6:3, 8:4, and 10:5 up to 26:13 were designed in this Modified CSLA architecture. The design code for the BEC was formed by using NOT, XOR and AND gates.

Then 2, 3, 4, 5 up to 11-bit RCA was designed.

III. DELAY AND AREA EVALUATION METHODOLOGY OF THE BASIC ADDER BLOCKS The design of XOR using AND, OR, and Inverter (AOI) is shown in Fig.4. The numeric representation of each gate points to the delay contribution by that gate. The delay and area estimation methodology considers all gates to be designed using AND, OR, and Inverter, each having delay equal to 1 unit and area equal to 1 unit. We then consider the

Xor

5

3

2:1 Mux

4

3

Half adder

6

3

Full adder

13

6

Table 1: Delay and Area Count of the Basic Blocks of Csla IV. DELAY AND AREA EVALUATION METHODOLOGY OF MODIFIED 64-B SQRT CSLA The architecture of the modified 64-b SQRT CSLA using BEC for RCA with Cin=1 to optimize the area and power we again divide the structure into ten groups. The delay and area estimation of each group can be calculated. The steps for the estimation are as follows.

1) The group2 has one 2-b RCA which consist 1 FA and1 HA for Cin=0. as a replacement for of another 2-b RCA for Cin=1 a 3-b BEC is used which adds one to the output from 2-b RCA. Based on the consideration of delay values of Table II, the arrival time of selection input C1[time(t)=7] of 6:3 mux is appear earlier than the s3[t=9] and c3[t=10] and afterward the s2[t=4]. Thus, the result sum3 and final C3 (output from mux) are based on mux and partial C1 (input to mux). Thus the result sum2 depends on c1 and mux.

2) For the remaining groups the arrival time of mux selection input is always larger than the arrival time of data inputs from the BEC’s. Thus, the delay of the remaining groups are based on the arrival time of mux selection input and the mux delay.

V. IMPLEMENTATION The SQRT CSLA and modified SQRT CSLA architectures have been developed using VHDL and synthesized in Xilinx ISE 14.1. Table V describes the simulation results of both the CSLA structures in terms of delay and power. The total power is addition of the leakage power, internal power and switching power. The power estimation is done in Xilinx Power Estimator.

A. RESULT This architecture has been simulated using Xilinx tool.

Table shows the comparison between conventional CSLA, Modified CSLA for 64-bit. The parameters on which they

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Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL (IJSRD/Vol. 3/Issue 10/2015/081)

are compared are delay and power. Graph I shows that the delay of modified CSLA is slightly greater than regular CSLA. The results compared in Graph II shows that the power consumption of modified SQRT CSLA is reduced. It is clear that power and area of modified SQRT CSLA for 64-bit is reduced as compared to conventional adder.

Type of adder

Delay(ns)

Power(uw)

Delay power product

Regular CSLA

7.497

682.629

5117.669

Modified CSLA

8.707

356.064

3100.249

Table.3 comparisons between Regular and Modified architecture

Delay(ns) 9 8.5 8 Delay(ns)

7.5 7

VII. FUTURE SCOPE This work has been designed for 64-bit word size and results are evaluated for parameters like area, delay and power.

This work can be extended for higher number of bits. New architectures can be designed in order to reduce the power, area and delay of the circuits.

ACKNOWLEDGEMENTS We would like to take this opportunity to thank one and all who have provided their valuable advice, without their guidance this work would not have been a success, we have to thank who have helped us directly or indirectly since they have given us more than just guidance. Our profound thanks to Dr. S R Gengaje, Head of the Department, Department of Electronics Engineering, Walchand Institute of Technology, Solapur, for his invaluable advice and constant encouragement to complete this work in a successful manner. I would like to convey our sincere thanks to management and supportive staff of Walchand Institute of Technology, Solapur, for encouraging us to come up with this paper work.

6.5 Regular CSLA Modified CSLA

REFERENCES

Fig . 5: Graph I: Delay of Regular and modified CSLA

Power(uw) 800 700 600 500 400 Power(uw)

300 200 100 0 Regular CSLA

Modified CSLA

Fig .6 : Graph II: Power dissipation of Regular and modified CSLA VI. CONCLUSION Power, delay and area are the significant factors in VLSI design that limits the performance of any circuit. This work Present a simple approach to reduce the area and power of CSLA architecture. The conventional carry select adder has the drawback of more power consumption and occupying more chip area. The proposed SQRT CSLA using BEC has low power and reduced area than all the other adder structures. In this way, the transistor count of proposed SQRT CSLA is reduced having less area and low power which makes it simple and efficient for VLSI hardware implementations.

[1] low-power and area-efficient carry select adder b. ramkumar and harish m kitturieee transactions on very large scale integration (vlsi) systems, vol. 20, no. 2, february 2012 [2] P. Sreenivasulu, Dr. K. Srinivasa Rao, Malla Reddy, Dr.A.VinayBabu/ International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 2, Mar-Apr 2012, pp.436440 436 [3] International Journal of Computer Applications (0975 – 8887) Volume 69– No.6, May 2013 29128 Bit Low Power and Area Efficient Carry Select Adder SudhanshuShekhar Pandey Amit Bakshi [4] Analysis of Low Power, Area- Efficient and High Speed Fast Adder Pallavi Saxena1, Urvashi Purohit2, Priyanka Joshi3 Analysis of Low Power, AreaEfficient and High Speed Fast Adder Pallavi Saxena1, Urvashi purohit2, priyanka joshi3 [5] international journal of advanced research in electrical, electronics and instrumentation engineering vol. 2, issue 7, july 2013 copyright to ijareeie www.ijareeie.com 3112 128-bit carry select adder having less area and delay m.chithra1, g.omkareswari2 [6] International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 2, Issue 4, July 2013 375 Modified Low-Power and AreaEfficient Carry Select Adder using D-Latch Veena V Nair M-Tech student, ECE Department, Mangalam College of Engineering, Kottayam, India [7] International journal of innovative research in technology & science(ijirts) 40 international journal of innovative research in technology&sciencearea and power-efficient carry select adder by LaxmanShanigarapuBhavana P. Shrivastava [8] Design of 32-bit Carry Select Adder with Reduced Area Yamini Devi Ykuntam.V.Nageswara Rao G.R.Locharl

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