A Survey on SRAM Cell to Improve Leakage And Energy Efficiency

IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 08, 2015 | ISSN (online): 2321-0613

A Survey on SRAM Cell to Improve Leakage and Energy Efficiency S.Nijantha1 Prof. K.A.Dattathreya2 1 P.G. Scholar 2Professor 1,2 Department of Electronics & Communication Engineering 1,2 Adhiyamaan College of Engineering Hosur, India Abstract—Static Random Access Memory (SRAM) is a type of Memory which is faster and more suitable than other memories such as Dynamic Random Access Memory (DRAM) or Flash Memories. The main advantage of the SRAM is need not to be refreshed. SRAM is mainly used for Cache memory in many applications such as Microprocessors, Engineering Workstations, Mainframe Computers etc…for High Speed and Low Power Consumption. The Energy Efficiency and Speed of SRAM are the most Crucial issue. The Aim of this Survey Paper is to provide a Energy Efficient Low Power SRAM Cell and here various Techniques and Approaches are discussed to Achieve the Better Performance.

Key words: Static Random Access Memory (SRAM), Energy Efficiency, Leakage, Low Power I. INTRODUCTION System-on-chip refers to integrating all components of a computer or other Electronic System in to a Single Integrated circuit. It performs many functions on a Single Chip Substrate, some SOC’s are used as Multiprocessor System-on-chip (MPSOC) which include more than one processor core. Usually Processor includes Memory Blocks such as ROM, RAM, EPROM, EEPROM and Flash. From these blocks, SRAM plays a important role in Providing the Required Power, Performance and energy consumption of Applications. SRAM’s have achieved Ultra-Low Power Energy through Supply Scaling. Even though, they suffer from various design issues. By further scaling the Supply voltage near or below Transistor’s threshold voltage, energy efficiency and power of SRAM will greatly affect the Performance. Similarly other design Parameters such as Stability, read/write margin and leakage are noted for Reliable Performance. Generally, In CMOS Circuits the static leakage power affects the SRAM for two main reasons. First, Leakage Power is Proportional to total number of transistors on chip and secondly it is related to temperature dependence of some sources of Leakage Power.

Hence in order to improve Leakage and to achieve Energy Efficiency, many Literatures and its Techniques were discussed.

II. LITERATURE SURVEY AND ITS TECHNIQUES In this section, the Leakage and Energy Efficiency issues of SRAM cell and their approaches are discussed.

A. Design of an Ultra-Low Voltage 9T SRAM with Equalized Bit line Leakage and CAM-assisted Energy Efficiency Improvement.

Bo Wang, Truc Quynh Nguyen, Anh Tuan Do, Jun Zhou, Minkyu Je and Tony Tae-Hyoung Kim, IEEE has Compared many SRAM cell and its Layout. The Analysis of Static Noise Margin (SNM) , Write margin with Bit line Equalization with the worst case of leakage are discussed to address the problem in Existing method and in Proposed

method the technique used to improve Efficiency are MultiThreshold CMOS (MTCMOS) and CAM-assisted write Performance Boosting Technique. In MTCMOS, the overall Performance is slow in implementing write operation. To overcome this above issue, the CAM-assisted technique is used and the technique to boost the write performance by alerting the CPU when the write operation is finished. The Read and Write operations of SRAM with CAM and Without CAM are tested for lowest minimum energy. In this Paper, the Efficiency is improved by 40.3% with minimum energy per operation of 2.07PJ at 0.4V B. A Single-Ended Disturb-free 9T Sub threshold SRAM with Cross-point Data-Aware write Word-line Structure, Negative Bit-line and Adaptive read operation Timing tracing.

Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang (Willis) Shih, Shyh-Jye Jou, Senior Member, IEEE, and Ching-Te Chuang, Fellow, IEEE has Proposed Disturb-free 9T Sub threshold SRAM which enhances Soft-error Immunity by Error Checking and Correction Technique (ECC). In this paper, SRAM cells improve the read stability by reducing the Performance of one-side of NMOS pull-down transistor with one read port and the cell eliminates read disturb and write Half-Select Disturb for better operation. The minimum energy per operation is 4.5PJ at 0.5V. C. A 250mv 8kb 40nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM) Adam Teman, Student Member, IEEE, Lidor Pergament, Omer Cohen, and Alexander Fish, Member, IEEE Proposed Power Reduction by implementing a supply feedback to weak the Pull-up Current during write cycles, Using this technique the leakage power reduced up to 60% while comparing with other 8 bit cell, 15-16% reduction of static power is achieved without adding any other Peripheral Circuitries.

D. A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep mode.

Tae-Hyoung Kim, Student Member, IEEE, Jason Liu, Member, IEEE, and Chris H. Kim, Member, IEEE has Proposed 512 Cells per Bit line. The MBLC (Marginal Bit line Leakage Consumption) Scheme is used for Compensating Bit line leakage current and it is made to work under the deep sleep mode to improve the leakage current and RSCE (Reverse Short Channel Effect) is used to improve Read and Write ports of SRAM cell with minimum energy.

E. A Super-Pipelined Energy Efficient Sub threshold 240 MS/s FFT core in 65nm CMOS Dongsuk Jeon, Student Member, IEEE, Mingoo Seok, Student Member, IEEE, Chaitali Chakrabarti, David Blaauw, Senior Member, IEEE, and Dennis Sylvester,

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A Survey on SRAM Cell to Improve Leakage and Energy Efficiency (IJSRD/Vol. 3/Issue 08/2015/109)

Fellow, IEEE has proposed two methods, they are Superpipelining and Parallel-Pipelining. The Pipelining increases number of Pipelines and reduce the Leakage and the Parallel Pipelining use all Functional units to reduce the leakage and here those techniques are applied in FFT to design the High Performance System.

F. A 65nm 32b Sub threshold Processor with 9T multi-Vt SRAM and Adaptive Supply Voltage Control Sven Lutkemeier, Student Member, IEEE, Thorsten Jungeblut, Member, IEEE, Hans Kristian Otnes Berge, Student Member, IEEE, Snorre Aunet, Senior Member, IEEE, Mario Porrmann, Member, IEEE, and Ulrich Ruckert, Member, IEEE has proposed Energy Efficient SRAM with minimum energy at average of 325mv by Adaptive Supply Voltage Control, whereas the Processor cores in SOC are based on Custom Standard cell library with Ultra-Low Voltage.

G. A Sub-0.3V Area Efficient L-Shaped 7T SRAM with Read Bit line Swing Expansion Schemes based on Boosted Read-Bit line, Asymmetric Vth read-port, and offset cell Vdd Biasing Techniques Meng-Fan Chang, Ming-Pin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su,Yuan-Hua Chu, Wen-Ching Wu, Tzu-Yi Yang, and Hiroyuki Yamauchi has proposed L-shaped 7T cells and Read Bit line Swing expansion Scheme (RBL-EXPD) to minimize the energy and to be used for Low-Voltage Applications. This paper has improved write margin with reduced cell area than the 8T SRAM cells.

H. An Embedded Energy monitoring circuit for a 128kbit SRAM with Body-Biased Sense amplifiers Yildiz Sinangil and Anantha P. Chandrakasan has Proposed energy sensing circuit with 128kbit SRAM’s which use Body-Biased PMOS-input strong-arm type Sense amplifiers to achieve low SRAM overhead of approximately around 3.5%.

III. CONCLUSION Energy Efficiency and Leakage are main concerns in the SRAM. The remedies to overcome this problem are discussed in this survey with various approaches and design techniques where they have undertaken. I am going to implement a modified 9T SRAM with Self-Adaptive Voltage Level circuit to minimize leakage and to improve Energy Efficiency. In Future, the Enhancements can be made in upper SVL Circuit to fasten the read and write operations thereby reducing the total Power.

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