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IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 08, 2015 | ISSN (online): 2321-0613

Analysis of Various Techniques in Low Noise Amplifier Design F. Ruby Mary1 P. Kannan2 1,2 Anna University Abstract—Low noise amplifier is a crucial and essential component in RF receiver design. It amplifies the received weak RF signal with minimum noise contribution.

Designing Low noise amplifier with CMOS technology is one of the important topics in research fields due to its advantages of low power, low cost and higher integration.

Applications of LNA include WLAN, WSN and UWB applications. In this paper a detailed survey is provided for various LNA design techniques. The designed circuit is simulated using Advanced Design System (ADS) software.

Key words: RF, LNA, CMOS, WLAN, WSN, UWB, ADS I. INTRODUCTION Low Noise Amplifier is basically the first section and very important part of the receiver, which determines the overall efficiency of the receiver. Low Noise Amplifier is basically an electronic amplifier that amplifies the received weak signals and reduces the noise and other distortions present in the signal. The main requirement of Low Noise Amplifier is low noise figure and high gain. To determine the efficiency of Low Noise Amplifier, parameters like gain, noise figure, stability and linearity are analyzed.

In the past, instead of using CMOS technology, GaAs pHEMT and mHEMT technologies were used. Due to the advantages of low cost and high integration, CMOS technology is widely used in Low Noise Amplifier design.

In earlier days 0.35 µm CMOS and 0.18 µm CMOS technologies are used.

Due to the resulting advantages of reduced chip size, 0.13 µm technology is used nowadays. It covers the frequency range of many popular wireless products such as Cell phones, GPS and Bluetooth. The following Chapter gives the detailed literature survey on different methods for Low Noise Amplifier design.

The complete design of Low Noise Amplifier consists of three main sections, namely Main transistor section, Input matching network and the Output matching network. The first step in designing LNA is the selection of Transistor. The selected transistor must achieve high gain, low noise figure and high IIP3 Performance. The input matching and output matching network is used to increase the power transfer and to reduce the reflections [17].

II. METHODS FOR LNA DESIGN Some of the important LNA design techniques are discussed below.

A. Capacitive Cross Coupling Technique The Common Gate Low Noise Amplifier achieves wideband input impedance matching but it suffers from reduced noise performance. To overcome this problem a capacitive cross coupling technique is used. Here a noise inductor combined with the capacitive cross coupling technique is proposed for Common Source-Common Gate (CS-CG) two stages LNA to improve the noise performance and linearity performance of the differential cascade LNA. The CS stage is designed to achieve the input impedance matching and to obtain best

noise performance. The cascade transistor works as a Common Gate stage. It is mainly designed to reduce the Miller effect of the parasitic gate-drain overlap capacitance in the Common Source transistor. The improved inputoutput isolation and output impedance are also obtained here. This method provides gain of 8.4dB and noise figure of 1.92dB. The performance measure is shown in Table1.

Parameters Measured Values Frequency(GHz) 2.2 S11(dB) < -13 S21(dB) 8.6 NF(dB) 1.92 IIP3(dBm) -2.55 CMOS Process 0.35 Table 1: Performance Measures B. Self Forward Body Bias Technique Forward body bias technique is mainly used to reduce the power consumption and size of Low Noise Amplifier. In this paper, a low-power low-noise amplifier utilizing selfforward-body-bias (SFBB) technique for wideband application is proposed. An ultra-low power self-bias approach is used in SFBB technique, which improves the performance of conventional FBB technique. SFBB technique needs an additional bias circuit to provide supply for the bulk terminal of the MOSFET to obtain a forward bulk source bias. The SFBB technique is used to reduce supply voltage and saves additional bias circuit which leads to low power consumption. The direct coupling technique between the first two stages is also used to save bias circuits.

This method provides noise figure of 2.65 dB and power gain of 16 dB. The performance measure of this technique is shown in Table 2.

Parameters Measured Values Frequency(GHz) 3 - 6.5 S11(dB) < -12 NF(dB) 2.65 Power Supply(V) 1.06 CMOS Process 0.18 µm Table 2: Performance Measures C. Transformer Feedback Technique Transformer feedback technique is widely used for LNA design in low frequency applications. This method proposed a transformer feedback LNA, which is composed of four cascade common source stages with two different transformer feedback configurations. The gate-source transformer feedback at the input stage is used for achieving simultaneous noise and input impedance matching, and the contiguous stages are designed using the drain-source transformer feedback technique to achieve inter-stage matching and output matching with improved power gain.

This method provides noise figure of 5.4 dB and gain of 12.5 dB. The performance measure of this technique is shown in Table 3.

Parameters Measured Values Frequency(GHz) 60 Gain(dB) 12.5

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Analysis of Various Techniques in Low Noise Amplifier Design (IJSRD/Vol. 3/Issue 08/2015/220)

NF(dB) 5.4 Power Supply(V) 1 CMOS Process 90 nm Table 3: Performance Measures D. Parallel to Series Matching Network Technique Matching network is an essential part of RF circuit design.

Matching network is mainly used to transfer maximum power from source to load without any loss of power. In this paper, an efficient inter-stage matching technique is proposed to design wideband LNAs which are made up of cascaded CG and CS stages. The values of inductors and capacitors are selected properly for the resonation of parallel LC network and series LC network occurring at the same frequency. The resulting parallel to series matching network exhibits a dual-band response with a dip in the middle. This mid-band loss is compensated by the second stage. The first LNA operates at 3.1-10.3 GHZ having power gain of 9.612.71 dB and noise figure of 2.5-3.9 dB. The second LNA operates at 14.3-29.3 GHZ having power gain of 8.25 dB and noise figure of 4.3-5.8 dB. The performance measure of this technique is shown in Table 4.

Parameters Measured Values Frequency(GHz) 14.3 – 29.3 S11(dB) < -8.6 S21(dB) 8.25 ± 1.65 NF(dB) 4.3 - 5.8 IIP3(dBm) -2 Power Supply(V) 1.8 CMOS Process 0.35 µm Table 4: Performance Measures E. Current Reuse Technique The Current Reuse Technique is mainly used to provide same bias current in the circuit and to reduce power consumption. By stacking two NMOS devices (or one NMOS and one PMOS device) one can achieve the current reuse technique. It enhances the overall Trans-conductance of the circuit which in-turn minimizes the MOSFET noise.

In this paper the Current Reuse Technique is employed by sharing the bias current between the trans-conductance (gm) boosting and UWB signal amplifying stages. The proposed LNA exhibits Power gain of 13 dB and Noise Figure ranging between 3.5 and 4.5 dB. The performance measure of this technique is shown in Table 5.

Parameters Measured Values Frequency(GHz) 3-5 S11 -8.4 to -40 dB S22 -14 to -15 S21 13 dB S12 -55 to -40 NF 3.5 to 4.5 CMOS Process 130 nm Table 5: Performance Measures III. RESULTS AND DISCUSSIONS Thus in this paper various LNA design techniques are analyzed. The performance analyses of these methods are carried out using the parameters such as gain, noise figure, IIP3 and reverse isolation. This analysis shows that the Self Forward Body Bias Technique provides higher gain and the

Capacitance Cross Coupling Technique provides lowest noise figure.

IV. CONCLUSIONS This paper describes a survey of different methods for designing low noise amplifier. The analysis shows that the self forward bias technique provides higher gain and low noise figure, but this technique generates stability problem.

To overcome this problem shunt feedback is used instead of series feedback. Best result may be obtained by using this shunt feedback technique.

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[2] Bevilacqua.A and Niknejad.A.M, “An ultra-wideband CMOS lownoise amplifier for 3.1–10.6-GHz wireless receivers,” IEEE J. SolidState Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004.

[3] Ankita A. Pawade, Bhushan R. Vidhale, Dr.M.M. Khanapurkar, “Design and Analysis of Wideband Low Noise Amplifier for Multiple Wireless Applications”, International Journal of Engineering Research and General Science, Vol 3, Issue 2, Part 2, March-April 2015.

[4] Anuarj Madan, Michael J. McPartlin, Christophe Masse, William Vaillancourt and John D. Cressler, “A 5 GHz 0.95 dB NF Highly Linear Cascode Floating Body LNA in 180 nm SOI CMOS Technology”, IEEE Microwave and Wireless Components Letters, Vol. 22, No. 4, April 2012.

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[7] Hui-I Wu, Zi Hao Hsiung and Christina F. Jou, “A 0.75V CMOS Low Noise Amplifier for Ultra Wideband Wireless Receiver”, Piers Online, Vol. 3, No. 7, 2007.

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[9] Kim.C.W, Kang M.S, Anh P.T, Kim H.T, and Lee S.G , “An ultra-wideband CMOS LNA for 3–5-GHz UWB system,” IEEE J. Solid-State Circuits, vol. 40, No. 2, pp. 544–547, February 2015.

[10] Kluge, W., Poegel, F., Roller, H., Lange, M., Ferchland, T., Dathe, L., & Eggert, D. (2006), “A fully integrated 2.4-GHz IEEE 802.15.4-compliant transceiver for ZigBeeTM applications”. IEEE Journal Of Solid-State Circuits, 41(12), 2767–2775.

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[11] Manjula S, Selvathi D, “Design of Low Power 2.4 GHz CMOS Cascode LNA with Reduced Noise Figure for WSN Applications”, Wireles Press Commun (2013).

[12] Muhammad Khurram and Rezaul Hasan, “A 3-5 GHz Current Reuse gm Boosted CG LNA for Ultrawideband in 130 nm CMOS”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 3, March 2012.

[13] Po-Yu Chang, Sy-Haur Su, Shawn S. H. Hsu, Wei-Han Cho and Jn-De Jin, “An Ultra Low Power Transformer Feedback 60 GHz Low Noise Amplifier in 90 nm CMOS”, IEEE Microwave and Wireless Components Letters, Vol. 22, No. 4, April 2012.

[14] Tran Van Hoi, Nguyen Xuan Truong, Bach Gia Duong, “Design and Fabrication of High Gain Low Noise Amplifier at 4 GHz”, International Journal of Engineering and Innovative Technology, Vol. 4, Issue.

7, January 2015.

[15] Wang.s and Huang.B.Z, “A High Gain CMOS LNA for 2.4/5.2 GHz WLAN Applications” Progress in Electromagnetics Research C, Vol. 21, 155-167, 2011.

[16] Xiaohua Fan, Heng Zhang and Edgar SanchezSinencio, “A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA”, IEEE Journal of Solid State Circuits, Vol. 43, No. 3, March 2008.

[17] Yashpal Yadav and CRS Kumaar, “Design of p-HEMT based Low Noise Amplifier for RF Applications in „C‟ band”, International Journal ofuEngineering Science and Innovative Technology, Vol4, Issue, March 2015.

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