Integrated Converter Topology with ZVS for Power Factor Correction

IJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 04, 2016 | ISSN (online): 2321-0613

Integrated Converter Topology with ZVS for Power Factor Correction Anitha1 Dr.B V Sumangala2 M.Tech Student 2Professor & HOD 2 Department of Electrical & Electronic Engineering 1,2 Dr.Ambedkar Institute of Technology, Bengaluru 1

Abstract— This project proposes an integrated Boost-Buck converter to correct power factor at the front end of the ACDC converter module. Circuit topology integrates boost and buck converter. Power factor correction is taken care by boost converter and DC output regulation is taken care by buck converter. With this proposed topology zero voltage transition is made in the circuit naturally without use of any auxiliary circuit or switch. MATLAB software is used to carry out the simulation work. A low voltage prototype is done for testing the performance in the open loop.

Key words: Boost converter, buck converter, Discontinuous Conduction Mode (DCM), Zero-Voltage Switching (ZVS), Power Factor Correction (PFC) I. INTRODUCTION There are numerous ways to make almost sinusoidal line current. Boost or buck-boost converter has simple circuit and control which are extensively used for improving power factor [1]. To reach unity power factor, both converters voltage at the output side must be greater than magnitude of the ac line voltage. Accordingly, AC-DC converter consists of two-phases to get high power factor. First Phase power factor correction and second phase supplying stable DC output voltage to load [2-3]. The disadvantage of this twophase it takes power conversion approaches which simply introduces few losses which encompass switching losses, conduction losses and magnetic core loss.

Sepic and cuk converters also do power factor correction and stabilizes DC output [4-5].Cuk and sepic converter are the combination of boost and buck converter, both these converters have simple circuit topology which includes only a diode and active switch. The drawback of using these converters are excessive switching losses and high spike current this is because of energy stored in the parasitic capacitor discharges. By synchronous rectification technique the cuk and sepic converters are made to operate in critical conduction mode (CRM), timing of the switches has to be adjusted in this technique using additional circuit which is a disadvantage [6].

Many single stage AC-DC converters are designed by recent researchers. The single stage methodologies that associate PWM converter moreover have a few drawbacks which restrict further improving the circuit performance.

Drawback of this converter is hard switching operation of the switches which causes high current and voltage stress on components of the circuit, high switching losses this result in the poor efficiency and circuit balance [7-8].

This paper proposes a new circuit topology that consists of integrated boost-buck converter along with the zero voltage switching for correcting power factor at the front end of AC-DC converter which decreases switching losses, high current and voltage stress.

II. CIRCUIT CONFIGURATION AND OPERATION MODES For solving hard Switching problem, a new ac/dc converter is proposed, as shown in Fig. 1.The proposed circuit mainly consists of a diode-bridge rectifier (D1- D4), low-pass filter (Lm and Cm), a boost converter and a buck converter.

MOSFETs S1 and S2 play the roles of active switches and the antiparallel diodes DS1 and DS2 are their intrinsic body diodes, respectively. The boost converter is composed of Lp, DS1, S2 and Cdc and the buck converter is composed of Lb, D5, DS2, S1 and Co. Both converters operate at a high-switching frequency, fs. The boost converter corrects the power factor.

Low pass filter removes high frequency current components of inductor current. By this way, the boost converter can wave shape the input line current and input voltage to be in sinusoidal and in phase. The buck converter regulates the output voltage of the boost converter to supply stable dc voltage. For achieving ZVS buck converter designed to operate at DCM. To prevent cross conducting of the switches dead time is provided. Neglecting the short dead time, the duty cycle of vGS1 and vGS2 is 0.5.

Fig. 1: Proposed AC-DC converter For simplifying the circuit analysis, the following assumptions are made: 1) The semiconductor devices are ideal except for the MOSFETs parasitic output capacitance 2) The capacitances of Cdc and Co are large enough that the dc-link voltage Vdc and the output voltage Vo can be regarded as constant.

The circuit operation can be divided into eight modes in every cycle.

MODE 1: Mode 1 starts when the switch S1 is made to turn off by gate voltage, VGS1. Buck inductor current ib deviates from S1 to flow through the output capacitance. Correspondingly Capacitance CDS1 and CDS2 are charged and discharged. Boost inductor current starts to increase, when the rectified input voltage Vrec is more than the voltage VDS2 .The moment VDS2 reaches -0.7V, DS2 turns on and at this stage mode 1 ends.

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Integrated Converter Topology with ZVS for Power Factor Correction (IJSRD/Vol. 4/Issue 04/2016/301)

MODE 2: VDS2 is maintained about -0.7V by antiparallel diode at beginning of the mode 2. S2 is made to turn on by the gate voltage VGS2. If S2 on-resistance is small enough, majority of ib current flows through S2 from source to drain path. Lb and Lp voltages are equal to đ?‘Łđ?‘? (đ?‘Ą) = −đ?‘‰đ?‘œ (1) đ?‘Łđ?‘? (đ?‘Ą) = đ?‘Łđ?‘&#x;đ?‘’đ?‘? (đ?‘Ą) = đ?‘‰đ?‘š | sin(2đ?œ‹đ?‘“đ??ż đ?‘Ą)| (2) Time interval of mode 1 is short ib can be expressed as đ?‘‰ đ?‘–đ?‘? (đ?‘Ą) = đ?‘–đ?‘? (đ?‘Ąđ?‘œ ) − đ?‘œ (đ?‘Ą − đ?‘Ąđ?‘œ ) (3) đ??żđ?‘?

From equation (3) ib reduces from crest value.

Boost converter is designed such that it operates in DCM ip increases from 0-Vrec. đ?‘‰ đ?‘‰ |sin(2đ?œ‹đ?‘“đ??żđ?‘Ą)| đ?‘–đ?‘? (đ?‘Ą) = đ?‘&#x;đ?‘’đ?‘? (đ?‘Ą − đ?‘Ąđ?‘œ ) = đ?‘š (đ?‘Ą − đ?‘Ąđ?‘œ ) (4) đ??żđ?‘?

Fig. 2: Mode 1

đ??żđ?‘?

Current ib has two loops, part of which flows through S2 and remaining to ip. Mode 2 ends when ip rises more than ib.

MODE 3: In this mode, ip > ib. current ip has two loops, part of which flows through buck converter while rest of current to switch S2. The direction of current changes from drain to source naturally. Current ib decreases continuously on the other side ip increases. ib reduces to zero at the end of this mode.

MODE 4: In this mode the S2 switch is ON which carries current ip. The buck converter is off because ib is zero and output capacitor supplies load current. Mode 4 ends when switch S2 is made to turn off by gate voltage VGS2.

MODE 5: At the instant of turning off of S2, current ip reaches crest value. Boost inductor current flows through the CDS1 and CDS2 instead of switch S2.At onset of this mode ib is zero, and will start to increase when CDS1 voltage decreases than Vdc-Vo.Mode 5 ends when DS1 turns on.

MODE 6: VDS1 Voltage is maintained to -0.7V at onset of mode 6 by the diode DS1 connected antiparallel.

After the short overlap time the switch S1 is turned on. If S1 switch on-resistance is small enough, almost ip current courses through S1 from source to drain way. LP and Lb can be expressed as đ?‘‰đ?‘? (đ?‘Ą) = đ?‘‰đ?‘&#x;đ?‘’đ?‘? (đ?‘Ą) − đ?‘‰đ?‘‘đ?‘? = đ?‘‰đ?‘š |sin(2đ?œ‹đ?‘“đ??ż đ?‘Ą)| − đ?‘‰đ?‘‘đ?‘?

(5) Vb (t) = Vdc -Vo (6) Neglecting short dead time đ?‘‰ | sin(2đ?œ‹đ?‘“đ??ż đ?‘Ą)|−đ?‘‰đ?‘‘đ?‘? đ?‘–đ?‘? (đ?‘Ą) = đ?‘–đ?‘? (đ?‘Ą4 ) − đ?‘š (đ?‘Ą − đ?‘Ą4 ) (7)

Fig. 3: Mode 2

Fig. 4: Mode3

đ??żđ?‘?

đ?‘–đ?‘? (đ?‘Ą) =

đ?‘‰đ?‘‘đ?‘?− đ?‘‰đ?‘œ đ??żđ?‘?

(đ?‘Ą − đ?‘Ą4 )

(8)

ip has two current loops,. Part of ip flows through switch 1 and rest to buck converter. Mode 6 ends when i b rises more than ip.

MODE 7: ib is greater than the ip during mode7.There are two current loops for ib, Part of which flows through the boost converter and rest to switch S 1.The direction of current changes naturally from drain to source. ip decreases continuously while ib increases. As soon as ip reduces to zero mode ends.

MODE 8: Ib keeps increasing as S1 remains ON. This mode ends when VGS1 becomes lower level to turn off switch S1.operating circuit enters into mode 1 in the next high frequency cycle.

Fig. 5: Mode 4

Fig. 6: Mode 5

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Integrated Converter Topology with ZVS for Power Factor Correction (IJSRD/Vol. 4/Issue 04/2016/301)

Fig. 7: Mode 6

Fig. 10: Theoretical waveforms of the proposed converter III. DESIGN PROCEDURE

Fig. 8: Mode 7

Table I lists the circuit specifications. The input voltage is 230Vrms Âą 10%. The switching frequency is 50 kHz at rated power operation. In this design example, both converters are designed to operate at DCM. The circuit parameters are designed as follows: Calculation of design parameter Vpeak = Vrms ∗ √2 = 230 ∗ √2 = 325V The dc link voltage is given by đ?‘‰đ?‘‘đ?‘? ≼ 2 ∗ đ?‘‰đ?‘š , đ?‘‰đ?‘‘đ?‘? ≤ 2 ∗ đ?‘‰đ?‘œ đ?‘‰đ?‘‘đ?‘? ≼ 2 ∗ 325 = 650 , đ?‘‰đ?‘‘đ?‘? ≤ 2 ∗ 450 = 900 Vdc chosen is 750V đ?‘‰đ?‘‘đ?‘? 750 K= = = 2.3 đ?‘‰đ?‘š 325 Boost inductor value is obtained as đ??żđ?‘? = =

Fig. 9: Mode 8

2 Ćžâˆ—đ?‘‰đ?‘š

đ??ž3

[

[

2

1

2

đ?œ‹

đ?‘˜

đ?œ‹

(1 + sin−1 ) − đ?‘˜ 2 − đ?‘˜]

8∗đ?‘ƒđ?‘œ ∗đ?‘“đ?‘ √đ?‘˜ 2 −1 0.95∗3252 2.33

8∗60∗50∗1000 √2.32 −1

2

1

đ?œ‹

2.3

(1 + sin−1

2

) − 2.32 − ∗ 2.3] đ?œ‹

đ??żđ?‘? = 3.35đ?‘šđ??ť Buck inductor value found to be đ??żđ?‘? =

(đ?‘‰đ?‘‘đ?‘? −đ?‘‰đ?‘œ ) 8∗đ?‘ƒđ?‘œ ∗đ?‘“đ?‘

=

(750−450)∗750 8∗450∗0.13∗50∗1000

= 9.39đ?‘šđ??ť

Low pass filter at input side is taken đ??ś đ?‘–đ?‘ đ?‘?â„Žđ?‘œđ?‘œđ?‘ đ?‘’đ?‘› đ?‘Žđ?‘ 0.47đ?‘˘đ??š đ?‘ đ?‘œ đ??żđ?‘š = 2.16đ?‘šđ??ť đ?‘‰ 450 đ?‘…= = = 3461 đ?‘œâ„Žđ?‘š đ??ź 0.13 Input voltage 230Vrms,50Hz Boost inductor Lp=3.35mH Buck inductor Lb=9.39mH DC link capacitor Cdc=100đ?œ‡đ??š Load capacitor Co=100đ?œ‡đ??š Load resistor Ro=3461ohms Switching frequency fs=50kHz Table 1: Circuit Specification

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as

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Integrated Converter Topology with ZVS for Power Factor Correction (IJSRD/Vol. 4/Issue 04/2016/301)

IV. SIMULATION RESULTS Simulation work is carried out using MATLAB/Simulink software. The input voltage is 230V ac and output voltage is 450V dc with power factor correction to 0.998.

Fig. 11: Simulink model of proposed circuit Closed loop operation of the proposed circuit is carried out to maintain the output voltage of the load to be constant for power reducing from 60W to 1W

Fig. 12: Simulink model of closed loop control of proposed circuit

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Integrated Converter Topology with ZVS for Power Factor Correction (IJSRD/Vol. 4/Issue 04/2016/301)

Fig. 13: Waveforms of VDS1, iS1, VDS2, iS2 Fig. 17: THD of 230 open loop system

Time (sec)

Fig. 14: Output current io =0.13A

Fig. 18: Inductor current of Boost and Buck

Time (sec)

Fig. 15: Output voltage V0=450V

Dc link voltage Vdc(volts)

Fig. 20: Power factor of closed loop 230,50Hz system

Time (sec)

Fig. 16: Dc link voltage Vdc =750V

Fig. 21: THD of 230v, 50Hz closed loop V. HARDWARE IMPLEMENTATION

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Integrated Converter Topology with ZVS for Power Factor Correction (IJSRD/Vol. 4/Issue 04/2016/301)

Fig. 22: Block diagram of hardware Driver circuit is connected to pin 1.1 and 1.2 of microcontroller board (AT89C51) 8051, driver circuit provides gate signals to the switches as shown in Fig.13.60V ac supply is provided to diode bridge rectifier which converters ac to dc and buck converter provides a regulated dc output voltage.

Components used in driver circuit: 1) Diode IN4007 2) Capacitors 1000đ?œ‡đ??š/50đ?‘‰,1000đ?œ‡đ??š/25đ?‘‰ 3) Opto coupler MCT2E 4) Transistors 2N2222,SK100 5) Resistors 1k and 100 ohm 6) Transformer 230/12V Fig. 25: Output voltage Vo =74V

Fig. 23: Hardware of 60V, 50Hz Fig. 26: Dc link voltage Vdc=92V VI. CONCLUSION

Fig. 24: Switching pulse

With the proposed converter topology the front end AC-DC converter power factor is made near to unity i.e. 0.99.The topology integrates boost and buck converter. Boost converter used to improve power factor and buck converter maintains regulated output voltage .using this new topology the zero voltage switching is achieved without use of any additional circuits. Closed loop operation is done in simulation so that the output voltage is maintained constant

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Integrated Converter Topology with ZVS for Power Factor Correction (IJSRD/Vol. 4/Issue 04/2016/301)

from 60W to 1W. Simulation results show that the THD is improved in the closed loop compared with open loop. The results of simulation are practical tested by developing a low voltage of 60V prototype.

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[2] F. Zhang, J. Ni, and Yi Yu, “High power factor AC-DC LED driver with film capacitors,” IEEE Trans. Power Electron., vol. 28, no. 10, Oct. 2013, pp. 4831-4840.

[3] S. S. Lee, S. W. Choi, and G. W. Moon, “Highefficiency active clamp forward converter with transient current build-up (TCP) ZVS technique,” IEEE Trans.

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[5] H. Ma, J. S. Lai, Q. Feng, W. Yu, C. Zheng, and Z. Zhao, “A novelvalley-fill SEPIC-derived power supply without electrolytic capacitors for LED lighting application,” IEEE Trans. Power Electron., vol. 27, no.

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[6] J. W. Yang and H. L. Do, “High-efficiency ZVS ACDC LED driver using a Self-Driven synchronous rectifier,” IEEE Trans. Circuits and Systems—I: Regular Papers, vol. 61,no.8, pp. 2505-2512, Aug. 2014.

[7] Y. C. Hsieh, M. R. Chen, H. L. Cheng, “An Interleaved Fly back Converter Featured with Zero-VoltageTransition”, IEEE Trans. Power Electron., vol. 26, no.

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[8] G. Moschopoulos and P. K. Jain, “Single-phase singlestage power factor-corrected converter topologies,” IEEE Trans. Ind. Electron.,vol. 52, no. 1, pp. 23-35, Feb. 2005.

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