Single Phase Seven-Level PWM Inverter with Reduced Harmonics

IJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 04, 2016 | ISSN (online): 2321-0613

Single Phase Seven-Level PWM Inverter with Reduced Harmonics Aleena T Mathew1 Midhun G2 P.G. Student 2Assistant Professor 1,2 Department of Electrical & Electronic Engineering 1,2 Mar Baselios College of Engineering and Technology, Trivandrum 1

Abstract— Multilevel inverters have received great attention from the industry using high voltage and high power applications. A multilevel inverter can synthesize stepped output voltages similar to a sinusoidal wave. The proposed topology consists of a single dc voltage source with a series of capacitors, diodes, switches and an H-bridge cell.

Computer-aided simulations are performed through MATLAB Simulink software. Referring to the simulation results, based on the THD reduction a comparison study is done with conventional topologies. The proposed topology needs less number of components and carrier signals and THD of proposed topology is less as compared to conventional topologies.

Key words: Multilevel inverter, Phase Disposition (PD), Pulse Width Modulation (PWM), Total Harmonic Distortion (THD) I. INTRODUCTION The concept of multilevel inverter was introduced in 1975. Multilevel inverter provides more than two levels.

A multilevel inverter is a power electronic system that can synthesize stepped output voltages similar to sinusoidal wave. Multilevel inverters received more attentions in recent years due to the demands of high power and high voltage in industrial applications.

The general concept involves utilizing active semiconductor switches to perform the power conversion in small voltage steps. Increasing the number of voltage levels enhance several advantages like reduced harmonic distortion, lower electromagnetic interference and higher dc link voltages. Using multilevel technique, the amplitude of the voltage is increased, stress in the switching devices is reduced and overall harmonics profile is improved.

Plenty of multilevel topologies have been investigated, but only several of them are practical for industrial applications. Among existing multilevel inverters, diode-clamped and cascaded H-bridge multilevel inverters are the most widely used. It exhibits several attractive features such as simple circuit layout, less component counts, modular in structure and avoid unbalance capacitor voltage problem. However as the number of output level increases, the circuit becomes bulky due to the increase in the number of power device.

In this paper, a single phase seven level PWM inverter is proposed. The suggested topology consists of single dc voltage source, capacitors, diodes, switches and an H-bridge cell. Simulations are carried out by MATLAB Simulink software. Based on the reduction in THD, a comparison study is done with conventional topologies.

on a series connection of several single phase inverter typically, it is necessary to connect three to ten inverters in series to reach required output voltage. Each inverter can be seen as a module with similar circuit topology and modulation. This inverter is obtained by connecting Hbridge inverter in series and output is sinusoidal. Compare to the proposed topology it requires more number of components and THD is also greater for seven level output [1].

B. Seven-level PWM Inverter with RV Topology Fig.2 shows the schematic diagram of seven level inverter with RV topology. This topology is a hybrid multilevel topology which separates the output voltage into two parts.

One part is named level generation part and is responsible for level generating in positive polarity. This part requires high frequency switches to generate the required levels. The switches sin this should have high switching frequency capability. The other part is called polarity generation part and is responsible for generating the polarity of the output voltage, which is the low frequency part operating at line frequency. For generating seven level output voltage this topology requires more number of dc voltage sources and switches and also THD of this topology is greater than proposed topology [2]

Fig. 1: Schematic diagram of cascade H-bride seven level inverter

II. CONVENTIONAL TOPOLOGIES A. Cascade H-Bridge Topology Fig.1 shows the schematic diagram of cascade H-bride seven level inverter. Cascaded multilevel inverters are based

Fig. 2: Schematic diagram of seven level inverter with RV topology

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Single Phase Seven-Level PWM Inverter with Reduced Harmonics (IJSRD/Vol. 4/Issue 04/2016/305)

III. PROPOSED TOPOLOGY A. Block Diagram Fig.3 shows a block diagram of the proposed seven-level PWM inverter. It consists of a single dc voltage source, level and polarity generation part and load. The switches in an H-bridge cell provide polarities of the output voltage level with highest (or lowest) voltage level. Other voltage levels are generated by rest of the switches used in the circuit.

Fig. 3: Block Diagram of Seven-Level PWM Inverter B. Detailed Circuit Diagram Fig.4 shows a detailed circuit diagram of the proposed seven-level PWM inverter. It includes single dc voltage source, which is separated by three capacitors connected in series. Each capacitor voltage is considered to đ?‘‰đ?‘‘đ?‘? /3. Then output voltage wave having seven levels, i.e., đ?‘‰đ?‘‘đ?‘? , 2 đ?‘‰đ?‘‘đ?‘? /3, đ?‘‰đ?‘‘đ?‘? /3, 0, - đ?‘‰đ?‘‘đ?‘? /3, - 2đ?‘‰đ?‘‘đ?‘? /3, - đ?‘‰đ?‘‘đ?‘? . đ?‘‰đ?‘‘đ?‘? (or- đ?‘‰đ?‘‘đ?‘? ) is determined by the switches đ?‘†1 Ě´ đ?‘†4 .Other voltage levels are produced by đ?‘†5 , đ?‘†6 and đ?‘†7 .

pulse width modulation is adopted to control the inverter. It uses a reference and three carrier waves for modulation.

Here all carriers are in phase, which have the same frequency and amplitude but different offset voltages. Table 1 gives the switching states of each switch for generating output voltage levels. Command signals are produced by comparing the reference and each carrier wave in [3].

Fig. 5: Switching scheme for proposed topology SWITCHING STATES OUTPUT VOLTAGE đ?‘†1 đ?‘†2 đ?‘†3 đ?‘†4 đ?‘†5 đ?‘†6 đ?‘†7 đ??¸0 0 1 1 0 0 0 0 - đ?‘‰đ?‘‘đ?‘?

0 0 1 0 0 1 0 - 2đ?‘‰đ?‘‘đ?‘? /3 0 0 1 0 0 0 1 - đ?‘‰đ?‘‘đ?‘? /3 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 đ?‘‰đ?‘‘đ?‘? /3 0 0 0 1 1 0 0 2 đ?‘‰đ?‘‘đ?‘? /3 1 0 0 1 0 0 0 đ?‘‰đ?‘‘đ?‘?

Table 1: Output Voltage Levels with Switching States IV. SIMULATION

Fig. 4: Circuit Diagram of Proposed Topology

Simulation of proposed seven-level PWM inverter, cascaded H-bridge and seven-level PWM inverter with RV topology are done in MATLAB. A comparative study is done between conventional topologies and proposed work for the analysis of THD reduction. Fig.6 shows the simulink model of proposed seven-level PWM inerter. It uses sine wave as reference and three triangular waves as carriers. By comparing these, command signals are produced and it provides the switching pulses for each switch and sevenlevel output voltage is obtained. Fig.7 shows the output voltage with seven levels.

C. Switching Sequences Fig.5 shows the switching scheme for producing seven-level PWM output voltage. PD (Phase disposition) sinusoidal

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Single Phase Seven-Level PWM Inverter with Reduced Harmonics (IJSRD/Vol. 4/Issue 04/2016/305)

Fig. 6: Simulink model of proposed seven-level PWM inverter

Fig. 7: Seven-level PWM output voltage with R load (��� = 150�; x axis=0.1sec/div; y axis= 50V/div)

Fig. 8: Harmonic spectrum of proposed seven-level PWM inverter

V. FFT ANALYSIS The harmonics in the output current of the conventional and proposed topologies were done in FFT and compared based on THD point of view.

Multilevel inverter THD (%) for seven level topologies output current Proposed multilevel 0.63% inverter Multilevel inverter with 4.18% RV topology Cascade H-Bridge 43.79% multilevel inverter Table 2: Comparison of THD in Output Current

Fig. 9: Harmonic spectrum of RV topology

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Single Phase Seven-Level PWM Inverter with Reduced Harmonics (IJSRD/Vol. 4/Issue 04/2016/305)

Fig. 10: Harmonic spectrum of cascade H-bridge topology Harmonic spectrum of three topologies as shown in Fig. 8, Fig. 9 and Fig.10. Table II shows the THD of each topologies, according to this concluded that proposed topology have less THD compared to the conventional topologies.

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2643-2650, Aug. 2010.

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60, no. 5, pp. 1943-1954, May 2013.

VI. CONCLUSION In this paper, a single phase seven level PWM inverter is presented. Simulations are done in MATLAB and concluded that the proposed multilevel inverter that can effectively increase the number of output voltage levels with simple PWM control and less number of components. Also harmonic analysis between conventional and proposed scheme is done in terms of THD point of view and observed that in the proposed topology, THD is negligible compared with conventional topologies.

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