IJSTE - International Journal of Science Technology & Engineering | Volume 4 | Issue 5 | November 2017 ISSN (online): 2349-784X
Design and Analysis of Low Power High Speed Carry Select Adder using GDI Technique Manisha Singh M. Tech. Scholar Department of Electronics and Communication NIELIT Gorakhpur, India
Nishant Tripathi Scientist C Deputy Director Department of Electronics and Communication NIELIT Gorakhpur, India
Abstract In this paper, GDI technique implementation of modified Carry Select Adder is presented for the low power applications. The proposed Carry Select Adder can be used RCA using GDI and same size of BEC (binary to excess-1) and Multiplexer. Simulation is performed in T-SPICE using 45nm technology parameters. The results have been compared with 16-bit Regular SQRT-CSA BK using BEC and proposed 16-bit CSA using GDI technique. The performance of the designs is compared in terms of area, power and delay. Comparative analysis shows that the proposed CSA using GDI technique has reduced area and consumes less power. Keywords: CSA, Low Power VLSI, GDI, RCA ________________________________________________________________________________________________________ I.
INTRODUCTION
Area and power reduction in data path logic systems are the main area of research in VLSI system design. High speed addition and multiplication has always been a fundamental requirement of high-performance processors and systems. Addition is one of the four elementary operations in mathematics, the other being subtraction, multiplication and division. In digital systems, addition forms the most important operation. This is primarily because we can perform operations like subtraction, multiplication and division using the addition operation. Hence the design of a very fast, accurate and a lower power consumption adder directly results in the increased speed of the device for faster computational purpose as well as an improved life. Adders play a role of heart for computational circuits and other complex arithmetic circuits, based on its addition. Its arithmetic functions attracts a lot of researcher’s attention to adder for mobile applications. These adder cells mainly designed to increase speed and also to reduce more power consumption. Various approaches realizing adders CMOS technologies also investigated by these studies. It is necessary for designers to work within a very tight leakage power specification in order to meet product battery life and package cost objectives for mobile applications. Adder is still plays an important role though many people focus on more complex computation such as multiplier, divider circuits in arithmetic computations. There is no general architecture for measuring performance equally, so several algorithms are implemented in literature to overcome issues after under different conditions which possibly result in variable performance even implemented with the same algorithm. It uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input Cin and Cout then the final sum and carry are selected by the multiplexers (MUX) because, the CSA is not area efficient. Depends upon the great extent on the type of design style used for implementation as well as the logic function realized using the particular design style, full adder performs their function. To achieve a reasonable power delay product with high noise margins, with relatively higher tolerance to process variations, CMOS implementation allows circuits. II. OBJECTIVE The proposed research discusses a comprehensive investigation of carry select adder using GDI technique with primary focus on dynamics parameter such as power, area and delay. In CSA, all possible values of the input carry i.e. 0 and 1 are defined. Carry select adder is designed using RCA, BEC and then there is a multiplexer stage. Here, one Brent Kung adder is replaced by RCA. Also the CSA is designed using GDI technique in order to reduce the power delay of adder. The main objective of this thesis is to implement proposed architecture carry select adder using GDI technique and compare area and power with regular square root CSA Brent Kung adder using BEC. III. PROPOSED WORK Proposed Carry Select Adder using Gate Diffusion Input (GDI) technique has been designed. There are 4 groups. Each group contains one RCA, one BEC and one MUX. Each group has same size of RCA, Binary to Excess-l Converter (BEC) and MUX. BEC is used to add 1 to the input numbers. Less number of logic gates are used to design to Proposed 16- Bit Carry Select Adder
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Design and Analysis of Low Power High Speed Carry Select Adder using GDI Technique (IJSTE/ Volume 4 / Issue 5 / 010)
using GDI technique as compared to regular Square Root Brent Kung Carry Select Adder using BEC therefore proposed consumes less area and power.
Fig. 1: Proposed Carry Select Adder Design using GDI technique
Fig. 2: Waveform for Proposed Design
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Design and Analysis of Low Power High Speed Carry Select Adder using GDI Technique (IJSTE/ Volume 4 / Issue 5 / 010)
Adder Base Paper Results Modified Designs Results using GDI technique
Power 43.20 uW 31.82 uW
Delay 1.572 ns 0.705 ns
PDP 67.91 f 22.43 f
IV. CONCLUSION AND FUTURE SCOPE This paper presents logic style comparisons based on different logic functions and claimed Gate Diffusion Input logic (GDI) to be much more power-efficient than complementary CMOS logic design. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder. Thus, the implementations of different GDI adders have been suggested in this thesis. The work shows that proposed Carry Select Adder using GDI technique has less area and consumes less power. Also it provides reduced delay comparatively and therefore can be used in various processors in order to perform fast arithmetic operations. The simulation results for power, delay and PDP proves the significance of the GDI technique for low power applications. The work can be extended in the future for the further advancement in the technology and better chip area utilization. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9]
Shivani Parmar and Kirat Pal Singh," Design of High Speed Hybrid Carry Select Adder", IEEE's 3rd International Advance Computing Conference (IACC) Ghaziabad, ISBN: 978-1-4673-4527-9, 22-23 February 2013. Yajaun He, Chip-Hong Chang, and Jiangmin Gu, "An area efficient 64-Bit square Root carry-select adder for low power Applications, " in Proc. IEEE International Symposium Circuits and Systems, vol. 4, pp. 4082-4085,2005. M. Snir, "Depth-Size Trade-Offs for Parallel Prefix Computation", Journal of Algorithms, Vo!.7, Issue-2, pp.185-201, June 1986. David Jeff Jackson and Sidney Joel Hannah, "Modelling and Comparison of Adder Designs with Verilog HDL", 25th South-eastern Symposium on System Theory, pp.406-4tO, March 1993. Belle W.Y. Wei and Clark D. Thompson, "Area-Time Optimal Adder Design", IEEE transactions on Computers, vo!.39, pp. 666-675, May1990. Y. Choi, "Parallel Prefix Adder Design", Proc. 17th IEEE Symposium on Computer Arithmetic, pp. 90-98, 27th June 2005. J. M. Rabaey, "Digital Integrated Circuits- A Design Perspective", New Jersey, Prentice-Hall, 2001. R. Brent and H. Kung, "A regular layout for parallel adders", IEEE Transaction on Computers, vol. C-31,n o.3,p p. 260-264,M arch 1982. Adilakshmi Siliveru, M. Bharathi, "Design of Kogge-Stone and BrentKung adders using Degenerate Pass Transistor Logic", International Journal of Emerging Science and Engineering, Vol.-I, Issue-4, February 2013.
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