8086 Cheat Sheet

Intel Assembler 80186 and higher

CodeTable 1/2

© 1996-2003 by Roger Jegerlehner, Switzerland V 2.3 English. Also available in Spanish

TRANSFER Name Comment MOV Move (copy) XCHG Exchange

Code MOV Dest,Source XCHG Op1,Op2

Operation Dest:=Source Op1:=Op2 , Op2:=Op1

STC CLC CMC STD CLD STI CLI

Set Carry Clear Carry Complement Carry Set Direction Clear Direction Set Interrupt Clear Interrupt

STC CLC CMC STD CLD STI CLI

CF:=1 CF:=0 CF:= ¬ CF DF:=1 (string op's downwards) DF:=0 (string op's upwards) IF:=1 IF:=0

PUSH PUSHF PUSHA POP POPF POPA

Push onto stack Push flags Push all general registers Pop from stack Pop flags Pop all general registers

PUSH Source PUSHF PUSHA POP Dest POPF POPA

DEC SP, [SP]:=Source O, D, I, T, S, Z, A, P, C 286+: also NT, IOPL AX, CX, DX, BX, SP, BP, SI, DI Dest:=[SP], INC SP O, D, I, T, S, Z, A, P, C 286+: also NT, IOPL DI, SI, BP, SP, BX, DX, CX, AX

CBW CWD CWDE

Convert byte to word Convert word to double Conv word extended double

CBW CWD CWDE

AX:=AL (signed) DX:AX:=AX (signed) EAX:=AX (signed)

O D

I

Flags T S Z A P C

1 0 ± 1 0 1 0

±

±

±

±

±

±

±

±

±

±

IN i Input IN Dest, Port AL/AX/EAX := byte/word/double of specified port OUT i Output OUT Port, Source Byte/word/double of specified port := AL/AX/EAX i for more information see instruction specifications Flags: ±=affected by this instruction ?=undefined after this instruction ARITHMETIC Flags Name Comment Code Operation O D I T S Z ADD Add ADD Dest,Source Dest:=Dest+Source ± ± ± ADC Add with Carry ADC Dest,Source Dest:=Dest+Source+CF ± ± ± SUB Subtract SUB Dest,Source Dest:=Dest-Source ± ± ± SBB Subtract with borrow SBB Dest,Source Dest:=Dest-(Source+CF) ± ± ± DIV Divide (unsigned) DIV Op Op=byte: AL:=AX / Op AH:=Rest ? ? ?

DIV Divide (unsigned) DIV Op Op=word: AX:=DX:AX / Op DX:=Rest ? ? ?

DIV 386 Divide (unsigned) DIV Op Op=doublew.: EAX:=EDX:EAX / Op EDX:=Rest ? ? ?

IDIV Signed Integer Divide IDIV Op Op=byte: AL:=AX / Op AH:=Rest ? ? ?

IDIV Signed Integer Divide IDIV Op Op=word: AX:=DX:AX / Op DX:=Rest ? ? ?

IDIV 386 Signed Integer Divide IDIV Op Op=doublew.: EAX:=EDX:EAX / Op EDX:=Rest ? ? ?

MUL Multiply (unsigned) MUL Op Op=byte: AX:=AL*Op if AH=0 ♦ ± ? ?

MUL Multiply (unsigned) MUL Op Op=word: DX:AX:=AX*Op if DX=0 ♦ ± ? ?

MUL 386 Multiply (unsigned) MUL Op Op=double: EDX:EAX:=EAX*Op if EDX=0 ♦ ± ? ?

IMUL i Signed Integer Multiply IMUL Op Op=byte: AX:=AL*Op if AL sufficient ♦ ± ? ?

IMUL Signed Integer Multiply IMUL Op Op=word: DX:AX:=AX*Op if AX sufficient ♦ ± ? ?

IMUL 386 Signed Integer Multiply IMUL Op Op=double: EDX:EAX:=EAX*Op if EAX sufficient ♦ ± ? ?

INC Increment INC Op Op:=Op+1 (Carry not affected !) ± ± ± DEC Decrement DEC Op Op:=Op-1 (Carry not affected !) ± ± ±

A ± ± ± ± ? ? ? ? ? ? ? ? ? ? ? ? ± ±

P ± ± ± ± ? ? ? ? ? ? ? ? ? ? ? ? ± ±

C ± ± ± ± ? ? ? ? ? ? ± ± ± ± ± ±

CMP

Compare

386

CMP Op1,Op2

SAL Shift arithmetic left (≡ SHL) SAL Op,Quantity SAR Shift arithmetic right SAR Op,Quantity RCL Rotate left through Carry RCL Op,Quantity RCR Rotate right through Carry RCR Op,Quantity ROL Rotate left ROL Op,Quantity ROR Rotate right ROR Op,Quantity i for more information see instruction specifications LOGIC Name Comment Code NEG Negate (two-complement) NEG Op NOT Invert each bit NOT Op AND Logical and AND Dest,Source OR Logical or OR Dest,Source XOR Logical exclusive or XOR Dest,Source SHL SHR

Shift logical left Shift logical right

(≡ SAL)

SHL Op,Quantity SHR Op,Quantity

Op1-Op2

±

±

±

±

±

±

±

±

±

±

±

i i i i i i

± ±

± ±

? ?

± ±

± ± ± ± ± ±

♦ then CF:=0, OF:=0 else CF:=1, OF:=1

Operation Op:=0-Op if Op=0 then CF:=0 else CF:=1 Op:=¬ Op (invert each bit) Dest:=Dest∧ Source Dest:=Dest∨Source Dest:=Dest (exor) Source

O D ±

I

Flags T S Z A P C ± ± ± ± ±

0 0 0

± ± ±

± ± ±

? ? ?

± ± ±

0 0 0

i i

± ±

± ±

? ?

± ±

± ±

Download latest version free of charge from www.jegerlehner.ch/intel This page may be freely distributed without cost provided it is not changed. All rights reserved

© 1996-2003 by Roger Jegerlehner, Switzerland V 2.3 English. Also available in Spanish

CodeTable 2/2

Intel Assembler 80186 and higher MISC Name NOP

Comment No operation

Code NOP

Operation No operation

LEA

Load effective address

LEA Dest,Source

Dest := address of Source

INT

Interrupt

INT Nr

interrupts current program, runs spec. int-program

JUMPS (flags remain unchanged) Name Comment CALL Call subroutine

Code CALL Proc

JMP

Jump

JMP Dest

JE JZ JCXZ JP JPE

Jump if Equal Jump if Zero Jump if CX Zero Jump if Parity (Parity Even) Jump if Parity Even

JUMPS Unsigned (Cardinal) JA Jump if Above JAE Jump if Above or Equal JB Jump if Below JBE Jump if Below or Equal JNA Jump if not Above JNAE Jump if not Above or Equal JNB Jump if not Below JNBE Jump if not Below or Equal JC Jump if Carry JNC Jump if no Carry

Operation

JE Dest JZ Dest JCXZ Dest JP Dest JPE Dest

(≡ JZ) (≡ JE)

JNE JNZ JECXZ JNP JPO

Jump if not Equal Jump if not Zero Jump if ECX Zero Jump if no Parity (Parity Odd) Jump if Parity Odd

JNE Dest JNZ Dest JECXZ Dest JNP Dest JPO Dest

(≡ JNZ) (≡ JNE)

JA Dest JAE Dest JB Dest JBE Dest JNA Dest JNAE Dest JNB Dest JNBE Dest JC Dest JNC Dest

(≡ JNBE) (≡ JNB ≡ JNC) (≡ JNAE ≡ JC) (≡ JNA) (≡ JBE) (≡ JB ≡ JC) (≡ JAE ≡ JNC) (≡ JA)

JG Dest JGE Dest JL Dest JLE Dest JNG Dest JNGE Dest JNL Dest JNLE Dest JO Dest JNO Dest JS Dest JNS Dest

(≡ JNLE) (≡ JNL) (≡ JNGE) (≡ JNG) (≡ JLE) (≡ JL) (≡ JGE) (≡ JG)

(≡ JPE) (≡ JP)

AL 87

0

EDX 386 DX DH

DL Data mul, div, IO

31

24 23

16 15

87

0

ECX 386 CX CH

CL Count loop, shift

31

24 23

16 15

87

0

EBX 386 BX BH

BL BaseX data ptr

31 Flags:

24 23

16 15

87

- - - - OD I T S

0

Code RET

Accumulator 16 15

0

Comment Return from subroutine

AX

24 23

Flags T S Z A P C

Name RET

EAX 386

31

I

Operation

General Registers:

AH

O D

0

-A- P-C

Control Flags (how instructions are carried out): D: Direction 1 = string op's process down from high to low address I: Interrupt whether interrupts can occur. 1= enabled T: Trap single step for debugging

JUMPS Signed (Integer) JG Jump if Greater JGE Jump if Greater or Equal JL Jump if Less JLE Jump if Less or Equal JNG Jump if not Greater JNGE Jump if not Greater or Equal JNL Jump if not Less JNLE Jump if not Less or Equal JO Jump if Overflow JNO Jump if no Overflow JS Jump if Sign (= negative) JNS Jump if no Sign (= positive) Example: .DOSSEG .MODEL SMALL .STACK 1024 Two EQU 2 .DATA VarB DB ?

VarW DW 1010b VarW2 DW 257 VarD DD 0AFFFFh S DB "Hello !",0 .CODE main: MOV AX,DGROUP MOV DS,AX MOV [VarB],42 MOV [VarD],-7 MOV BX,Offset[S] MOV AX,[VarW] ADD AX,[VarW2] MOV [VarW2],AX MOV AX,4C00h INT 21h END main

386

(≡ JPO) (≡ JNP)

; Demo program

; Const ; define Byte, any value ; define Word, binary ; define Word, decimal ; define Doubleword, hex ; define String ; resolved by linker ; init datasegment reg ; init VarB ; set VarD ; addr of "H" of "Hello !" ; get value into accumulator ; add VarW2 to AX ; store AX in VarW2 ; back to system

Status Flags (result of operations): C: Carry result of unsigned op. is too large or below zero. 1 = carry/borrow O: Overflow result of signed op. is too large or small. 1 = overflow/underflow S: Sign sign of result. Reasonable for Integer only. 1 = neg. / 0 = pos.

Z: Zero result of operation is zero. 1 = zero A: Aux. carry similar to Carry but restricted to the low nibble only P: Parity 1 = result has even number of set bits

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