IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 33-39 IMPACT FACTOR 1.719 www.iord.in
IMPLIMENTATION OF ADVANCED ENCRYPTION ALGORITHM (AES) Mr. Nilesh Umate1, Ku. Shubhangi Dhengre2 Department Of electronics and communication Abha Gaikwad-Patil College of Engineering & Technology Nagpur (MH) 1, 2 Email: knileshumate@gmail.com1
Abstract- This Paper includes implementation of (AES) Advanced Encryption Technique means to encryption and decryption of data is 128 bit using the AES and its modified high security and reliability. The process of encryption consists of the combination of various classical techniques known as rearrangement, substitution and transformation encoding techniques. The encrypting and decrypting modules include the expansion of key which generates Key for all iterations. Cryptography importance are applied to security in electronic data transactions has acquired an essential relevance during the last few years. The many users Interchanges and generates large volumes of information in various fields, such as bank services, legal files and financial, via Internet and medical reports and other examples used to special treatment from the security point of view, transport as well as storage. In this paper cryptography techniques are especially applicable. The AES implementation will be useful in wireless security application like mobile telephony and military communication where there is a greater emphasis on these speed of communication. The Very high speed integrated circuit Hardware Descriptive Language of the design has been coded. All the results are simulated and synthesized using Xilinx ISE and ModelSim software respectively. This AES implementation is compared with other works to show the clock reduces and high efficiency.
Index Terms- VHDL, Encryption, Decryption, AES, Cipher text, FPGA.
I.
INTRODUCTION
AES algorithm is already supported by a few international standards at present, and AES algorithm is widely applied in the financial field in domestic, such as realizing authenticated encryption in ATM, magnetism card and intelligence card. After the first round of analysis was concluded in August 1999, the number of candidates was reduced to final five. The five algorithms selected RIJNDAEL, TWOFISH and SERPENT. The conclusion was that the five competitors showed same characteristics. On October 2nd 2000, by NIST announced that the Rijndael Algorithm as the winner of the contest. The primary criteria used by NIST to evaluate AES candidates included security, efficiency in software and hardware, and flexibility. Rijndael Algorithm developed by Joan Daemen and Vincent Rijmen. Was chosen since it had the best overall scores in performance, security, efficiency, implementation ability and flexibility. Hence chosen as the standard AES (Advanced Encryption Standard)
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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 33-39 IMPACT FACTOR 1.719 www.iord.in algorithm’s a symmetric block cipher that can process data blocks of 128 bits through the use of cipher keys with lengths of 128, 192, and 256 bits. The hardware implementation of the Rijndael algorithm can provide either high performance or low cost for specific applications. Cryptographic algorithms are most efficiently implemented in custom hardware than in software running on general purpose processors. The hardware implementations are of extreme importance in case of high performance, security against system intruders and busy systems, where a cryptographic task consumes too much time. Traditional ASIC solutions have the well-known drawback of reduced flexibility compared to software solutions. Hence the implementation of the AES algorithm based on FPGA devices has certain advantages over the implementation based on ASICs. One new AES algorithm with 128-bit keys (AES128) was described this paper, which has realized in VHDL. The 128-bit plaintext and 128-bit key, as well as the 128-bit output data are divided into all four 32-bit consecutive units respectively.
II. THE PROPOSED ARCHITECTURE
First, Substitution has Sub Byte and Inverse Sub Byte transformation in state matrix is replaced with a Sub Byte using an 8-bit data from AES S-Box. Secondly, Shift Row is cyclically shifts the bytes in each row by certain offset to the left. Then Mix Column is four bytes of each column of state are combined using an invertible linear transformation. Lastly, Add Round Key has bitwise XOR operation is performed between outputs from Mix Column and Round Key. AES decryption consists of four inverse operations of encryption which are compliment functions of encryption. They are Inverse Substitution, Inverse Shift Row, Inverse Mix Column, Key addition. AES key generation module is common unit gives necessary key expansion for both encryption and decryption functions.
Fig 1 AES Encryption and Decryption Algorithm
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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 33-39 IMPACT FACTOR 1.719 www.iord.in
III. METHODOLOGY AND IMPLIMENTATION The AES algorithm is a symmetric block cipher that cans encryption and decryption information. Encryption converts data to a unintelligible form called ciphertext. Decryption of the cipher-text converts the data back into it’s a original, which is called plain-text. 3.1. SUBBYTE TRANSFORMATION In SubBytes transformation there is a non-linear byte substitution, operating on each of the state bytes independently as shown in figure 2 The SubBytes transformation is done using a once-precalculated substitution table called S-box.
Fig 2 Subbyte Transformation
3.2. SHIFTROWS TRANSFORMATION In ShiftRows transformation, the rows of the state are cyclically left shifted. Row 0 is not shifted; row 1 is shifted one byte to the left; row 2 is shifted two bytes to the left and row 3 is shifted three bytes to the left as shown in figure 3.
Fig 3 Shiftrow Transformation
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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 33-39 IMPACT FACTOR 1.719 www.iord.in
3.3. MIXCOLUMNS TRANSFORMATION In MixColumns transformation, the columns of the state are considered as polynomials over GF (28). MixColumn operation performs column by column state, treating each column as a four-term polynomial over GF (28 ) .As a result of this multiplication, the new four bytes in a column are generatedas shown in figure 4.
Fig 4 Mixcolumn Transformation
3.4. ADDROUNDKEY In the AddRoundKey transformation, a Round Key is added to the State - resulted from the operation of the MixColumns transformation - by a simple bitwise XOR operation shown in figure 5. The RoundKey of each round is derived from the main key using the KeyExpansion algorithm. The encryption/ decryption algorithm needs eleven 128-bit RoundKey, which are denoted RoundKey[0] RoundKey[10].
Fig 5 Addround Transformation
IV. SIMULATION RESULT
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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 33-39 IMPACT FACTOR 1.719 www.iord.in
AES Encryption and Decryption Module, When RST is ‘0’, 128 bit Data_in and 128 bit Key in is applied as input to encryption algorithm we get encrypted 128 bit Cipher_out data shown in figure 6. At decryption side already user will have key used for encryption, same key is used in reverse order to decrypt the data. 128 bit enccrypted data Cipher_out with key is applied as input to decryption algorihm will provide us plaintext reffered as Data_out. Simulation results and synthesis results are shown on ModelSim 6.3f software shown and Xilinx ISE 13.1 software shown respectively.
Fig 6 AES Encryption and Decryption Module
Fig 7 Simulation result of Encryption code The simulation waveform is shown in Figure 7 and in Figure 8, in which plaintext_in and key_in are applied as input. When rst signal is ‘0’ and sys_clk is applied and aes_en is ‘1’, we will get encrypted data called as ciphertext after some delay. And when we will change sttus of signal aes_in to ’0’ we will get decrypted date back called as plaintext. Latency for encryption is 44 clock cycles and for decryption is 61 clock cycles.
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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 33-39 IMPACT FACTOR 1.719 www.iord.in
Fig 8 Simulation result of Decryption code In synthesis report number of logic utilised is shown in table 1. AES algorithm design is implemented separately on Xilinx XC3S500E Spartan-3E FPGA kit. V. COMPARISIONS
In synthesis report number of logic utilised is shown in table 1. AES algorithm design is implemented separately on Xilinx XC3S500E Spartan-3E FPGA kit. We calculate parameters like throughput and latency, for encryption and decryption design separately. Results obtained are compared with previous reported result shown in table 1. Throughput achieved for encryption is 672.52 Mbps, for decryption is 603.59Mbps.
Table 1 Comparative Analysis of AES algorithm result
VI. CONCLUSION
It has been observed that the implementation of AES Encryption and decryption on the FPGA is successful for several data input. The cipher key can be changed with respect to the user requirements. Efficient hardware
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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 33-39 IMPACT FACTOR 1.719 www.iord.in implementation of AES algorithm is presented in this paper. The whole process AES Encryption and AES Decryption is completed in 230.92MHz clock rate. Throughput achieved for encryption is 672.52 Mbps, for decryption is 603.59Mbps and for whole AES process is 281.5Mbps. High throughput is achieved in this design; results are compared with previous reported designs result. Latency for encryption is 44 clock cycles and for decryption is 61 clock cycles. Simulation of AES algorithm is done on ModelSim 6.3f software and implemented on Xilinx XC3S500E Spartan-3E FPGA kit.
VII. REFERENCES [1]Hoang Trang and Nguyen Van, “An efficient FPGA implementation of the Advanced Encryption Standard algorithm”,IEEE (2012). [2]Mg Suresh, Dr.Nataraj.K.R, “Area Optimized and Pipelined FPGA Implementation of AES Encryption and Decryption”, International Journal Of Computational Engineering Research (ijceronline.com) Vol. 2 Issue. 7, November 2012. [3]WANG Wei, CHEN Jie& XU Fei, “An Implementation of AES Algorithm Based on FPGA”,IEEE (2012). [4]Samir El Adib and Naoufal Raissouni, AES Encryption Algorithm Hardware Implementation Architecture: Resource and Execution Time Optimization, International Journal of Information & Network Security (IJINS) Vol.1, No.2, June 2012, [5]A. Amaar, I. Ashour and M. Shiple, “Design and Implementation A Compact AES Architecture for FPGA Technology”, World Academy of Science, Engineering and Technology 59, 2011. [6]Mr. Atul M. Borkar, Dr. R. V. Kshirsagar and Mrs. M. V. Vyawahare, “FPG A Implementation of AES Algorithm”, International Conference on Electronics Computer Technology (ICECT), pp. 401-405, 2011 3rd. [7]Pravin B. Ghewari, Mrs. Jaymala K. Patil and Amit B. Chougule, “Efficient Hardware Design and Implementation of AES Cryptosystem”, International Journal of Engineering Science and Technology Vol. 2(3), 2010. [8]Yang Jun Ding Jun Li Na GuoYixiong, “FPGA based design and
implementation of reduced AES
algorithm”,IEEE (2010).
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