Iord0814b

IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 08-11 IMPACT FACTOR 1.719 www.iord.in

A Survey Of Area Efficient And Low Power Carry Select Adder.

Gauravkumar D. Jade, Asst.Prof.Ashish Panchal, Prof.Sharad Jain gauravjade87@gmail.com, er.ashishpanchal@gmail.com, sharadjainani@gmail.com Lord Krishna College Of Technology, Indore(M.P).

Abstract— Digital adder with optimum area & speed is one of the important areas of research in VLSI system design. With optimum area & speed, reducing the power consumption is also important area of research in VLSI system design. Our approach uses carry select adder configuration for the implementation of fast adder. There are different choices for implement carry select adder. Carry select adder (CSLA) is one of the fastest adders and in many data processing processors to perform fast arithmetic function. From the structure of the CSLA, it is clear that there is a scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power consumption of CSLA. We compare some of these methods with existing conventional fast adder architecture to prove its efficiency.

Index Term— Literature Survey, Conventional Adder Circuits, Proposed CSLA Architecture.

I.

INTRODUCTION

Design of high speed digital adders with efficient area and power is one of the important areas of research in VLSI system design. Adders are the key components in general purpose microprocessors and digital signal processors. The Ripple Carry Adders (RCAs) have the most compact design among all types of adders, they are the slowest types of adders. On the other hand, Carry Look-ahead Adders (CLAs) are the fastest adders, but they are not so good from the area point of view. Carry Select Adders (CSAs) have been considered as a compromise solution between RCAs and CLAs because they offer a good tradeoff between the compact area of RCAs and the short delay of CLAs. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an each adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position.

The CSLA used in many arithmetic systems to solve the problem of carry propagation delay by independently generating multiple carrys and then select a carry to generate the final sum [1] [2]. However, the CSA is not area efficient because it uses multiple pair of adders to generate partial sum and carry by considering carry input Cin=0 and Cin=1, after that the final sum and carry are selected by the mux [1].The carry out bit of the preceding block of the adders acts as the select signal to the mux. Several examples of such adders have been published and there are many efficient implementations.

II. LITERATURE SURVEY As we know adders are of fundamental importance in a wide variety of digital systems, several types of fast adders exist but adding fast using low area and power is still challenging. In digital adders, the speed of addition is limited by the time required to propagate a carry through adder. So the CSLA is used in many computational systems to alleviate the problem of carry propagation delay. So many papers were published on this with several examples of such adders and many efficient implementations were also done.

In 1962, O.J.Bedrij [1] described the extremely fast digital adder with sum selection and multiple-radix carry. He compared the amount of hardware and the logical delay for a 100-bit ripple-carry adder and a carry-select adder. The problem of carry-propagation delay was overcome by independently generating multiple-radix carries and using these carries to select between simultaneously generated sums. In this adder system, the addend and augend were divided into subaddend and subaugend sections that were added twice to produce two sub sums. One addition was done with a carry digit forced into each section, and the other addition combined the operands without the forced carry digit. The selection of the correct sub sum from each of the adder sections depended upon whether or not there actually was a carry into that adder section.

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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 08-11 IMPACT FACTOR 1.719 www.iord.in There are many carry select adder approaches available but most of them use ripple carry adder. T.Y.Chang and M.J.Hsiao [3], suggested that instead of using dual ripple carry adders, a carry select adder scheme using an add one circuit to replace one ripple carry adder requires 29.2% fewer transistors with a speed penalty of 5.9% for bit length n=64. If speed was important for this 64 bit adder, then two of carry-select adder blocks could be substituted by the proposed scheme with a 6.3% area saving and the same speed.

The Youngjoon kim and Lee-Sup Kim [4] suggested that a carry-select adder could be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders. They proposed a new add-one circuit using the first zero finding circuit and multiplexers to reduce the area and power with no speed penalty. For n=64 bit, this new carry-select adder requires 38% fewer transistors than the dual ripple-carry carryselect adder and 29 percent fewer transistors than Chang's carry-select adder using single ripple carry adder. This new 64b adder using a 0.25 um CMOS technology had 3.45 ns delay time at 2.5 V power supply. Behnam Amelifard et.al [6], suggested a new adder called carry select adder with sharing (CSAS) which was area efficient but the delay was more. M.Alioto et.al [5], suggested using variable size block sizing depending on the multiplexers delay.

The B.Ramkumar, H.M.Kittur, and P. M. Kannan [7] suggested a very simple approach to improve the speed of addition. Based on this approach a 16, 32 and 64-bit adder architecture was developed and compared with conventional fast adder architectures. In many parallel multipliers to speed up the final addition, CLA was arranged in the form of Carry Select adder (CSLA) & was used. But due to the structure of the CSLA it occupied more chip area, because it uses multiple pairs of RCA’s to generate the partial sum and carry by considering Cin=0 and Cin=1.Thus the complexity of the final adder structure was high. So they replaced the RCA (CLA) with Cin=1 with BEC logic, which reduced the maximum area and delay in the final adder structure.

III.

CONVENTIONAL ADDER CIRCUITS

Fig.1 shows the internal logic schematic of a carry select adder constructed using the conventional ripple carry adder (RCA). The RCA uses multiple full adders to perform addition operation. Each full adder have a carryin input, which is the carry-out of the preceding adder. The CSA divides the words into blocks which is to be added and forms two sums for each block in parallel, one with assumed carry in Cin=0 and the other with Cin=1. As shown in Fig. 1, the carry-out from one stage of RCA is used as the select signal for the multiplexer. This selects the corresponding sum bit from the next block of data. This speeds-up the computation process of the adder. Thus, the carry select adder achieves higher speed of operation at the cost of increased number of devices used in the circuit.

This in turn increases the area and power consumed by the circuits of this type of structure.

A[15:11] B[15:11]

A[10:7]

15:11 RCA 15:11 RCA1

A[6:4] B[6:4]

10:7Cin RCA

0

10:7 RCA 1

1

2

B[10:7]

10 CY MUX 12:6

6:4 RCA

1

5 Cout

SUM[15:11]

1

CY MUX 10:5 4 SUM[10:7]

3:2 RCA

1

A[1:0]

1

CY MUX 8:4

Cin

1 2

4 C3[10]

B[1:0]

1:0 RCA

0

2 6

C6[13]

B[3:2]

3:2 RCA

0

2 8

C10[16]

6:4 RCA

0

2

A[3:2]

CY MUX 6:3

3

2

SUM[6:4]

SUM[3:2]

2 C1[7]

SUM[1:0]

Fig.1.Conventional 16-Bit Carry Select Adder

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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 08-11 IMPACT FACTOR 1.719 www.iord.in

A[15:11] B[15:11]

A[10:7]

15:11 RCA 6 bit BEC1

10:7Cin RCA

0

5 bit BEC 1

1

2

B[10:7]

A[6:4]

CY MUX 12:6

4 bit BEC 1

1

5 Cout

SUM[15:11]

3 bit BEC

1

C6[13]

A[1:0]

1

CY MUX 8:4

4 SUM[10:7]

B[1:0]

1:0 RCA

0

2 4

C3[10]

Cin

1

2 6

CY MUX 10:5

B[3:2]

3:2 RCA

0

2 8

C10[16]

A[3:2]

6:4 RCA

0

2 10

B[6:4]

CY MUX 6:3

3

2

SUM[6:4]

SUM[3:2]

2 C1[7]

SUM[1:0]

Fig.2.Modified 16-Bit Carry Select Adder

IV.

PROPOSED CSLA ARCHITECTURE

In 2012, B.Ramkumar and H.M.Kittur [8] suggested a very simple approach to reduce the area and power of SQRT CSLA architecture. The basic idea of this work was to use Binary to Excess-1 Converter (BEC) instead of RCA with Cin=1 in the regular CSLA to achieve lower area and power consumption. Fig.2 shows the proposed design of modified CSLA architecture. The number of gates of this work was reduced which offered the great advantage in the reduction of area and also the total power. The compared results shown that the modified SQRT CSLA has a slightly larger delay (only 3.76%), but the area and power of the 64-b modified SQRT CSLA were significantly reduced by 17.4% and 15.4% respectively. The power-delay product and also the area-delay product of the proposed design had shown a decrease for 16, 32, and 64-bit sizes which indicated the success of the method and not a mere tradeoff of delay for power and area. This proposed design had reduced area and power as compared with regular SQRT CSLA with only a slight increased in the delay.

V.

CONCLUSION

In this paper, various types of Carry select adder design have been reviewed from the most recent and previous published research work. Various different logics are used in this paper to build the carry select adder to reduce the power, delay, area and power-delay product and transistors count. Based on survey it is conclude that the modified CSLA with BEC-1 have consume less power and area with slightly increase in the delay, the power delaydelay product and area-delay product have also decrease for 16,32,64-bit sizes which indicated the success of the method and not a mere tradeoff of delay for power and area. This modified CSLA architecture is therefore low power, low area, simple and efficient for VLSI application. It would be interesting to test and obtain the results for the modified 128,256 and 512 bit CSLA. REFERENCES [1] O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron. Comput., pp. 340–344, 1962.

[2] J.Sklansky, “Conditional-Sum Addition Logic,” IRE Trans. Electron. Comput., vol. EC-9, pp.226-231, 1960.

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IORD Journal of Science & Technology E-ISSN: 2348-0831 Volume 1, Issue V (JULY-AUGUST 2014) PP 08-11 IMPACT FACTOR 1.719 www.iord.in [3] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron. Lett., vol. 34, no. 22, pp. 2101– 2103, Oct. 1998.

[4] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,” Electron. Lett., vol. 37, no. 10, pp. 614–615, May 2001.

[5] M.Alioto et.al, “A Gate Level Strategy To Design Carry Select Adders,” ISCAS 2004.

[6] Behnam Amelifard et.al “Closing the Gap between Carry Select Adder and Ripple Carry Adder,” Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05), 2005.

[7] B. Ramkumar, H.M. Kittur, and P. M. Kannan, “ASIC Implementation Of Modified Faster Carry Save Adder,” Eur. J. Sci. Res., vol. 42, no. 1, pp. 53–58, 2010.

[8] B. Ramkumar and H.M. Kittur, “Low Power and Area Efficient Carry select Adder” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume: 20, Issue: 2, 2012.

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