N0289195

IOSR Journal of Engineering (IOSRJEN) ISSN: 2250-3021 Volume 2, Issue 8 (August 2012), PP 91-95 www.iosrjen.org

A New Technique to Decrease Leakage Power in VLSI Circuits K.Sridhar1, L.Narayana Rao2, Santosh Amshala3, Mohd Saleem Uddin4 Abstract: - Motivated by emerging battery-operated application on one hand and shrinking technology of deep sub micron (DSM) regime on the other hand, leakage power dissipation is rapidly playing a significant role in the total power dissipation as threshold voltage becomes small. The Low-power design techniques for leakage power minimization are investigated and presented in this paper and then propose a novel method, named ‘‘Multi purpose technique”. This method is based on reducing leakage power in active mode with the least delay and the off-state leakage mechanism while saving exact logic state. Library designed using 65nm BSIM4 model of Berkeley Predictive Technology Model (BPTM) has been used to simulate proposed technique compared to investigate techniques.

Key Words: - Multipurpose, DSM, ITRS, 65nm.

I.

INTRODUCTION

Rapid growth in semiconductor technology has led to shrinking of feature sizes of transistors using deep submicron (DSM) process. As MOS transistors enter deep submicron sizes, undesirable consequences regarding power consumption arise. Until recently, dynamic or switching power component dominated the total power dissipated by an IC. Voltage scaling is perhaps the most effective method to decrease dynamic power due to the square law dependency of digital circuit active power on the supply voltage.

As a result, this demands a reduction of threshold voltage to maintain performance. Low threshold voltage results in an exponential increase in the sub-threshold leakage current. On the other hand as technology scales down, shorter channel lengths result in increased sub-threshold leakage current through an off transistor.

Therefore, in DSM process static or leakage power becomes a considerable proportion of the total power dissipation. For these reasons, static power consumption, i.e. leakage power dissipation, has become a significant portion of total power consumption for current and future silicon technologies.

II. SUB-THRESHOLD LEAKAGE CURRENT Sub-threshold or weak inversion conduction current between source and drain in an MOS transistor occurs when gate voltage is below VTH .The sub-threshold leakage is modeled as Equation (1):

μ denotes carrier mobility ,Cox is the gate oxide capacitance per unit area, W and L denote the width and effective length of the transistor, K is the Boltzmann constant, T is the absolute temperature, and q is the electrical charge of an electron. In addition, VTH is the zero biased threshold voltage, _ is body effect coefficient, _ denotes the drain-induced barrier lowering (DIBL) coefficient, n is the slope shape factor subthreshold swing coefficient. [1]

III. PREVIOUS WORK There are several different approaches tackling leakage. Each technique provides an efficient way to reduce leakage power, but disadvantages of each technique limit the application of each technique. Previously proposed work can be divided into following techniques: (1) state-saving techniques: where circuit state (present value) is retained.

(2) state-destructive techniques: where the current Boolean output value of the circuit might be lost.

MTCMOS power gating is a well-known way to reduce leakage and it continues to be applied to verydeep submicron CMOS technologies. This can be done by using one PMOS transistor and one NMOS transistor in series with the transistors of each logic block to create a virtual ground and a virtual power supply as depicted in Fig.1(a). Notice that in practice only one transistor is necessary, because of their lower on-resistance, NMOS transistors are usually used.

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A New Technique to Decrease Leakage Power in VLSI Circuits All the logic transistors contain low V TH transistors to achieve the fastest switching speeds in the active mode, while the sleep transistors are built using high VTH transistors to minimize the leakage during the standby mode. The sleep transistor is controlled by a sleep signal used for active/standby mode control (sleep=0/1 during standby and active modes respectively). During active mode the switch control (S) signal is high and both high VTH transistors are turned on .Consequently, the low V TH logic gates operate normally and at high speed. On the other hand, in the standby mode, switch control (S) signal goes to low, and high VTH transistors are turned off at the same time. In this state, the leakage current reduces by using high VTH transistors. However, this technique results in destruction of state plus a floating output voltage because of circuit state floating after sleep mode [5][6] .

Fig. 1: Tackling leakage techniques (a: MTCMOS- b: SCCMOS -c: Forced Stack) Another technique, which is similar to MTCMOS power gating, is Super Cutoff CMOS (SCCMOS).

As seen from (1), the sub-threshold leakage is dependent on the VGS. According to Fig.1(b) by using slight negative voltage gate, the sub-threshold current reduces exponentially The key difference with MTCMOS is that the sleep transistors have the same low threshold voltage.

Because of using low VTH sleep transistors the additional delay caused by high VTH sleep transistors can be reduced during active mode. Although this scheme can improve the performance of the circuit, like MTCMOS, it can't save the circuit logic state during standby mode, so the technique results in destruction of circuit logic state [7].

Another approach used for leakage power reduction in active mode is the stack technique which has shown in fig.1( c). Narendra et al. studied the effectiveness of the stack effect.

Stack effect or Self-Reverse bias effect is the phenomenon where leakage current decreases due to two or more series transistors that are turned off .Equation 1 shows dependence of the sub-threshold current to the voltages of all the four terminals. Transistor stacking technique exploits the dependence of ISUB on the source terminal voltage.

According to (1) with the increase of the Vs of the transistor, transistor, the sub-threshold leakage current reduces exponentially. This would happen due to the following reasons:  The Gate-to-Source voltage ( VGS ) would reduce and if the input applied is grounded, it would turn negative .This would reduce SUB I exponentially Threshold voltage increases due to body effect.  The DIBL coefficient decreases due to lower drain to source potential thereby further reducing leakage.

However, the forced stack technique cannot save power consumption in standby mode [8]-[9]-[10].

IV. MULTI- PURPOSE TECHNIQUE This technique has a combined structure of the following techniques.  MTCMOS technique  SCCMOS technique  Forced stack technique Unlike the MTCMOS and SCCMOS technique, This technique can reduce power consumption during active mode and retain the exact logic state and unlike the forced stack technique, it technique can save power consumption during standby mode. Fig. 2 shows multi purpose scheme.

The sleep transistors of the circuit operate similar to the sleep transistors used in the MTCMOS technique in which sleep transistors are turned on during active mode and turned off during sleep mode.

During active mode in Fig.(a), S = 0 and S_ = 1 are asserted, and thus all sleep transistors and transistors in parallel to the sleep transistors are turned on. This structure can potentially reduce circuit delay .On the other side stack structure reduces leakage power during active mode asserted, and thus all sleep transistors are turned off.

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A New Technique to Decrease Leakage Power in VLSI Circuits

Fig. 2: Multi purpose technique (a:Active mode- b:Standby mode) pull-up network. Similarly, to maintain a value of „0â€&#x; in standby mode, transmission gate in parallel to the NMOS sleep transistors is the only source of GND to the pull-down network

V. SIMULATION RESULT Simulations have been performed using HSPICE in 65 nanometer (nm) standard CMOS technology at room temperature; with supply voltage 0.7v to estimate power consumption.

We use the BSIM4 model of Berkeley Predictive Technology Model (BPTM) parameters for the technologies 65 nanometer (nm) standard CMOS technology [11]-[12]-[13].

1-bit full adder (Fig.3) and NAND circuit are chosen to compare our technique to the other techniques: MTCMOS, SCCMOS and Forced stack. Dynamic power is measured with a random input vector changing every clock cycle.

Fig. 3: Resulting waveform of 1 bit full adder The resulting waveforms,Va,Vb,Vc according to Fig.4 are asserted cyclically for 500ns and the average power dissipated measured by HSPICE during this period recorded as dynamic power .We measure sub-threshold current by varying V(a) and V(b) to sub-threshold voltage from 0 to 0.18 volt and V(c)=0.7v as dc source. In this condition average current has been measured during 0 to 500ns.

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A New Technique to Decrease Leakage Power in VLSI Circuits Tables _ are shown the result of simulation for full adder and NAND cases respectively .Also Fig.3 shows the output of the circuit according to HSPICE.

According to simulation result in this method there is a 1333-time, 1466-time and 2-time decrease compared to MTCMOS, SCCMOS and Stack respectively during active mode, and a 5- time _ 11.36-time decrease compared to MTCMOS and SCCMOS during standby mode, But because of adding additional transistors to circuit dynamic power has increased in all approaches .The above-mentioned points can be seen in the following charts in fig.4.

VI. CONCLUSION There are various points that must be taken in to account low-power design which include the style of logic, the technology used, the logic implemented and trade off. After analyzing various leakage reduction techniques, it can be concluded that there is a strong correlation between the three performance metrics: leakage power, dynamic power and propagation delay.

In this paper, it presented an effective technique to low leakage power VLSI design. The proposed approach focuses on reducing sub-threshold current during active and standby mode of circuit unlike MTCMOS which can reduce its during standby mode and unlike forced stack which can reduce its during active mode.

Fig. 4: Resulting charts

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A New Technique to Decrease Leakage Power in VLSI Circuits .On the other hand this technique can retain the exact logic state in sleep mode. With application of dual VTH , multi purpose technique is the most efficient approach to reduce leakage current but ,this technique has some area and dynamic power consumption penalty. However it is necessary to trade off between leakage power, dynamic power and propagation delay. For our future work, we plan to investigate why the multi purpose technique increases dynamic Power consumption over the other approaches.

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International Technology Roadmap for Semiconductors, 2007.

T.SAKURAI ,Perspective of Low Power VLSI_s,IEICE Transaction, vol.E87.no.4,pp.429-436, April 2004.

Borisav Jovanovic, Milunka Damnjanovic, Proceeding. 54th ETRAN Conference, , June 7-10, 2010 Donji Milanovac Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande , Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits, International journal of computer application,vol.7,no.5,pp.1-4,septamber 2010.

Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., and Yamada, J. 1-V, Power Supply High-Speed Digital Circuit Technology with Multi-threshold-Voltage CMOS, IEEE Journal of Solid-State Circuits, vol.30, no.8, pp.847-854, August 1995.

Kao, J. T., and Chandrakasan, A. P. “Dual-Threshold Voltage Techniques for Low-power Digital Circuits,” IEEE Journal of SolidState Circuits, vol.35, no.7, pp.1009-1018,July 2000.

Kawaguchi, H., Nose, K., and Sakurai, T. “ A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Pico ampere Stand-By Current,” IEEE Journal of Solid State Circuits vol.35,n.10 pp.1498-1501, October 2000.

Park, J. C., and Mooney III, V. J. “Sleepy Stack Leakage Reduction.Very Large Scale Integration (VLSI) Systems,” IEEE Transactions ,vol.14,no.11, pp.1250-1263, November 2006.

B.S. Deepaksubramanyan and Adrian Nu˜nez EECS Department,Syracuse University , Analysis of Subthreshold Leakage Reduction inCMOS Digital Circuits, Proceeding of the 13TH NASA VLSISymposium Post Fall, IDAHO, USA, June 2007.

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1.

K Sridhar is doing his Ph.D. research in area of Image Processing and he completed his B.Tech ECE from Vijay Rural Engineering & Technology, M.Tech from Mahaveer Institute Of Science And Technology,,Hyderabad. Currently he working as Asst Prof at JNTUH affiliated college, having 6 years of experience in Academic has guided many students. His research areas include Image Processing, Wireless Networks and Computer Networks.

2.

Narayana Rao Latchupatula B.Tech ECE from Avanthi College of Engineering & Technology, Vishakhapatnam M.Tech VLSI SD from Kshatriya College of Engineering, Armoor Currently he working as Asst Prof at JNTUH affiliated college, having 5 years of experience in Academic has guided many students. His interest areas include Mobile Communication, VLSI, Embedded System, Signal Processing

3.

Santosh Amshala B.Tech ECE from Vijay Rural Engineering & Technology, M.Tech ECE from Vijay Rural Engineering & Technology. Currently he working as Asst Prof at JNTUH affiliated college, having 4 years of experience in Academic has guided many students. His interest areas include Mobile Computing, Embedded System ,VLSI Design.

4. Mohd. Saleem Uddin done B.Tech ECE from Kshatriya College of Engineering, M.Tech ECE from Vijay Rural Engineering & Technology. Currently he working as Asst Prof at JNTUH affiliated college, having 2years of experience in Academic. His interest areas include Mobile Communication, VLSI, Embedded System, Signal Processing.

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