International Journal of Scientific Engineering and Technology Vo lu me No.3 Issue No.4, pp : 408-410
(ISSN : 2277-1581) 1April 2014
New Approach to Reduce Energy Consumption in Six Transistors SRAM Bilal Ahme d Ansari1 , Alok Kumar2 1 M.E. Student, SSCET, Bhilai, C.G., India 2 Assistant profesor, SSCET, Bhilai, C.G.,India 1 bilal5100@gmail.com, 2 alok13dec@gmail.com Abstract— This paper presents the technique used to reduce the power dissipation in 6T SRAM. Normally there is a power loss in charging and discharging the bit line during reading and writing. This power loss is drastically reduced with the use of additional adiabatic circuit. Simulation of the circuit is done using HSPICE in 65nm technology. This circuit also preserve power during writing phase also. Keywords— SRAM, power dissipation, stability, low power. I.
In tr o du c ti o n
The low cost consumer electronic devices (cell phone with camera, notepad, hand held low cost computing devices etc.) we enjoy today is the direct impact of much phenomenal development of the VLSI technology. As in late 1970s Moore stated a law that in every eighteen month the number of transistor in the chip becomes double. Therefore, to meet the requirement of the portable appliances various low power techniques had been used [I]. Low power design plays a significant role in high performance IC leads to circuit designs with high clock frequencies. Due to the increase in clock frequency, there is a proportional increase in power dissipation. Moreover, for most portable systems, the IC (Integrated Circu it) co mponents consume a significant portion of the total system power [II]. The dynamic power consumption equation [III]: PDynamic = f.Cinterconnect.V2 dd Where, f is the frequency of operation Cinterconnect is the interconnect capacitance Vdd is the supply voltage. Clearly it can be seen that for every VLSI circuit there is dynamic power dissipation due to the operating frequency, operating voltage and the interconnected capacitance. In static random access memory (SRAM) also there is dynamic power d issipation, which can be reduced by using several technique. In [IV] it is found that about 70% of the total power is lost while reading and writing into the cell. In six transistors SRAM there are double ended reading is done through two bitlines. The two bitlines are used to obtain the stability in read ing and to obtain high signal to noise ratio. In 1995 D. So meshekar et.al. [V] Says that there is about 85% of the power reduction is obtain by using adiabatic principle. They do not use the extra precharge circuitry. But now there is a scope of improvement in SRAM with respect to energy saving. Tzart zanis et.al [VI] proposed a new energy recovery latch based with two phase resonant clock driver. It is claimed that the energy-recovery SRAM energy recovery resulted in
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significant energy savings (e.g. 59% to 76%) for the different 0.5μm SRAM parts at 200 M Hz. In [VII] J.Kim et.al uses a dummy bit line capacitance with a constant load for each pair of bit lines in order to provide a constant load to the charging source during all the operation cycles including hold cycles. They found that 53% of power is saved as compared to conventional SRAM at 400MHz and 2.5V during write cycle. Shunji Nakata [VIII] connects the high resistive switch in between SRA and VDD and in between SRAM and ground. This arrangement gives the energy s aving during writ ing operation. The switches are operated in such a manner that while writing, the power supply voltage to the SRAM is gradually changed fro m ground level to VDD level II. Co nv ent ion al 6 T S RA M In t his s ectio n t he b rie f r e vision o n t he co nv e ntion al 6 T S R A M i s fo cu se d. As it se e n th at th e o p er ation o f S R A M is di vid ed into thr ee m od es t h at is h old m o d e, w rite m od e a nd r e ad m od e. Th e fig 1 s ho w s th e cir c uit di ag r a m f or 6 T S R A M . Th e re is t w o cr oss co u ple d in v ert er c on n e cte d b ac k t o ba c k e a ch oth e r . T h e in v ert er is m a d e up of t w o tr ansist ors M P 1 a nd M N 1 . Si mil arly a n oth er inv ert er is m a d e by th e c o m bin ation of N M O S M N 2 a nd P M O S M P 2. T h e out put of o ne in ve rte r i s c on n e cte d to t h e in put of oth e r inv ert er. T h er e ar e t w o a c c ess tra nsisto rs A N 1 an d A N 2 b oth ar e N M O S t yp e. Th e so ur c e t er mi n als o f both th e in v ert er a r e co n n ect ed to t he o utp ut o f e a ch inv e rte r. T h e dr ain t er mi n al is co n n ect ed to t he bitline an d c o mpli m ent of th e bitlin e. T h e g ate ter min al of th e a c ce ss tr an sistor is c o nn e cte d t o a sig n al call ed a s w o rd lin e ( WL ) . T h e w o rd line will d e cid e w h et he r th e S R A M is in h old m o d e or in r e ad/ w rite mo d e. If th e WL i s lo w th e S R A M c ell is dis co nn e ct ed fr o m b oth t h e bitline s, h en c e t he d at a pr es ent in th e c ell will b e in t h e h old stat e. Wh e n th e WL is hig h t he n t he SR A M eith e r pe rf or m r e a ding o p er atio n o r w riting o p er ation . T h e w rite driv e r cir cuit de ci de w h eth er to re a d fr o m th e SR A M o r to writ e dat a int o th e S R A M . Wh e n t he WE ( w rite en a ble ) si gn al is high th e n th e d ata w ill b e w rite i nto t he S R A M c ell. Oth e r wis e re a din g is do n e th ro u gh r e ad a m plifie r.
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International Journal of Scientific Engineering and Technology Vo lu me No.3 Issue No.4, pp : 408-410
(ISSN : 2277-1581) 1April 2014
Fig. 1- conventional 6T SRAM with write driver and read amplifier circu it. The read stability of the cell is obtained by making the transistor MN1 and MN2 greater than the access transistor AN1 and AN2. As it is known that the for reading the data present at the node ‘Q’ will switch if the NMOS transistor is not greater than the access transistor. The width of the pull up transistor is made smaller as compared to the access transistor and the pull down transistor. The simulation waveform of the conventional 6T SRAM cell is shown in Fig. 2. The waveform is simulated in HSPICE using Predictive Technology model [IX] in 65n m technology. The waveform shows the writing and reading operation. The voltage used for operating is 1.0V.
Fig. 3- Ad iabatic d river circu it with read amp lifier in 6T SRAM The driver circu it consists of an N and a P MOSFET connected to the capacitance load. When the input signal says ‘IN’ is low, the capacitance charges to the peak value of the power clock voltage ‘Vpc’. When the input signal is high, the charges stored in the capacitance are pumped back to the signal generator. As we use adiabatic technique there is very less loss of energy. In order to make use of the driver to save energy in bit line, one driver is needed for one bit line. The energy saved is proportional to: E = ½.CBL.V2 Where ‘CBL’ = b it line capacitance and ‘V’ = b it line vo ltage The simulat ion waveform of the proposed circuit is shown in Fig. 4. The simulat ion is done in 65n m technology and size of the each transistor is kept in mind to obtain less power dissipation.
Fig. 2- waveform during write, read and hold operation of conventional 6T SRAM The energy consumed in the conventional SRAM is 96e-12 joule. The larger amount of energy is dissipated during writing is about 60% of the total energy dissipated. This energy consumption is reduced by adiabatic technique.
III. Proposed Techni que-Ad ia b at ic 6 T S R AM It is s ee n th at th er e is mo r e po w e r c o ns u m ption in writin g the op e r ation in co n ve ntio n al 6T SR A M c ell, h e n ce a n e w pr o po s ed te ch niq u e is use d to r ed u c e the e n er gy c o nsu m pti on du rin g the w ritin g op e r ation . Th e p ro p os ed cir c uit f or th e a dia b atic 6 T SR A M is sh o w n b elo w in Fi g. 3. Fig. 4- waveform during write, read and hold operation of proposed 6T SRAM
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International Journal of Scientific Engineering and Technology Vo lu me No.3 Issue No.4, pp : 408-410
(ISSN : 2277-1581) 1April 2014
VI. Ackn o wled g em ent IV. Res u lts H e r e th e p er fo r m a n ce of b oth th e typ e o f SR A M is co m p a r ed wit h th e h el p of g r ap h sh o w n b elo w . 100
My thanks to the Mr. Alok Kumar for his guidance and v aluable support.
References
80 60 Total energy (pJ)
40 20 0 Type 1
Type 2
Ty p e 1= C o nv e ntio n al 6 T S R A M T yp e 2 = A di a b atic 6 T S R A M V e rtic al Col u m n sho w s the total e n er gy c on su m ptio n a nd h ori zo nt al axis r ep r es e nt th e typ e of SR A M us ed . It is cl e arly s e en f ro m th e g ra p h that th e e n er gy dissi p ation in c on v e ntion al SR A M is a bo ut 96 .0 6 pJ a nd th e en e r gy c ons u m ptio n in Adi a b atic S R A M is 48 .5 4 pJ . It is se e n that a bo ut 50 .5 4 % of en e rg y is s av e d du rin g writin g op e r atio n in SR A M c ell. V. Con clusion Wit h an inte nsio n of ar rivi ng at a en e rg y ef fi cie nt S R A M , e ff ort h as be e n put to desi g n an 6 T SR A M c ell with on e bit lin e for re a d an d o n e bit line for write alo n g with du al w or d line s. A sim pl e en e rg y r ec o v er y dri ve r alo n g wit h a lar ge r a c c ess tra nsisto r c o nn e ct ed to the writ e bit lin e hel ps in e n h an ci ng the w rite a bility, in ad ditio n to savi ng e n er g y d uri ng writin g. R e ad sta bility h as be e n i mp ro v e d by si zin g th e pull d o w n tr ansist or c on n e cte d t o t h e sin gl e e nd e d r e ad a m plifie r.
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I. A. P. Chandrakasan and R. W. Brodersen, Low-Power CMOS Design. Piscataway, NJ: IEEE Press, 1998. II. J. Rabaey and M. Pedram, Low Power Design Methodologies. Norwell, MA: Kluwer Academic Publishers, 1996, pp. 21-24. III. J. Rabaey, A. Chandrakasan, and B. Nicolic, Digital Integrated Circuits A Design Perspective, 2nd ed. Prentice Hall, 2003 IV. L. Villa, M. Zhang, and K. Asanovic.2000. of International Symposium on Microarchitecture, Dynamic zero compression for cache energy reduction, proceedings 2000, pp. 214–220. V. D. Somasekhar, Yibin Ye, Kaushik Roy, “An Energy Recovery Static RAM Memory Core, In Proc. 1995 Symposium on Low Power Electronics”, San Jose, CA, October 9-1, 1995 VI. Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou “Energy Recovering Static Memory” In Proc. ISLPED’02, Monterey, California, USA, August 12–14, 2002 VII. J. Kim, C.H.Ziesler, “ Fixed-Load Energy Recovery Memory for Low Power”, In Proc.International Symposium on Very Large Scale Integration. Systems, pp. 145. 6.,2004 VIII. Shunji Nakata in “Recent Patents on Electrical Engineering,2009,Vol.2,No.1 IX. PTM models taken from http://ptm.asu.edu/
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