International Journal of Scientific Engineering and Technology Vo lu me No.3 Issue No.4, pp : 408-410
(ISSN : 2277-1581) 1April 2014
New Approach to Reduce Energy Consumption in Six Transistors SRAM Bilal Ahme d Ansari1 , Alok Kumar2 1 M.E. Student, SSCET, Bhilai, C.G., India 2 Assistant profesor, SSCET, Bhilai, C.G.,India 1 bilal5100@gmail.com, 2 alok13dec@gmail.com Abstract— This paper presents the technique used to reduce the power dissipation in 6T SRAM. Normally there is a power loss in charging and discharging the bit line during reading and writing. This power loss is drastically reduced with the use of additional adiabatic circuit. Simulation of the circuit is done using HSPICE in 65nm technology. This circuit also preserve power during writing phase also. Keywords— SRAM, power dissipation, stability, low power. I.
In tr o du c ti o n
The low cost consumer electronic devices (cell phone with camera, notepad, hand held low cost computing devices etc.) we enjoy today is the direct impact of much phenomenal development of the VLSI technology. As in late 1970s Moore stated a law that in every eighteen month the number of transistor in the chip becomes double. Therefore, to meet the requirement of the portable appliances various low power techniques had been used [I]. Low power design plays a significant role in high performance IC leads to circuit designs with high clock frequencies. Due to the increase in clock frequency, there is a proportional increase in power dissipation. Moreover, for most portable systems, the IC (Integrated Circu it) co mponents consume a significant portion of the total system power [II]. The dynamic power consumption equation [III]: PDynamic = f.Cinterconnect.V2 dd Where, f is the frequency of operation Cinterconnect is the interconnect capacitance Vdd is the supply voltage. Clearly it can be seen that for every VLSI circuit there is dynamic power dissipation due to the operating frequency, operating voltage and the interconnected capacitance. In static random access memory (SRAM) also there is dynamic power d issipation, which can be reduced by using several technique. In [IV] it is found that about 70% of the total power is lost while reading and writing into the cell. In six transistors SRAM there are double ended reading is done through two bitlines. The two bitlines are used to obtain the stability in read ing and to obtain high signal to noise ratio. In 1995 D. So meshekar et.al. [V] Says that there is about 85% of the power reduction is obtain by using adiabatic principle. They do not use the extra precharge circuitry. But now there is a scope of improvement in SRAM with respect to energy saving. Tzart zanis et.al [VI] proposed a new energy recovery latch based with two phase resonant clock driver. It is claimed that the energy-recovery SRAM energy recovery resulted in
IJSET@2014
significant energy savings (e.g. 59% to 76%) for the different 0.5μm SRAM parts at 200 M Hz. In [VII] J.Kim et.al uses a dummy bit line capacitance with a constant load for each pair of bit lines in order to provide a constant load to the charging source during all the operation cycles including hold cycles. They found that 53% of power is saved as compared to conventional SRAM at 400MHz and 2.5V during write cycle. Shunji Nakata [VIII] connects the high resistive switch in between SRA and VDD and in between SRAM and ground. This arrangement gives the energy s aving during writ ing operation. The switches are operated in such a manner that while writing, the power supply voltage to the SRAM is gradually changed fro m ground level to VDD level II. Co nv ent ion al 6 T S RA M In t his s ectio n t he b rie f r e vision o n t he co nv e ntion al 6 T S R A M i s fo cu se d. As it se e n th at th e o p er ation o f S R A M is di vid ed into thr ee m od es t h at is h old m o d e, w rite m od e a nd r e ad m od e. Th e fig 1 s ho w s th e cir c uit di ag r a m f or 6 T S R A M . Th e re is t w o cr oss co u ple d in v ert er c on n e cte d b ac k t o ba c k e a ch oth e r . T h e in v ert er is m a d e up of t w o tr ansist ors M P 1 a nd M N 1 . Si mil arly a n oth er inv ert er is m a d e by th e c o m bin ation of N M O S M N 2 a nd P M O S M P 2. T h e out put of o ne in ve rte r i s c on n e cte d to t h e in put of oth e r inv ert er. T h er e ar e t w o a c c ess tra nsisto rs A N 1 an d A N 2 b oth ar e N M O S t yp e. Th e so ur c e t er mi n als o f both th e in v ert er a r e co n n ect ed to t he o utp ut o f e a ch inv e rte r. T h e dr ain t er mi n al is co n n ect ed to t he bitline an d c o mpli m ent of th e bitlin e. T h e g ate ter min al of th e a c ce ss tr an sistor is c o nn e cte d t o a sig n al call ed a s w o rd lin e ( WL ) . T h e w o rd line will d e cid e w h et he r th e S R A M is in h old m o d e or in r e ad/ w rite mo d e. If th e WL i s lo w th e S R A M c ell is dis co nn e ct ed fr o m b oth t h e bitline s, h en c e t he d at a pr es ent in th e c ell will b e in t h e h old stat e. Wh e n th e WL is hig h t he n t he SR A M eith e r pe rf or m r e a ding o p er atio n o r w riting o p er ation . T h e w rite driv e r cir cuit de ci de w h eth er to re a d fr o m th e SR A M o r to writ e dat a int o th e S R A M . Wh e n t he WE ( w rite en a ble ) si gn al is high th e n th e d ata w ill b e w rite i nto t he S R A M c ell. Oth e r wis e re a din g is do n e th ro u gh r e ad a m plifie r.
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