12.IJAEST-Vol-No-6-Issue-No-1-Implementation-of-Partial-Reconfigurable-FIR-Filters-using-Dynamic-Par by ISERP ISERP

S.karthik et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 065 - 069

Implementation of Partial Reconfigurable FIR Filters using Dynamic Partial Reconfiguration

SENSE Department, VIT University, Vellore, INDIA. skarthik@vit.ac.in

SENSE Department, VIT University, Vellore, INDIA. prudhvisairangisetti@gmail.com This paper presents a partially reconfigurable FIR filter design that targets to meet all the objectives (low-power consumption, autonomous adaptability/reconfigurability, faulttolerance, etc.) on the FPGA, which are set by dynamic partial reconfiguration (DPR). FPGAs are programmable logic devices that permit the implementation of digital systems. They provide an array of logic cells that can configured to perform a given functionality by means of a configuration bit stream. Many of FPGA systems can only be statically configured. Static reconfiguration means to generates a configuration bit stream starting from an HDL completely configure the device before system execution. If a new reconfiguration is required, it is necessary to stop system execution and reconfigure the device it over again. Some FPGAs allow performing partial reconfiguration, where a reduced bit stream reconfigures only a given subset steps of internal components. DPR allows the part of device be modified while the rest of the device (or system) continues to operate and unaffected by the reprogramming [2].

Abstract— This paper intends to describe the development of a dynamically reconfigurable system which supports multiple modules running concurrently, all with hardware support. A standard Xilinx FPGA is used to test the possibilities of loading partially new hardware configurations while other parts of the FPGA still are active. Its scope is to implement an autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters and flexibility allowing dynamically inserting and/or removing the partial reconfigurable FIR filters with various taps. This reconfigurable FIR filter design method using Xilinx Virtex-5 FPGA shows the configuration time improvement and flexibility by using the dynamic partial reconfiguration.

Prudhvi sai R, Spurthy S,

S.karthik (Asst prof), Jean shilpa (Asst prof),

Keywords— Reconfigurable FIR filter; Xilinx FPGA; Dynamic Partial reconfiguration.

I. INTRODUCTION FIR filters are employed in the majority digital signal processing (DSP) based electronic systems. The emergence of demanding applications (i.e., software defined radio, image, audio/video signal processing, coding, smart device to be healthcare systems and sensor filtering, etc.) in terms of power, speed, performance, system compatibility and reusability make it imperative to design the reconfigurable architectures. Recently, explosive proliferation in wired and wireless communication standards renders traditional FIR architectures less suitable for future communication needs. On the other hand, software radio has gained much attention from the researchers worldwide due to a strong demand for reconfigurable communication systems capable of multistandard operations. In light of this trend, programmability and reconfigurability need be taken into account in filter architecture design.

ISSN: 2230-7818

The FIR filter is a special kind of digital filters and has a wide applicability because it has a good characteristic such as linear phase and stability. However, it may need a large number of coefficients to obtain the desired specification. This results in the large number of area (slice) for FPGA design. Therefore, there are certain disadvantages associated with runtime reconfigurable design of higher order tap FIR filters using conventional FPGA design techniques. One of the major disadvantages is the so called reconfigurable overhead, which is the time spent for reconfiguration. This depends on the reconfigurable device and the method of reconfiguration. Partial reconfiguration can be used in this case since the 14-tap or 16-tap FIR filter have FIR filters are employed in the majority of digital signal so many similarities in there structure. Therefore, partial reconfiguration addresses the reduced reconfiguration overhead, coefficient flexibility and area efficiency for higher order FIR filters. This paper is organized as follows. Background and related work is described in Section II. The modular design and module-based partial reconfiguration are described in Section III. Section IV presents the design method and proposed design of reconfigurable FIR filter. Section V presents the implementation process for partially

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II. BACKGROUND AND RELATED WORK

B. Module based partial reconfiguration Module-based partial reconfiguration method is a special case of modular design. And this method can reconfigure only a given subset of internal components during device is activating. A complete initial bit stream must be generated, and then, partial bit steams are generated for each reconfigurable module. Fig. 1 shows the design flow of module-based partial reconfiguration. Hardwired Bus Macros must be included in design as shown in Fig. 2. These macros guarantee that each time partial reconfiguration is performed routing channels between modules remain unchanged, avoiding contentions inside the FPGA and keeping correct inter module connections. The Module-Based Partial Reconfiguration flow is used for these designs

Reconfigurable logic has established itself as a popular alternative to implement digital signal processing algorithms [1]. Furthermore, a number of articles have been published on using DPR to implement different signal processing algorithms. The capability of reconfiguring a filter at run time is of special interest for applications such as wireless communications and software radio. Hardware realizations of FIR filters can be divided into constant coefficients and multiplier-based implementations. In the latter case, DPR is mainly used to change a filter‟s overall structure, or other filter-wide characteristic. At a higher level, DPR is also used to simply change the level of parallelism of an implementation by changing the number of filter cores in an application‟s critical path. In all these cases, changes are usually initiated from a desire to implement a new filter, based on power or resources considerations, or simply to obtain new functionality. A change in coefficients does not require reconfiguration for this type of filter implementation. Thus, for these cases, DPR has milder constraints in terms of reconfiguration speed and reconfigurable logic partition.

3) Final assembly: In the phase, the team leader assembles and implements the top-level design using each sub modules and generates top-module bit stream.

reconfiguration of reconfigurable FIR filter. Section VI describes results. The conclusion is given in Section VII.

III. MODULE-BASED PARTIAL RECONFIGURATION

Figure 1. Module based partial reconfiguration flow.

A. Modular design The modular design flow allows the designer to split the whole system into modules. For each module, the designer generates a configuration bit stream starting from an HDL description and going through the synthesis, mapping, placement, and routing procedures, independently of other modules. The modular design flow consists of „Modular Design Entry / Synthesis‟ and „Modular Design Implementation‟. „Modular Design Entry and Synthesis‟ step must be done for top-level design and the modules. Top-level design is designed by team leader and consists of „black box‟ for each sub-modules and „wiring‟ for interconnection of each sub-modules. „Modular Design Implementation‟ step comprises mainly of following three phases [5]. 1) Initial budget phase: In this phase, the team leader assigns top-level constraints to the top-level design. Top-level constraint needs to area constraint and bus macro assignment. 2) Active module implementation: In this phase, the team members implement the reconfigurable modules.

Figure 2. Design layout with two reconfigurable modules.

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S.karthik et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 065 - 069

Fig3. N-tap transposed FIR filter.

Figure 4. Block diagram of Partial reconfigurable n-order FIR filter.

It is further broken down depending on if communication is needed between modules. For designs where the modules are completely independent (e.g. no common I/O except clocks) and there is no communication between modules, bus macros are not needed. However, for modules that do communicate with each other, a special bus macro (allows signals to cross over a partial reconfiguration boundary. Without this special consideration, inter module communication would not be feasible as it is impossible to guarantee routing between modules. The bus macro provides a fixed "bus" of inter-design communication. Each time partial reconfiguration is performed, the bus macro is used to establish unchanging routing channels between modules, guaranteeing correct connections.

IV. RECONFIGURABLE FIR FILTER DESIGN

The FIR filter computes an output from a set of input samples, which is multiplied by a set of coefficients. And then the FIR filter adds together to produce the output as shown in Fig 3. Implementation of FIR filters can be undertaken in either hardware or software. A software implementation will require sequential execution of the filter functions. Hardware implementation of FIR filters allows the filter functions to be executed in a parallel manner, which makes improved filter processing speed as fast as possible but is less flexible for changes. Thus, reconfigurable FIR filter offers both the flexibility of computer software, and the ability to construct custom high performance computing circuits. Fig. 4 shows the partial reconfigurable n-order FIR filter, which can implement from n=8 to 20. This FIR filter consists of three PR multiply accumulate (MAC) module and one right-side NIAC module, which is connected by bus macros. And each PR MAC module has three kinds of M\AC structure: 1, 2 and 3 rMAC units, which include the serial-to-parallel register to get coefficient inputs in serial. In our proposed design it has only one reconfiguration module, where we can merge all n-order filters in to that module. There is a fixed logic and also PR (partial reconfiguration) logic where a static and reconfigurable design can be implemented. Fig. 5 shows the block diagram of our proposed design, where different order filters can be implemented in less reconfiguration time.

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Figure 5. Block diagram of our proposed design for Reconfigurable FIR filter.

V. IMPLEMENTATION

A. Hardware Description Language (HDL) design and synthesis Partial reconfiguration requires a hierarchical design approach that must be strictly followed during the HDL coding process. The first step of the PR design flow is to define 3 kinds of HDL design description and then synthesize those HDL descriptions separately. These HDL design descriptions are composed to following three design modules [3]. 1) Top-Level design The top-level module that does not contain any logic only contains I/O instantiations, clock primitives, static module instantiations, partial reconfiguration module instantiations, and signal declarations. In addition, the top-level module must define bus macros. The based design and each PRM must be connected through the bus macro. 2) Base design The static modules contain logic that will remain constant during reconfiguration. This step is same with traditional HDL design method, but the static modules cannot contain any clock or reset-related primitives. In the proposed design, the control manager is implemented by the based design.

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E. Merge The final implementation phase is the merge phase. During the merge phase, a complete design is built from the base design and each PRM. In this step, many partial bit streams for each PRM and initial full bit streams are created to configure the FPGA.

3) PRMs design Similar to the static modules, the partial reconfiguration modules must also not contain global clock signals, but may use those from the top-level module. When designing multiple reconfigurable modules to utilize the same reconfigurable area, the component name and port configuration of each module must match the reconfigurable module instantiation located in the top-level module. The proposed system has only one PRM in which different order filters can be reconfigured.

Figure 7. Test bed for Partial reconfiguration using VIRTEX-5 VI. RESULTS

Figure 6. FGPA device view during Initial budget phase.

B. Set Design Constraints After the HDL design description and synthesis, the next step is to set design constraints. Design constraints include the area group, reconfiguration mode, timing constraint and location constraints. The area group constraint specifies which modules in the top-level module are static and which are reconfigurable. Each module instantiated by the top-level module is assigned to a group. As shown in the Fig6, the reconfiguration mode constraint is also only applied to the reconfigurable group, which specifies that the group is reconfigurable. Location constraints must be set for every pin, clocking primitive, and bus macro in the top-level design. Bus macros are located so that they straddle the boundary between the PR region and the base design. C. Implement Base Design Before the static modules are implemented, the toplevel is translated to ensure that the constraints file has been properly created. The information generated by implementing the base design is used for PRM implementation phase. The base design implementation follows three steps: i.e., translate, map and Place & Route (PAR).

The partial reconfiguration of reconfigurable symmetric transposed FIR filters was implemented on Xilinx Virtex-5 XC5V-LX110t FPGA device using test environment shown in Fig.7. Using plan Ahead tool different configurations can be designed full bit and partial bit files are generated, and configuration bit stream download is operated by Xilinx parallel IV Cable and iMPACT tool. Firstly, the full bit stream is downloaded to initial the device, then, the partial bit streams are downloaded when the FPGA is running, meanwhile, the ledâ&#x20AC;&#x;s light along with the choosed partial bit streams. The full bit stream is 1012KB, while the partial bit stream is 13KB for 18-tap filter and 16KB for 18-tap filter. Since the size of the bit stream is directly proportional to the number of resources being configured, partial reconfiguration utilizes a smaller bit stream than a full bit stream for the FPGA. The direct benefit is less space needed for storing the necessary configurations for operation. As reconfiguration times are highly dependent on the size and organization of the PRRs, an additional benefit is that the reconfiguration time is shorter. TABLE I. SIZE OF EACH PR MODULE BIT FILES

D. Implement PRMs After the base design is implemented, each PRM must be implemented separately and follows base design implementation steps: translate, map, and PAR.

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TABLE II. OCCUPIED SLICE NUMBER OF EACH PR MODULE .

ACKNOWLEDGMENT This implementation was supported by the Xilinx virtex-5 kit under Xilinx University support Program. REFERENCES

Table II shows the occupied slice number of each PRmodule. Each PR module's sub-module has same netlist except the order. Therefore occupied slice number of each PR module is almost same. PR modules are synthesized by using Xilinx ISE 12.1 software.

[1]

[2]

[3]

VI. CONCLUSION

[4]

“Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic,” Daniel Llamocca, Marios Pattichis, and. Alonzo Vera, 20 November 2010(references) “An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform,” Chang-Seok Choi and Hanho Lee Department of Information and Communication Engineering(references) “An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform” Chang-Seok Choi and Hanho Lee Department of Information and Communication Engineering Inha University, Incheon, 402-751, Korea [4] Xilinx Corp., "Development System Reference Guide," www.xiinx.com . (references) Xilinx Corp., "XAPP 290: Two flows for Partial Reconfiguration: Module Based or Difference Based," www.xilinx.com , Sept 2004.,in press. Y. C. Lim and S. R. Parker, "FIR filter design over a discrete powers of two coefficient space," IEEE Trans. on Acoustics, Speech and Signal Processing, Vol.ASSP-3 1, pp. 583-591, June 1983. Xilinx Inc., "Early Access Partial Reconfiguration User Guide," www.xilinx.com. March 2006.,in press. Xilinx Inc., "Xilinx University Program Virtex-5 Pro Development System Hardware Reference Manual," March 2005.,unpublished

Table I shows the size of each PR module. Full bit files has more size than partial bit files, therefore it is easier to download partial bit files which also have less reconfiguration time to reconfigure the modules.

[5]

[6]

[7]

In this paper, we present a reconfigurable FIR filter design using dynamic partial reconfiguration, which has area efficiency, flexibility and configuration time advantage allowing dynamically inserting and/or removing the partial modules. The proposed method produces a reduction in hardware cost and allows performing partial reconfiguration, where a reduced bit-stream reconfigures the reconfiguration module. This proposed design can also be designed by difference based partial reconfiguration flow by identifying only the difference between the different FIR order filters and generating particular partial bit files and can be reconfigured.

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