17.IJAEST-Vol-No-8-Issue-No-1-Design,-Simulation-&-Optimization-of-On-Chip-Amplifier-for-CCD-Array-1 by ISERP ISERP

Dr. Rahul Malhotra* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 8, Issue No. 1, 107 - 112

Design, Simulation & Optimization of On-Chip Amplifier for CCD Array

C. Interline (IL) D. Split Frame Transfer (SFT) Full-Frame (FF) CCDs have the simplest architecture and are the easiest to fabricate and operate. They consist of a parallel CCD shift register, a serial CCD shift register and an signal sensing output amplifier. Images are optically projected onto the parallel array which acts as the image plane. The device takes the scene information and partitions the image into discrete elements which are defined by the number of pixels thus "quantizing" the scene.

Abstract—CCD are used to capture the images modern digital cameras and high resolution cameras consists of CCD array but all the performance of the CCD array is depends on the performance of On-Chip amplifier which is placed at the end of the array. The real world is analog, so the field of Analog VLSI design is an essential part of any electronics system. In this paper low power amplifier is presented for CCD array. Metal-Oxide Semiconductor forms the basis for the charge-coupled device; an understanding of the structure is useful in order to understand CCD operation. Single and Two stage amplifiers are simulated and the result is presented for the power and bandwidth by varying the sizes of the different transistors. All the results are verified by using the Tanner tool. There are number of analysis presented by the researchers in the literature to improve the power dissipation but most of the structure are compromise sometimes with the area or sometimes with the bandwidth here we have achieve the lesser power dissipation but with the value of bandwidth is also maintained to support this claim the detailed results are presented in the result section.

Amit Kumar

Deparment of Electronics & Comm. Engg. Bhai Maha Singh College of Engineering Muktsar , Punjab, India amitkumar_sgnr@yahoo.co.in

Dr. Rahul Malhotra

Deparment of Electronics & Comm. Engg. Bhai Maha Singh College of Engineering Muktsar , Punjab, India blessurahul@gmail.com

Keywords: Gain; power dissipation; bandwidth; capacitance I.

I. INTRODUCTION

Charge Coupled Devices (CCDs) were invented in the 1970s and originally found application as memory devices Charge Coupled Devices (CCD) have many applications, but the most important is in imaging [3]. The basic operation of the sensor is to convert light into electrons. When light is Incident on the active area of the image sensor it interacts with the atoms that make up the silicon crystal. The energy transmitted by the light (photons) is used to enable an electron to escape from the tight control of one atom to roam more freely about the device as a “conduction” electron, leaving behind an atom shy of one electron [11]. Modern CCD has four types of architecture: A. Full-Frame (FF) B. Frame-Transfer (FT)

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Fig. 1 Full Frame architecture The resulting rows of scene information are then shifted in a parallel fashion to the serial register which subsequently shifts the row of information to the output as a serial stream of data. The process repeats until all rows are transferred off chip. The image is then reconstructed as dictated by the system. Because the parallel register is used for both scene detection and readout, a mechanical shutter or synchronized

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Dr. Rahul Malhotra* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 8, Issue No. 1, 107 - 112

Frame-Transfer (FT) CCDs are very much like FF architectures. The difference is that a separate and identical parallel register, called a storage array, is added which is not light sensitive. The idea is to shift a captured scene from the photosensitive, or image array, very quickly to the storage array. Readout off chip from the storage register is then performed as described in the FF device previously while the storage array is integrating the next frame. The advantage of this architecture is that a continuous or shutters less/strobe less operation is achieved resulting in faster frame rates. Because twice the silicon area is required to implement this architecture, FT CCDs have lower resolutions and much higher costs than FF CCDs. The architecture is shown in the fig. 2.

being integrated thus achieving a continuous operation and a higher frame rate. Because of this architecture, the image smear during readout using FT CCDs is significantly improved using IL CCDs.

strobe illumination must be used to preserve scene integrity. The simplicity of the FF design yields CCD imagers with the highest resolution and highest density. The architecture is shown in the fig. 1.

Fig. 3 Interline Architecture

Fig. 2 Frame transfer architecture

Both of the above architecture are widely used but the performance of both the architecture are depends on the type and the quality of the On-chip (output) amplifier which is fabricated at the last stage of the structure as shown in the fig. above. Interline (IL) CCDs are incorporated to address the shortcomings of the FT devices. This is achieved by separating the photo-detecting and readout functions by forming isolated photosensitive regions in between lines of non-sensitive or light shielded parallel readout CCDs. After integrating a scene, the signal collected in every pixel is transferred, all at once, into the light shielded parallel CCD. Transfer to the output is then carried out similar to FF and FT CCDs. During readout, like the FT CCD, the next frame is

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The major disadvantages of IL CCD architectures are their complexity which leads to higher unit costs and lower sensitivity. Lower sensitivity occurs because less photosensitive area (i.e. a reduced aperture) is present at each pixel site due to the associated light shielded readout CCD. Furthermore, quantization (or sampling) errors are greater because of the reduced aperture. Lastly, some IL architectures using photodiodes suffer image "lag" as a consequence of charge transfer from photodiode to CCD. Split Frame Transfer (SFT) device is essentially the same as a frame transfer device, except that the storage section is split in half, with each half being located above and below the imaging section. The advantage of this is that it allows the image to be transferred out of the imaging section in half the time that is required for a frame transfer device. Once charge has been injected into a CCD it propagates along the channel under the control of the clock voltages on the gate electrodes. At some point the charge packet for the associated surface potentials, must be sensed. If the sensing is performed at the end of a CCD delay line, then it can be destructive because the signal charge has in any case to be removed from the CCD channel completely at the end of the device. In a multi-tap situation, however where the charge must be sensed several times during its passage through the CCD, the sensing operation must be non destructive. Another option in sensing techniques is whether a voltage or current output is required from the process. Both these considerations affect the choice of sensing technique and have given rise, consequently, to a variety of sensing circuits [1, 2, 3, 10].

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residing under the P2 gates again. Note that all charge packets move simultaneously one pixel to the right. In addition, the first packet moves to the charge detection amplifier where the number of signal electrons is measured. N such clock cycles are required to readout an entire N-pixel linear register. At all times within a single pixel, a well and a barrier to the next pixel co-exist. These are required in order to store the charge and to maintain the uniqueness and identity of each charge packet. Note that by interchanging the roles of any two of the gates the charge will move to the left. This flexibility is clearly another advantage of the three phase process. The effectiveness with which the transfer process occurs is measured by the Charge Transfer Efficiency (CTE). Typically, charge may be transferred with efficiency greater than 99.999% per pixel [8, 9].

II.

A charge-coupled device consists of a regular array of individual pixels. In fig. 4 illustrates a linear array of pixels, each with three separate gates, referred to as Phase 1, Phase 2, and Phase 3 (P1, P2, and P3). As shown within the linear register, all P1 gates are connected to the same bias or clock line; the same is true for P2 and P3. A single CCD pixel has no means to read out the quantity of charge accumulated beneath the integrating electrode. The process of reading out this signal charge involves moving the packet from the site of collection to a charge detecting amplifier located at the end of the linear array. This is the charge transfer process, which is illustrated in fig. 4.

ARCHITECTURE OF ON-CHIP AMPLIFIER

Output amplifier has also two type of the architectures:

A. Single stage amplifier B. Two stage amplifier

VRD

W=22u L=2u

VRG

FD out

Detection Node W=22u

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W=22u L=2u

Fig. 4 Three phase charge transfer process

Assume that charge is collected beneath the P2 electrodes. At time, t1, we apply a positive bias to the P3 electrode equal to the P2 bias, turning the P3 electrodes “on”. The charge located entirely beneath the P2 electrodes spills to the region beneath P3 due to self-induced drift and diffusion. At t2, the P2 electrodes are turned “off” (i.e., the voltage applied to the P2 gates now equals that on the P1 gates). The charge under P2 now moves rapidly to a position beneath the P3 electrodes. Note that the charge moves from a position under the P2 gates to one under P3 gates. Indeed, the process of moving or coupling the charge from one gate to its immediate neighbor gives rise to the name charge-coupled device. Repeating the process using the P3 and P1 gates results in the charge moving to position under the P1 gates. One more cycle involving the P1 and P2 gates leaves the charge packet

VDD

L=2u

Fig. 5 Single Stage CCD On-Chip amplifier The single stage amplifier consists of source follower M1 and load transistor Mc for biasing. The reset FET is connected to the detection node and consists of floating diffusion [4, 6, 7] and the gate of M1. In the ON state it resets the detection node to a reference voltage (VRD) and in the OFF state the floating can receives the next charge packet. The voltage source

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Dr. Rahul Malhotra* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 8, Issue No. 1, 107 - 112

between the gate and source of the current sink Transistor Mc determines the bias current of the first stage and can be used as a signal injection point to measure the ratio between total capacitance and the effective sense capacitance and the bandwidth in the off state. The Two stage amplifier further improves the character tics of the amplifier and gives the better result which is shown in the result section of the paper and the architecture of two stages is shown two stage amplifier also improves the sensitivity of the amplifier and this also reduces the noise level of the overall CCD.

Transistor „M2‟: -The gain can be maximized by increasing the width of this transistor as this increases the difference in the output voltage amplitude. Transistor „M3‟: -The gain can be maximized by decreasing the width of this transistor as this increases the difference in the output voltage amplitude. To achieve maximum bandwidth: Transistor „M1‟: - The bandwidth of the circuit can be increased by increasing the width of this transistor as the increase in width increases the transconductance which helps in increasing the bandwidth as the impedance decreases.

Transistor „MC‟: - The bandwidth of the circuit can be increased by increasing the width of this transistor as the increase in width increases the transconductance which helps in increasing the bandwidth as the impedance decreases.

Transistor „M2‟: - The bandwidth of the circuit can be increased by increasing the width parameter of this transistor. So bandwidth can be increased by changing this parameter.

Transistor „M3‟: - The bandwidth of the circuit can be increased by increasing the width of this transistor as the increase in width increases the Tran conductance which helps in increasing the bandwidth as the impedance decreases, although the change desired is not that large.

Fig. 6 Two Stage CCD On-Chip amplifier

OPTIMIZATION

III.

For optimization of the on-chip amplifier Length and Width of the individual transistor are varied and the various optimization results are obtained. The effect of increase and decrease of Length and Width of the transistor is given as

To achieve minimum power dissipation: Transistor „M1‟: - The power dissipation of the circuit can be reduced by reducing the width of this transistor as the current flowing into this transistor reduces with the reduction in the width while power dissipation can be reduced by increasing the length because increase in length reduces transconductance which in turn reduces the amount of current flowing into the transistor. Transistor „MC‟: - The power dissipation of the circuit can be reduced by reducing the width of this transistor as the current flowing into this transistor reduces with the reduction in the width while power dissipation can be reduced by increasing the length because increase in length reduces transconductance which in turn reduces the amount of current flowing into the transistor.

To achieve maximum gain: Transistor „M1‟: -The gain can be maximized by increasing the width of this transistor as this increases the difference in the output voltage amplitude.

Transistor „M2‟: - The power dissipation of the circuit can be reduced by reducing the width of this transistor as the current flowing into this transistor reduces with the reduction in the width.

Transistor „MC‟: -The gain can be maximized by decreasing the width of this transistor as this increases the difference in the output voltage amplitude.

Transistor „M3‟: - The power dissipation of the circuit can be reduced by reducing the width of this transistor as the current flowing into this transistor reduces with the reduction in the width.

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Dr. Rahul Malhotra* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 8, Issue No. 1, 107 - 112

IV.

RESULTS

Table 4: When the Length of the transistor M2 varied

Table 1: When the width of the transistor M3 varied Transistor Dimensions (W× L) μm M1

M2 (W× L) μm

M3 (W× L) μm

Power Dissipation (mW)

Bandwidth BM (MHz)

Transistor Dimensions (W× L) μm M1

M2 (W× L) μm

M3 (W× L) μm

Power Dissipa tion (mW)

Bandwidth in (MHz)

15×25

12×10

20x5

10x15

6.5

155

15×25

12×10

20x10

10x15

6.2

495

12×10

20x10

8x25

5.7

285

15×25

12×10

20x10

10x25

5.9

302

15×25

12×10

20x15

10x15

6.0

560

15×25

12×10

20x10

12x25

5.95

320

15×25

12×10

20x18

10x15

5.9

570

15×25

12×10

20x10

14x25

6.0

268

15×25

12×10

20x20

10x15

5.8

334

15×25

12×10

20x10

16x25

6.3

225

15×25

12×10

20x10

18x25

6.55

205

Transistor Dimensions (W× L) μm

M2 (W× L) μm

M3 (W× L) μm

Power Dissipation (mW)

Bandwidth BM (MHz)

15×25

12×10

22x10

10x25

5.4

15×25

12×10

20x10

10x25

5.1

15×25

12×10

18x10

10x25

5.25

15×25

12×10

16x10

10x25

5.2

15×25

12×10

14x10

10x25

5.3

15×25

12×10

12x10

10x25

5.4

Table 3: When the Length of the transistor M3 varied Transistor Dimensions (W× L) μm

M2 (W× L) μm

M3 (W× L) μm

Power Dissipation (mW)

Bandwidth in (MHz)

15×25

12×10

20x10

10x5

7.5

575

15×25

12×10

20x10

10x10

6.8

590

15×25

12×10

20x10

10x15

6.2

598

15×25

12×10

20x10

10x18

6.0

370

15×25

12×10

20x10

10x20

5.7

265

15×25

12×10

20x10

10x25

5.4

135

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12×10

20x25

10x15

5.75

384

The results of the above table are taken from the Tanner Tspice tool by using the 2.0 Mosis model file for the enhancement MOSFET transistor. The power dissipation and the bandwidth are directly, measures from the waveform editor in the Tanner EDA tool [5, 12].

Table 2: When the width of the transistor M2 varied

15×25

CONCLUSION AND FUTURE SCOPE

It is observed from the result that in case of single stage OnChip amplifier minimum power dissipation and maximum bandwidth is achieved when the Width of the M1 transistor is 18μm and the Length of the M1 transistor is 25μm meter and the Width of the Mc transistor is 10μmr and the Length of the Mc transistor is 16μm. In this case power dissipation is 4.3 milli-watts and the gain of the amplifier is 0.82 and bandwidth is 617MHz. In case of two stage amplifier maximum bandwidth is achieved when dimension of transistor is as M1(15μmx25μm), M2(20μmx10μm), M3(10μmx15μm) & Mc(12μmx10μm) and for minimum power dissipation the dimension of all the transistor should be M1(15μmx25μm), M2(20μmx10μm), M3(10μmx25μm) & Mc(12μmx10μm). The whole design simulated using MOSIS/Orbit 2.0μm process by using Tanner tool. In this paper Analog simulation is done by using the Tanner tool and using the enhancement type MOSFET transistor is used, this work can be further extended for the depletion type MOSFET because in depletion type MOSFET noise level will get further reduce and the other thing which can be improved in future is, semiconductor and environmental noise effect which is not consider in this current paper. REFERENCES [1] Gruner, Sol M. Tate, Mark W. Eikenberry and Eric F “Charge - coupled device area x-ray detectors”. Review of Scientific Instruments, page No. 2815 2842 Volume:73 Issue: 8

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[2] M.J.Howess & D.V.Morgan, “Charge-Coupled Devices and Systems”, John Wiley & Sons. [3] James R. Janesick, “Scientific Charge-Coupled Devices”, Spie Press Monograph Vol.85. [4] M.s Tyagi, “Introduction To Semiconductor Materials And Devices”, by John Wiley & Sons, Inc © 1991. [5] Dalsa web site; CCD Technology Primer; http://www.dalsa.com/corp/markets/ccd_vs_cmos.as px [6] Kodak CCD Primer, #KCP-001,”Charge coupled device (CCD) Image Sensors”, Eastman Kodak Company - Microelectronics Technology Division. [7] D.Barbe, "Imaging Devices Using the ChargeCoupled Concept". Proceedings of the IEEE, pp. 38-67, Jan. 1975. [8] Stuart A. Taylor, “CCD and CMOS Imaging Array Technologies: Technology Review”, Technical Report EPC106, Xerox Research Centre Europe, 1998. [9] Beynon J.D.E, “The Basic Principles Of Charge Coupled Devices”, MICROELECTRONICS, vol.7 No.2c 1975 Mackintosh Publications Ltd. Luton. [10] P. Centen, E. Roks. "Characterization of Surfaceand Buried-Channel Detection Transistors for On-Chip Amplifiers". Technical Digest IEDM97, pp.193-196, San Francisco, Dec 7-10, 1997. [11] S.M.Sze, “Semiconductor Devices, Physics and Technology 2nd Edition”, John Wiley & Sons (Asia) Pte. Ltd., Inc © 2002. [12] http://www.mosis.com/products/fab/vendors/tsmc/ts mc-kits.html

Dr. Rahul Malhotra* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 8, Issue No. 1, 107 - 112

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