BRAHMA REDDY.P et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 111 - 115
An Area efficient and low power design for decimation filter using CSD representation BRAHMA REDDY.P
GANESH REDDY.K
JAGANNADHA NAIDU.K
Student, MTech(VLSI Design) SENSE,VIT University, Vellore, Tamil Nadu, India p.brahmareddy409@gmail.com
Student, MTech(VLSI Design) SENSE,VIT University, Vellore, Tamil Nadu, India saiganesh453@gmail.com
Asst Prof, VLSI Division SENSE,VIT University,Vellore, Tamil Nadu, India jagannadhanaidu.k@vit.ac.in
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In audio applications, need for efficient digital filter has been increasing at high rate because of high speed and low power requirements. In this paper, we discussed design of a decimation filter used for high performance audio applications. We implemented decimation filter in order to obtain low-power with the use of canonical signed digit (CSD) representation. Basic requirement of this digital filter is to decrease the frequency spectrum and filtered out the feedback signal. The architecture of the proposed digital filter includes a 4- filter stage, i.e a comb filter and three stages of half-band finite impulse response (FIR) filters. The CSD representation is suitable for common sub expression elimination, and it significantly reduces the number of adders required for the filter synthesis. This project is implemented in CADENCE EDA tools using TSMC180nm library.
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Abstract:
because at each stage the filters operate at a lower sampling rate. comb filter used at the beginning of the decimation filter requires minimal hardware to perform down-sampling to low frequency components from high frequency components. canonic signed digit (CSD) representation is an efficient way for representing filter coefficients .In this paper, we implemented a decimation filter using a comb filter and three half-band FIR filters[4].The filter coefficients obtained are represented using CSD representation, which requires less hardware and consumes less power. The remainder of the paper is organized as follow. Section 2 describes the filter architecture. Section 3 presents the comb filter implementation section 4 presents half-band fir filter design, section 5 presents CSD number representation and CSD conversion algorithm and section 6 includes results. Table[1]. Filter specifications(ref[1]) 128
KEYWORDS: Decimation, Canonic signed digit, Comb filter, Half-band fir filter.
Pass band frequency
20khz
Pass band ripple
0.0001
1. INTRODUCTION :
Cut-off frequency
20khz
Need for decimation filter is to remove the quantization noise within the band of interest and avoid aliasing of high frequency down to low frequency components or within the signal bandwidth. This way of implementation reduces the power consumption, also utilizes much lesser hardware compared to few other designs this is
Output word length
16bits
Output word rate
10khz
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Decimation factor
2. FILTER ARCHITECTURE: In our design, we chosen a comb filter and half-band fir filters for implementing decimation filter. Decimation filter consists of four stages i.e, a comb filter and 3 stages of half-band fir filters.
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BRAHMA REDDY.P et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 111 - 115
filter stages.[3] since filter stages operate at low frequency which results in decrease in the hardware used and also reduces power consumed by these stages.[1] Comb filter is used as first stage of decimation filter as it is suitable to operate at high frequencies, whose response is a low pass filter with a sharper cut-off. Comb filter is a Sinc fir filter, which is realized using L+1 averaging filters, where L is the order of deltasigma modulator.[6] Transfer function of a single averaging filter Tavg(z) is given as Tavg(z) =
Comb-filter
X[n]
A
16-bit
16-bit
Half-band
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Fir1
16-bit
Half-band Fir2
Halfband
(1)
∑
T
Which is realized as follows , Tavg(z) =
(2)
Where cascade of L+1 filters is obtained as,
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Delta sigma modulator output bit pattern at 1.28Mhz is given as input for decimation filter whose output will be down sampled to 10khz with a pass-band ripple of 0.0001.[1] Comb filter is implemented as a combination of 3 stages of integrators and 3 stages of differentiators, and a decimation factor of 16 is used for down sampling. Comb filter output will down sample the sampling frequency from 1.28Mhz to 80khz. Also we used 3 stages of half-band fir filters with down sampling of 2 for each stage. The first halfband fir filter with input sampling frequency of 80khz has a pass band ripple of 0.00004, passband of 20khz, and stop-band attenuation of 110db, and the number of coefficients for this filter is 4. The second half-band filter has a sampling frequency of 40khz, has a pass band ripple of 0.00004, pass-band of 20khz, and stopband attenuation of -110db, and the number of coefficients for this filter is 4. The third half-band filter has a sampling frequency of 20khz, has a pass band ripple of 0.00001, pass-band of 20khz, and stop-band attenuation of -100db, and the number of coefficients for this filter is 8. Filter specifications of above decimation filter include as follows,
Tavg(z) =
(
)
(3)
Here we are choosing L+1 averaging filters in cascade because the order of analog low-pass filter in over sampling D/A converter should be higher than the order of ∆-∑ modulator.[6] Also the slope of the attenuation for this low-pass filter should be greater than the quantization noise, thereby resulting noise falls off at a relatively low frequency. An efficient way to realize cascaded averaging filters is as follows, x[n]
Y[n] 16-bit
Fir3
y[n]
Fig.1 comb filter architecture(Ref[1])
3. COMB FILTER IMPLEMENTATION: Comb filter decimates high frequency input signal to a low frequency signal and gives as input for ISSN: 2230-7818
Fig.2 comb filter as cascaded integrators and differentiators.[6]
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FIR filters offer control over filter shaping and linear phase performance. Due to its linear phase response, they are used in audio application, but at the cost of the high filter order.[2] A linear phase FIR filter requires large number of coefficients, we have implemented half-band FIR filter to reduce the number of coefficients.[4] In half-band filters, the number of taps is reduced considerably since the odd coefficients are zeros, which reduces the hardware and also power consumption. For the design of half-band filter with impulse response[3] h(n)={ Where i be any real number.
For a given M-bit representation of a number the signed digit representation can be related to its 2’s complement version as follows, X = -xM-12M-1 +∑
(4)
∑
Where xk {0,1} , Sk {-1,0,1} where SkSk-1=0 for k=1......M-1.[3]Signed digits are ternary, in contrast with 2’scomplement digits, which are binary.[5] The value of a CSD number can be obtained by summing terms Sk≠0.[3] Since always filter coefficients are normalized to x [-1,1]. CSD numbers can be represented as follows, X =∑
(5)
Where L is number of non-zero digits and } Pk {
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The number of taps in an FIR filter is proportional to the stop band rejection, the ratio of the sampling frequency, and the transition band. [1]Half-band FIR filter is realized as follows,
way for representing filter coefficients, since it reduces 33% of non-zero digits compared with the binary representation.
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4. HALF-BAND FIR FILTER DESIGN:
CSD CONVERSION ALGORITHM:
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Consider two’s complement representation of a number A as A=ậW-1 ậW-2........ ậ1 ậ0 and its CSD representation as A=aW-1 aW-2....... a1 a0 .[5]
X[n]
C2
C4
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C0
Y[n]
ậW = ậW-1 for(i=0 to W-1) {
C5
Fig.4 Half-band Fir filter
5. CSD REPRESENTATION:
It is an efficient way of representing signed digit numbers(twos complement numbers). The number set used for representing CSD number is {-1,0,1}, and also CSD is a unique representation such that no two consecutive bits in representing number are non-zero.[3] A number represented in CSD requires atmost non-zero digits where n is the total number of bits used for representing the number.[4] CSD number system is most efficient ISSN: 2230-7818
ậ-1=0 -1=0
i=ậi
ậW-1
i=
i
i -1
ậi = (1 - 2ậI+1)
i
}
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BRAHMA REDDY.P et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 111 - 115
Synthesis of the design is performed at 180nm by applying constraints for low power and area optimization using RTL compiler.
SIMULATION RESULT:
Decimation filter architectures
Power consumption(nW)
Area required(µm)
23707491.837
136182.816
With multiplier
33392443.479
154450.443
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Without multiplier
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It can be inferred from the obtained synthesized reports that by using CSD multiplier, since number of non-zero bits gets reduced to half there by amount of hardware(adders) required gets reduced, which results in reduction power dissipation but at the cost of area.
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CONCLUSION:
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Fig.4 Response for half-band fir filter
Input to a comb filter is 1.28Mhz which is the output of oversampling converter. In this filter decimation factor 16 is used, there output of comb filter is 80Khz.This is the input frequency of 3stage half band fir filters in which each half band fir is decimates individually by a factor of 2, the total decimation factor of cascaded half band fir filters is8.so the output sampling frequency is 10Khz.Above results are obtained using matlab, also verified the same for low power and compactness in are using synthesis tool. Also functionality is verified using modelsim through observing the down sampling i.e missing samples with respect to the given down sampling rate.
In this paper, we have implemented a decimation filter designed for high performance audio applications. which includes a comb filter and 3-stages of half-band fir filters are designed and implemented using Matlab and verified for real time application using Modelsim. Filter coefficients are represented using hardware efficient CSD(ternary) representation. And CSD multiplier is used to perform general multiplication which requires less number of adders thereby it reduces the amount of hardware required . Also the design implemented is synthesised in cadence RTL complier using tsmc 180nm and verified for low power consumption and compact with respect to area. REFERENCES: [1] Khalid H. Abed, Shailesh B. Nerurkar and StephenColaco,“Design and implementation of adecimationfilterforhighperformanceaudioapplicat ions”Electronics, circuits and systems,2007,ICECS2007,14thIEEEinternationalc onference,page no: 812-815.
SYNTHESIS REPORT: ISSN: 2230-7818
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[2] K.Shunhagavalli andDr.P.Vanaiaranian, “An area optimization of decimation filter using csd representation for hearing aid application”Irish signals and systems conference,2006,IET publication 2006,page:303-307.
[4] Guo-Ming Sung and Hsiang-Yuan Hsieh “An ASIC design for decimation filter with canonic signed–digit representation”Intelligent signal processing and communication systems, 2008. ISPACS 2008.page:1-4.
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[5] keshab k.parhi,”VLSI Digital signal processing systems, Design and Implementation” John Wiley and Sons Pte Ltd
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[3] Khalid H. Abed and Vivek Venugopal and Shailesh B. Nerurkar,“High speed digital filter design using minimal signed digit representation”southeastcon,2005,proceedings,IE EE,10.1109/SECON.2005.1423227.page:105-110
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[6] ken martin “ANALOG INTEGRATED CIRCUIT DESIGN” wiley publications.
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