Hanish chowdary .v et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 141 - 143
Variable Frequency Scheme for Low Power Digital Circuits Mahaboob Alisha Syed Mtech VLSI DESIGN SENSE, VIT University, Vellore, Tamil Nadu, India m_syed6@yahoo.com
Abstract: Now-a-days, power dissipation is one of the most significant focus in VLSI design. The most widely used operation performed today is multiplication. The multiplier is the complex cell which occupies more area and dissipates more power compared to all cells in library. In this paper we explore the possible way to reduce complexity in FIR filter by reducing the number of multiplication operators.
Jagannadha Naidu .k Asst Prof, VLSI Design SENSE, VIT University, Vellore, Tamil Nadu, India jagannadhanaidu@vit.ac.in
Implementation of digital filters using signed power of two (SPT). Drawbacks: The drawback of this technique is low accuracy and overflow
Implementation of filters using canonical signed digit(CSD). Drawback: It cannot generate programmable coefficients. Some techniques use shift and add multiplication algorithm with common subexpression elimination (CSE). All these schemes although simple does not guarantee the optimal solution.
A
ES
So, Computation sharing multiplication technique [1] which uses the pre-computation bank is used, to decrease the number of multiplications so that power can be saved. We implemented this technique in FIR filter. This paper combines two techniques Computation sharing multiplication (CSHM) and adaptive frequency scaling which has been applied for the FIR filter. Self timed circuit in synchronous environment is used for applying the above techniques. To avoid problems at the synchronous interface, care must be taken such that FIFO should never become full or empty. So, depending upon the state of the FIFO the clock frequency is adjusted.
Reddy E.V.K Pinnitla Mtech VLSI DESIGN SENSE, VIT University, Vellore, Tamil Nadu, India eshwar455@gmail.com
T
Hanish chowdary .v Mtech VLSI DESIGN SENSE, VIT University, Vellore, Tamil Nadu, India vhanish221@gmail.com
Keywords: Computation sharing multiplication (CSHM) , Finite impulse response (FIR) , FIFO
I. INTRODUCTION:
IJ
As there is a need for improving the data rates with reduced power dissipation. One of the most widely used operations is finite impulse response (FIR) filtering [5]. This process involves product of filter coefficients with input signal x. In this paper, we tried to reduce the complexity in FIR filter by removing the computation redundancy by synthesis phase of filter. The implementation of filters with CSHM architecture reduces computation complexity and increases reusability which helps in power sharing.
II. CSHM APPROACH:
A.) CSHM Multiplier: This multiplier reduces
power consumption of FIR filter with real value coefficients. It consists of precomputed, select units, shifters and adders. To cover every possible coefficient
and multiplication operation we used 8 alphabets.( 1x, 3x, 5x, 7x ,9x, 11x, 13x, 15x).
B.) CSHM Architecture: This technique is not power efficient for a single multiplication operation. The computation 1x, 3x, 5x, 7x, 9x, 11x,13x,15x will be performed once and shared by all
The optimization of constant multiplication problem (multiplication of input by filter coefficient) has been accomplished in different ways .Many researchers reported different techniques to reduce the computational redundancy.
ISSN: 2230-7818
@ 2011 http://www.ijaest.iserp.org. All rights Reserved.
Page 141
Hanish chowdary .v et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 141 - 143
in the down module is again shifted to left by four times before it is given to the adder where it is added with the upper module output. Finally, the result we get will be equivalent to 11100100x i.e. CX. Hence with the use of precomputed blocks, shifter and adder we are able to perform the multiplication operation. The advantages in power saving are observed when more number of multiplication operations are required III. PROPOSED ARCHITECTURE
converter
T
DC TO DC
State Detector
FIFO Buffer
FIR with CSHM
ES
R E G
Clk1 clk1
Fig1: CSHM architecture [4]
IJ
A
Let us consider an example for the complete understanding of the CSHM. Suppose our coefficient C is a 8 bit number 11100100[4].The last four bits are given to the upper module shifter in which the right shift operation should take place until a 1 is found in the LSB bit[4]. This is to match with the computation stored in the pre-computed bank. As the product of odd numbers with the input signal x are multiplied and stored in the pre-computed bank the shifted bits with the last bit one will match with that in the pre-computed bank data. The number of shift operations until we get 1 in last bit is stored and given to the lshifter. In the final output of right shifter the first three bits are given as the select lines to the mux and the corresponding data from the pre-computed banks are selected. In our example 0100 is given to the upper module and two shits take place so 10 is given to the lshift. After two shifts the output of right shift is 0001 so the first three bits 000 are given as select lines to the mux which selects the 1x from the precomputed banks and given to the lshift. There again two left shift operation take place as two is given from right shifter to lshift. So, the resultant from the lshift is equivalent to the 0100[4].
FIG2: Self timed circuit in synchronous environment [2].
The whole architecture operates in synchronous environment [2]. In this architecture, data is written into the buffer at the faster rate compared to speed at which data is read and pumped into FIR. The state detector compares the data rates of writing and reading operations of buffer and generates a signal to increase the rate of reading data from buffer such that buffer will never become full . Similarly buffer never becomes empty, if data is read at a faster rate from FIFO. So the voltage gets scaled depending upon the data rate. IV RESULTS: Synthesis has been done for basic constant multiplier and CSHM based FIR filter (8 – tap) . The filter programmable coefficients are generated using MATLAB. Their reports are summarized as below. The synthesis is performed using Cadence RTL Compiler with the technology library tsmc-90 nm and operating voltage is 1V.
The same procedure is repeated with the down module to which the first four bits are given as inputs. The result
ISSN: 2230-7818
@ 2011 http://www.ijaest.iserp.org. All rights Reserved.
Page 142
Hanish chowdary .v et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 141 - 143
POWER REPORT (nW)
Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on Page(s): 1245 1248 volume.2.
AREA REPORT (u m2)
S.No
FIR FILTER
1.
With constant multiplier
444095
7589
2.
With CSHM multiplier
277147
3948
2.
Lars S. Nielsen, Cees Niessen, Jens Sparso, and Kees van Berkel, Dept. of Comput. Sci., Tech. Univ. ― Low-power operation using self-timed circuits and adaptive scaling of the supply voltage" Denmark, Lyngby Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Page(s): 391 – 397, Publication Year: 1994 .
3.
Georgios Karakonstantis and Kaushik Roy School of Electrical and Computer Engineering, Purdue University ―A n optimal algorithm for low power multiplierless fir filter design using chebychev criterion” Acoustics, Speech and Signal Processing, 2007. ICASSP 2007. IEEE International Conference on Volume: 2, Publication Year: 2007, , Page(s): II-49 - II-52
V Future work:
ES
The power consumed by the FIR filter with constant multiplier is more compared to the FIR filter with CSHM multiplier if the numbers of computations are more. Simulation is done using 90nm technology. Area occupied is also less in the CSHM filter compared to FIR constant multiplier.
To the proposed architecture, we can save the power further by using adaptive supply voltage scaling. Scaling of voltage is done with work load estimation of FIFO which. is operating in synchronous environment . If the FIFO is running empty the supply voltage applied to FIR will get scaled to lower voltage level such that data from FIFO can be read at lower rate. Similarly if FIFO is running full, the supply voltage gets increased.
A
VI Conclusion:
T
Table.1
IJ
In this paper, we proposed a CSHM FIR filter architecture which is power and area efficient. It helped us to achieve low power and high performance. The design which was presented in this paper is simple but effective for synchronous low power digital circuits. There are number of power efficient techniques to reduce the computational redundancy in FIR filters but each technique has its own drawbacks.
4.
Ji-Woong Choi, Senior Member, IEEE, Jungwon Lee, Member, IEEE, Byung Gueon Min, and Jongsun Park, Member, "Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver" IEEE transactions on circuits and systems—ii: express briefs, vol. 57, no. 8, august 2010, on page(s): 632-636.
5.
Sandeep dhar and Dragan maksimovic department of electrical and computer engineering university of Colorado, boulder, co 80309-0425 ― Low-Power Digital Filtering Using Multiple Voltage Distribution and Adaptive Voltage Scaling”, vol 2, on pages 207-209.
In this technique we reduced the complexity and improved the reusability. In addition to that we controlled the data rate for efficient operation of FIR using FIFO in synchronous environment.
VII References: 1.
Hunsoo Choo, Khurram Muhammad and Kaushik Roy School of Electrical and Computer Engineering, Purdue University West Lafayette, IN 47907, USA, ― Decision feedback equalizer with two's complement computation sharing multiplication”
ISSN: 2230-7818
@ 2011 http://www.ijaest.iserp.org. All rights Reserved.
Page 143