33.IJAEST-Vol-No-5-Issue-No-2- Energy-Efficient-Domino-VLSI-Circuits-and-their-Performance-with-PVT- by ISERP ISERP

Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

Energy-Efficient Domino VLSI Circuits and their Performance with PVT Variations in DSM Technology Salendra.Govindarajulu1, Dr.T.Jayachandra Prasad2, Chimakurthy.Sreelakshmi3, C.H.Balaji4,

Associate Professor, ECE, RGMCET, Nandyal, JNTU, A.P.State, India, Email: rajulusg06@yahoo.co.in 2 Principal, RGMCET, Nandyal, JNTU, A.P.State, India, Email: jp.talari@gmail.com 3 PG Student, ECE, RGMCET, Nandyal, JNTU, A.P.State, India, Email: sreelakshmi0718@gmail.com 4 UG Student, KLU, Vijayawada. II. DUAL-RAIL DOMINO FOOTLESS CIRCUIT WITH SELF- TIMED PRECHARGE SCHEME (DRDFSTP): Conventional domino circuits: In this section, several conventional domino circuits with their own clocking schemes are briefly reviewed. A. Dynamic DCVSL Footed Circuit (DDCVSLF): Fig.1 shows AND/NAND dynamic DCVSL Footed circuit. One of the disadvantages of this kind of domino circuit is that the existence foot transistor slows the gates somewhat, as it presents an extra series resistance. Moreover, simultaneous precharge may cause an unacceptable IR-drop noise.

Abstractâ&#x20AC;&#x201D; Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in dynamic logic such as domino is often used in performance critical paths, to achieve high speeds where static CMOS fails to meet performance objectives. However, domino gates typically consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static CMOS gates. Keeping in view of the above stated problems in previous existing designs, novel energyefficient domino circuit techniques are proposed. The proposed circuit techniques reduced the dynamic switching power consumption; short-circuit current overhead, idle mode leakage power consumption and enhanced evaluation speed and noise immunity in domino logic circuits. Also regarding performance, these techniques minimize the power-delay product (PDP) as compared to the standard full-swing circuits in deep sub micron CMOS technology. Also the effect of the Process, Voltage and Temperature (PVT) variations on the performance of the CMOS Domino circuits with various techniques are analyzed.

Key words: Dynamic, Domino, Noise Margin, Deep submicron technology (DSM), High speed, Power consumption, Power delay product (PDP), PVT variations, Reduced dynamic swing.

IJ A

I. INTRODUCTION

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power dissipation. However, domino gates typically consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static CMOS logic circuits. In this paper novel energy-efficient domino circuit techniques are proposed. This paper is organized as follows. In section II, Dual-rail domino circuit with self-timed precharge scheme is proposed. The Reduced dynamic swing domino logic is presented in section III. Section IV describes performance evaluation results of energy-efficient dynamic node low voltage swing with dual supply, dual grounds and dual-Vt domino logic. Section V describes the effect of PVT variations on domino logic presented in section II, III, IV. Then conclusions are presented in section VI.

ISSN: 2230-7818

Fig.1. Dynamic DCVSL AND/NAND Footed gate B. Dynamic DCVSL Footless Circuit (DDCVSLFL): Fig.2 shows AND/NAND dynamic DCVSL Footless circuit. Two benefits come from the usage of footless domino gates: improved pull-down speed and reduced precharge signal load. Main disadvantage is simultaneous precharge will cause short-circuit current.

Fig. 2. Dynamic DCVSL AND/NAND Footless gate

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

Fig.3 illustrates the delayed-reset domino AND/NAND circuit [3]. However, the use of delay elements, together with the need of both footed and footless cell libraries tends to increase design complexity.

Fig:3. The delayed-reset domino AND/NAND circuit D.

Dual-Rail Data-Driven Dynamic Logic (D4L):

Fig:5. Dual-rail footless domino AND/NAND gate with selftimed precharge scheme. Simulation results:

In this work, we have implemented a Dynamic DCVSL circuit, Dual-Rail Data-Driven Dynamic Logic and a proposed circuit Dual-Rail Domino Footless Circuit with Self-Timed Precharge Scheme. The results of simulation are shown in the below TABLES1-3.

D4L circuit uses input signals instead of precharge signal for correct precharge and evaluation sequencing [5]. Correspondingly, clock-buffering and clock-distribution problems can be eliminated. Furthermore, the foot transistor can be eliminated without causing a short-circuit problem. A D4L two-input AND/NAND gate is shown in Fig.4.

self-timed precharge scheme. The self-timed precharge control logic consists of static CMOS inverter whose source of NMOS transistors are tied to input signals, which generate subprecharge signals (PC1-PC4) from precharge signal P in cases of the corresponding input signals are zero. The PMOS precharge tree above the pull down network (PDN) is used for precharging the corresponding gate.

C. Delayed-Reset Domino Circuit (DRDC):

IJ A

Table1. AND/NAND GATE

Fig.4. Dual-Rail Data-Driven Dynamic AND/NAND Logic ( D4L) Dual-Rail Domino Footless Circuit with Self- Timed Precharge Scheme (DRDFSTP): The presence of the foot transistor in the conventional dynamic DCVSL circuit shows the gate somewhat, as it presents an extra series resistance. To safely remove the transistor, two constraints must be met: (1) gate changes to evaluation phase before valid input come; (2) gate changes to precharge phase only after inputs change to zero. We propose a footless duail-rail domino circuit with self-timed precharge scheme to realize a high performance footless domino circuit while meeting the constraints mentioned above. It is expected that the peak of precharge current could be reduced due to the self-timed precharge scheme. Fig. 9 shows the AND/NAND gate of the proposed footless dual-rail domino circuit with

ISSN: 2230-7818

Technique

Power (Âľw)

PDP (10-15 ws) 0.6688 3.8

Area (Âľ.sqm)

7.6 152

Critical Delay (ns) 0.088 0.025

DDCVSLF DDCVSLF L DRDC

205

0.137

28.085

252.9

D4L

72.555

0.111

8.053606

93.3

DRDFSTP

7.676

0.042

0.322392

177.6

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69.62 65.41

Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

B. Reduced–Swing Domino with Single supply (RSSLS):

Table2. OR/NOR GATE

Power (µw)

PDP (10-15 ws) 0.65946 13.05

Area (µ.sqm)

7.58 145

Critical Delay (ns) 0.087 0.090

DDCVSLF DDCVSLF L DRDC

220

0.403

88.66

290

D4L

10.163

0.112

1.138256

78.48

DRDFSTP

7.583

0.042

0.318486

130.18

74.82 66.59

Table3. XOR/XNOR GATE

Power (µw) 11.7 99.023

Critical Delay (ns) 0.032 0.032

PDP (10-15 ws) 0.3744 3.1687

DDCVSLF DDCVSLF L DRDC

Area (µ.sqm)

231

0.091

21.021

D4L

16.802

0.029

0.487258

100.5

DRDFSTP

11.642

0.04

0.46568

200.13

99.2 92.17

Fig.7.Reduced – Swing Domino with Single supply C. Reduced Swing Mirror Domino (RSMRD): This is one of the alternative approaches for having reduced swing, which is shown in fig.8. This is an arrangement in which the precharge and footer transistors are exchanged with an NMOS and PMOS transistor respectively.

Technique

The RSDLS circuit shown above is simplified by replacing the extra supply voltages with transistors providing the desired threshold voltage drops. The configuration is shown in fig.7.

Technique

391.9

III. REDUCED DYNAMIC SWING DOMINO (RDSDOMINO):

IJ A

A. Reduced–Swing Domino with Dual supply (RSDLS):

The first circuit configuration proposed to reduce the dynamic node voltage swing is obtained by simply altering the appropriate supply voltages of the standard domino gates as shown in fig.6.

Fig.8.Reduced Swing with Mirror Domino

This arrangement dictates that the precharge and evaluate cycles be reversed with regard to clock. That is, clock begins high corresponding to precharge and clock goes low corresponding to the evaluate cycle. Given this arrangement, the voltage swing of the internal dynamic node is limited by the transistor thresholds. The supply voltage and the input/output signals all remain unmodified. Simulation results: The benchmark circuits using the stated four techniques are implemented. The figures of merits used to compare these techniques are power consumption, propagation delay and power delay product (PDP). The benchmark circuits implemented are OR2 gate, AND2 gate, XOR2 gate, 16-bit Full adder, 16-bit Comparator , D-flip flop and 4-bit LFSR (Linear Feedback Shift Register).

Fig.6. Reduced–Swing Domino with Dual Supply

This circuit is here after referred to as a reduced–swing (RSDLS) domino gate with dull supply.

ISSN: 2230-7818

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65nm 65nm 65nm

0.007 17.094 0.0322

0.032 0.023 0.016

Power Delay Product (*10-15 Watt-Sec) 0.0000224 0.393162 0.0005152

65nm

0.433

0.054

0.023382

Techniques

RSDLS RSSLS RSMRD StdDomino

Power(µ Watts)

Delay(ns)

Table5. Optimum values of different techniques of 2-input AND Gate

65nm 65nm 65nm

Delay (ns) 0.026 0.017 0.044

65nm

0.506

0.102

0.051612

Table6. Optimum values of different techniques of 2-input XOR Gate

Delay(ns)

RSDLS

65nm

22.881

0.046

1.052526

RSSLS

65nm

23.002

0.067

1.541134

RSMRD StdDomino

65nm

1.592

0.067

0.106664

65nm

1.711

0.102

0.174522

IJ A

TECHNIQUES

Power (µ Watts)

Power Delay Product (*10-15 Watt-Sec)

Table7. Optimum values of different techniques of 16-bit adder

Techniques

Power (µ Watts)

Delay(ns)

Power Delay Product (*10-15 Watt-Sec)

RSDLS

65nm

0.15

0.025

0.00375

RSSLS

65nm

0.649

0.073

0.009735

RSMRD StdDomino

65nm

1.909

1.682

0.03818

65nm

0.586

24.825

0.015236

ISSN: 2230-7818

Power Power Techniques

Delay

Product

Delay

(*10 -12 Watt-

Watts)

(ns)

Sec)

RSDLS

65nm

1.053

0.069

0.072657

RSSLS

65nm

1.07

0.058

0.06206

RSMRD

65nm

6.901

0.041

0.282941

65nm

0.833

0.033

0.027489

STDDOMINO

Table9. Optimum values of different techniques for D-Flip flop

Techniques

Techniques RSDLS RSSLS RSMRD StdDomino

Power(µ watts) 21.635 32.102 0.355

Power Delay Product (*10-15 WattSec) 0.56251 0.545734 0.01562

Table8. Optimum values of different techniques for 16-bit comparator

Table4. Optimum values of different techniques of 2-input OR Gate

Power (m Watts)

Delay(ns)

Power Delay Product (*10-12 Watt-Sec)

RSDLS

65nm

0.01925

0.118

0.0022715

RSSLS

65nm

0.115

0.083

0.009545

RSMRD STDDOMINO

65nm

0.118

0.075

0.00885

65nm

0.05964

0.270

0.0161028

Table10. Optimum values of different techniques for 4-bit LFSR

Techniques

Power (m Watts)

Delay (ns)

RSDLS

65nm

0.0244

0.780

RSSLS

65nm

0.683

0.275

RSMRD STDDOMINO

65nm

0.293

0.299

65nm

1.455

2.156

Power Delay Product (*10-12WattSec) 0.01 9032 0.18 7825 0.08 7607 3.13 698

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

IV. DYNAMIC NODE LOW VOLTAGE SWING DOMINO LOGIC CIRCUITS WITH DUAL POWERS, GROUNDS AND DUAL VT:

The single Vt domino logic circuit with dual power supply, dual ground is shown in Fig.11.

This section discusses several dual threshold voltage domino circuit design techniques to reduce the power dissipation of domino logic while simultaneously improving noise immunity. The benefits are achieved by limiting the voltage swing of the internal dynamic node in a typical domino gate. This dynamic storage node is the node connected to the input of the output inverter of a domino gate as shown in fig.9.

B.Single Vt domino logic circuit with dual power supply, dual ground: (DUAL SUPPLY)

Fig.11. The dynamic node low voltage swing domino circuit technique with dual power supplies and ground voltages VDDL<VDD , VgndH>Vgnd

C. Dual Vt Domino Logic circuit With Dual power supply,Dual Ground(N1 High Threshold): (DUAL N1)

Fig.9. Dynamic node low voltage swing domino logic circuit The above circuit is used to reduce the voltage swing at the dynamic node of a domino gate. A complete analysis of the effects of the reduced swing at the dynamic node on both noise tolerance and propagation delay is presented with respect to specific circuit configurations below. A. Single Vt domino logic circuit with keeper: (NORMAL)

The dual Vt domino logic circuit with dual power supply, dual ground (N1 high threshold) is shown in Fig.12. The NMOS transistor in the output inverter has high Vt. Short circuit current is therefore reduced only in the evaluation phase if the inputs are high. Hence evaluation speed of the circuit is higher as compared to N1, P1 high threshold technique.

IJ A

The single Vt domino logic circuit with keeper is shown in Fig.10. Keeper circuit is used to maintain the voltage level at dynamic node which also increases the noise immunity. The voltage at the dynamic node should be VDD but gets diminished due to several reasons, by using the keeper in the above circuit with P2, N2 transistors pair forming inverter turns ON Pk transistor which pulls dynamic node to VDD.

Fig.12. The dynamic node low voltage swing domino circuit technique with dual power supplies and ground voltages VDDL<VDD , VgndH>Vgnd and with N1 high threshold D. Dual Vt domino logic circuit with dual power supply, dual ground (N2 ground):

Fig.10. Domino logic circuit with keeper.

ISSN: 2230-7818

The dual Vt domino logic circuit with dual power supply, dual ground (N1 high threshold) is shown in Fig.13. N2 FET

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

Fig.13. The dynamic node low voltage swing domino circuit technique with dual power supplies and ground voltages VDDL<VDD , VgndH>Vgnd and with N2 Ground

Fig.15. dynamic node low voltage swing domino circuit technique with dual power supplies and ground voltages VDDL<VDD , VgndH>Vgnd and with N1, P2, Pk high thresholds G. Dual Vt domino logic circuit with dual power supply, dual ground (P11,PK,P1 high threshold): The dual Vt domino logic circuit with dual power supply, dual ground (P11, PK, P1 High threshold) is shown in fig.16. P11, Pk, P2 FETs threshold voltages are increased, these modifications are made to the basic circuit in order to analyze the variations in the parameters like power, delay, area, power delay product (PDP) and to find the efficient technique.

E. Dual Vt domino logic circuit with dual power supply, dual ground (N1, P1 high threshold): (DUAL N1,P1)

modifications are made to the basic circuit in order to analyze the variations in the parameters like power, delay, area, power delay product (PDP) and to find the efficient technique.

is grounded; these modifications are made to the basic circuit in order to analyze the variations in the parameters like power, delay, area, power delay product (PDP) and to find the efficient technique.

IJ A

The dual Vt domino logic circuit with dual power supply, dual ground (N1, P1 High Threshold) is shown in Fig.14. The short circuit current produced by the output inverter is suppressed during both the precharge and evaluation phases of operation, since the NMOS and PMOS transistors in the output inverter have high Vt. However, evaluation speed is also degraded due to the weaker pull-up strength of high Vt PMOS transistor.

Fig.14. The dynamic node low voltage swing domino circuit technique with dual power supplies and ground voltages VDDL<VDD , VgndH>Vgnd and with N1, P1 high thresholds F. Dual Vt domino logic circuit with dual power supply, dual ground (Pk, P2, N1 high threshold):

The dual Vt domino logic circuit with dual power supply,

dual ground (Pk, P2, N1 high threshold) is shown in Fig15. P2, N1 FETs threshold voltages are increased, these

ISSN: 2230-7818

Fig.16. dynamic node low voltage swing domino circuit technique with dual power supplies and ground voltages VDDL<VDD , VgndH>Vgnd and with Pk, P1, P11 High thresholds Simulation results: In this work, the benchmark circuits using the stated seven techniques are implemented. The benchmark circuits implemented are OR2, AND2, XOR2, 16-bit Full Adder, 16bit Comparator, D-Latch, 4-bit LFSR. Here the results are given for 16-bit Full Adder, 16-bit Comparator, D-Latch, 4-bit LFSR.

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Table11. Optimum values of different techniques for 16-bit adder PDP(10-12 w-s)

S.N o

TECHNIQU ES

POWER(m w)

DELAY( ns)

11.062

127.081

10.958

99.218

1405.7589 6 1087.2308 44

NORMAL N2 GROUND DUAL POWER SUPPLY

11.402

100.63

PK ,P11, P1

12.088

PK ,P2, N1

20.15

DUAL P1, N1

21.88

100.633

DUAL N1

10.245

90.907

S.NO

DELAY( ns)

12826.9

NORMAL

4.587

6.797

31.1778 39

2255.05

1147.3832 6

13782

2.976

8.245

24.5371 2

2493.05

61.160

739.30208

12159.48

2.882

7.434

21.4247 88

2472.36

42.118

848.6777

15409.67

12809.5

TECHNIQU

POWER(m

DELAY(

ns)

NORMAL

10.475

104.86

GROUND

8.204

156.921

DUAL POWER SUPPLY

7.795

PK ,P11, P1

8.457

10371

PDP(10-12

Area(mic

w-s)

sq.meter)

1098.4085

18914 19316

209.5

1633.0525 1271.1885

18329.6

150.312

18369.4

IJ A

1265.0123

DUAL P1,

20240.6

105.00109

10.432

119.209

18453

1279.5316

DUAL N1

8.56

ISSN: 2230-7818

149.478

PK ,P11, P1

3.08

5.436

16.7428 8

2468.4

PK ,P2, N1

2.929

5.452

15.9689 08

2482.7

DUAL P1, N1

2.889

5.409

15.6266 01

2463.3

5.404

16.0390 72

2483.34

15269

1287.3798

148.72

N2 GROUND DUAL POWER SUPPLY

2210.8500 4 931.34221 5

S.N

8.506

Area(mic ro sq.meter)

POWER(m w)

comparator

PK ,P2, N1

PDP(1012 w-s)

TECHNIQU ES

Table12. Optimum values of different techniques for 16-bit

LFSR

Area(mic ro sq.meter)

Table13. Optimum values of different techniques for 4-bit

18840

DUAL N1

2.968

Table 14. Optimum values of different techniques for D-Latch S.N O

TECHNIQU ES

POWER(m w)

DELAY(n s)

NORMAL

0.158

0.572

GROUND

PDP(10 -12 w-s) 0.09037 6

Area(mic ro sq.meter) 215.56

0.07530

0.163

0.467

254.92

0.1177

261.41

DUAL

POWER 3

SUPPLY

0.22

0.535

PK ,P11, P1

0.169

0.385

PK ,P2, N1

0.169

0.383

0.06506 5

258.69

0.06472 DUAL P1,

262.885

0.06219

0.169

0.368

DUAL N1

0.169

0.358

256.11

0.06050

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

V. PROCESS, VOLTAGE AND TEMPERATURE VARIATIONS (PVT) ON THE PERFORMANCE OF DOMINO LOGIC: The effect of PVT variations on the domino logic circuit techniques which are explained in sections II, III, IV are

(Oxide layer thickness) and UO (carrier mobility). The

The PVT variances

on the domino logic in sections II, III, IV are given in below Tables15-23.

studied and analyzed in this section. The process variations considered are VTHO (Threshold voltage at zero bias), TOXE PVT Variations for section II:

AND/NAND

VTHO= 0.3 TOXE= 0.7 UO=0.0 30

POWER DISSIPATIO N (µW) ION (ma)

7.520

0.120

OR/NOR

IOFF (na)

Dynamic DCVSL Footless

POWER DISSIPATIO N (µW) ION (ma) IOFF (na)

Delay Reset Domino Circuit

POWER DISSIPATIO N (µW) ION (ma)

ISSN: 2230-7818

XOR/XNOR

VTHO= 0.35 TOXE= 1.1 UO=0.0 55

VTHO= 0.4 TOXE= 1.6 U0=0.08

VTHO= 0.3 TOXE= 0.7 UO=0.0 30

VTHO= 0.35 TOXE= 1.1 UO=0.0 55

VTHO= 0.4 TOXE= 1.6 U0=0.08

VTHO= 0.3 TOXE= 0.7 UO=0.0 30

VTHO= 0.35 TOXE= 1.1 UO=0.0 55

VTHO= 0.4 TOXE= 1.6 U0=0.08

7.6

7.623

7.565

7.58

7.45

11.330

11.7

11.23

0.250

0.358

0.120

0.250

0.358

0.120

0.250

0.358

IJ A

Dynamic DCVSL Footed

Table15.PROCESS VARIATIONS (V AND T CONSTANT)

BENCHMARK CIRCUITS

100

152

153

102

145

161

98.427

99.023

99.400

0.120

0.250

0.358

0.120

0.250

0.358

0.120

0.250

0.358

201.872

205

204.347

94.254

220

221.392

230.013

231

231.925

0.051

0.107

0.153

0.051

0.107

0.105

0.051

0.107

0.105

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POWER DISSIPATIO N (µW) ION (ma) IOFF (na)

Foot Less Duail-Rail Domino Circuit with Self Timed Precharge Scheme Logic

POWER DISSIPATIO N (µW) ION (ma) IOFF (na)

BENCHMARK CIRCUITS

48.316

72.555

85.268

8.846

10.163

10.475

13.914

16.802

13.85

0.120

0.250

0.358

0.120

0.250

0.358

0.12

0.250

0.358

7.446

7.676

7.765

7.400

7.583

7.773

11.61

11.642

10.007

0.120

0.205

0.358

0.120

0.205

0.358

0.120

0.250

0.247

AND/NAND

IOFF(na)

Dynami c DCVS L Footles s

POWER DISSIPATION(µ W) ION(ma) IOFF(na)

Delay Reset Domin o

POWER DISSIPATION(µ W)

ISSN: 2230-7818

VDD=0. 8

OR/NOR

VDD=1

IJ A POWER DISSIPATION(µ W) ION(ma)

Table16.VOLTAGE VARIATIONS (P AND T CONSTANT)

VDD=0.7

Dynami c DCVS L Footed

Duail-Rail Data Driven Dynamic Logic

IOFF (na)

XOR/XNOR

VDD=0. 7

VDD=0. 8

VDD=1

VDD=0. 7

VDD=0. 8

VDD=1

7.152

7.153

7.6

7.141

7.524

7.58

9.345

11.809

11.7

0.131

0.171

0.250

0.131

0.171

0.250

0.131

0.171

0.250

100.714

101.621

152

102.185

145.317

145

98.264

99.821

99.023

0.131

0.171

0.250

0.131

0.171

0.250

0.131

0.171

0.250

67.053

102

205

94.217

94.712

220

220.013

230.983

231

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

DuailRail Data Driven Dynami c Logic

ION(ma)

0.131

0.171

0.107

0.131

0.171

0.107

0.131

0.171

0.107

IOFF(na)

54.187

72.868

72.555

9.127

9.217

10.163

14.717

16.504

16.802

0.131

0.171

0.250

0.131

0.171

0.250

0.131

0.171

0.250

7.885

7.278

7.676

7.317

7.155

7.583

11.521

11.504

11.642

0.131

0.171

0.250

0.131

0.171

0.250

0.131

0.171

0.250

POWER DISSIPATION(µ W) ION(ma) IOFF(na) POWER DISSIPATION(µ W) ION(ma) IOFF(na)

Foot Less DuailRail Domin o Circuit with Self Timed Prechar ge Scheme Logic

BENCHMARK CIRCUITS

Circuit

Table17.TEMPERATURE VARATIONS (P AND V CONSTANT) AND/NAND

127

IJ A

-73

OR/NOR

Dynamic DCVSL Footed

POWER DISSIPATION(µ W) ION(ma) IOFF(na)

Dynamic DCVSL Footless

Delay Reset Domino Circuit

XOR/XNOR

-73

127

-73

127

7.503

7.6

7.768

7.425

7.58

8.025

11.369

11.7

11.691

0.445

0.250

0.163

0.445

0.250

0.163

0.445

0.250

0.163

POWER DISSIPATION(µ W) ION(ma)

246

152

108

247

145

112

169

99.023

77.078

0.445

0.250

0.163

0.445

0.250

0.163

0.445

0.250

0.163

IOFF(na)

208.507

205

217.451

162

220

72.266

116

231

248.93 7

0.190

0.107

0.069

0.190

0.107

0.069

0.107

0.069

POWER DISSIPATION(µ W) ION(ma)

ISSN: 2230-7818

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IOFF(na) Duail-Rail Data Driven Dynamic Logic

POWER DISSIPATION(µ W) ION(ma)

94.835

72.555

59.951

4.072

10.163

11.788

5.767

16.802

22.507

0.445

0.250

0.163

0.445

0.250

0.163

0.445

0.250

0.163

7.555

7.676

8.355

7.408

7.583

8.358

9.024

11.642

13.708

0.445

0.250

0.163

0.445

0.250

0.163

0.445

0.250

0.163

IOFF(na) POWER DISSIPATION(µ W) ION(ma) IOFF(na)

Foot Less Duail-Rail Domino Circuit with Self Timed Precharge Scheme Logic

PVT Variations for section III:

AND2

OR2

VTHO =0.4 TOXE= 1.6 U0=0.8

VTHO =0.3 TOXE= 0.7 UO=0. 030

XOR2

VTHO =0.4 TOXE= 1.6 U0=0.8

IJ A

VTHO =0.3 TOXE =0.7 UO=0. 030

Table18.PROCESS VARIATIONS (V AND T CONSTANT)

BENCHMARKCIRCUI TS

STD DOMINO

POWER DISSIPAT ION(µW) ION(ma) IOFF(na)

RSSLS

POWER DISSIPAT ION(µW) ION(ma) IOFF(na)

RSDLS

POWER DISSIPAT ION(µW) ION(ma)

ISSN: 2230-7818

D-LATCH

4-BITLFSR

VTHO=0. 3 TOXE=0.7 UO=0.030

VTHO=0. 4 TOXE=1. 6 U0=0.8

VTHO= 0.3 TOXE=0 .7 UO=0.0 30

VTHO =0.4 TOXE =1.6 U0=0.8

VTHO= 0.3 TOXE= 0.7 UO=0.0 30

VTHO= 0.4 TOXE= 1.6 U0=0.8

6.238

18.390

15.099

0.846

11.264

31.786

31.281

89.351

157

451

0.120

0.358

0.051

0.153

0.120

0.358

0.051

0.183

0.051

0.153

11.958

17.044

11.325

15.834

15.910

22.471

54.203

76.475

264

389

0.051

0.139

0.120

0.358

0.51

0.153

0.051

0.139

0.051

0.153

7.90

3.604

0.004

29.521

4.719

37.451

34.612

778

393

0.449

0.438

0.304

0.280

2.794

0.438

7.012

0.449

2.794

7.012

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POWER DISSIPAT ION(µW) ION(ma) IOFF(na)

BENCHMARKCIRCUITS

STD DOMINO

POWER DISSIPATION( µW) ION(ma) IOFF(na)

RSSLS

POWER DISSIPATION( µW) ION(ma)

8.109

13.437

0.234

0.227

7.254

12.033

30.259

49.151

284

0.591

0.120

0.358

0.120

0.358

0.12

0.358

0.120

0.358

0.120

0.358

Table19.VOLTAGE VARIATIONS (P AND T CONSTANT): AND2

OR2

RSDLS

RSMRD

POWER DISSIPATION( µW) ION(ma) IOFF(na)

ISSN: 2230-7818

XOR2

D-LATCH

4-BITLFSR

VDD=0. 7

VDD=0. 8

VDD=0 .7

VDD=0. 8

VDD=0. 7

VDD=0. 8

VDD=0. 7

VDD=0. 8

VDD=0. 7

VDD=0. 8

11.878

12.263

0.558

26.48

15.438

18.255

38.655

47.105

361

348

0.250

0.107

0.250

0.107

2.598

6.081

6.824

11.221

0.7

6.97

8.108

26.114

41.306

125

0.107

0.958

0.107

1.337

0.107

1.464

2.431

0.003

1.167

4.329

5.743

14.256

54.152

156

1.337

0.446

1.337

0.171

0.375

0.152

0.176

0.737

0.889

0.942

2.410

2,737

0.120

0.594

IJ A

IOFF(na)

RSMRD

IOFF(na)

0.788

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POWER DISSIPATION (µW) ION(µA) IOFF(nA)

RSSLS

POWER DISSIPATION(µW) ION (µA) IOFF(nA)

RSDLS

POWER DISSIPATION (µW) ION (µA)

OR2

RSMRD

POWER DISSIPATION (µW) ION (µA) IOFF(nA)

ISSN: 2230-7818

XOR2

D-LATCH

4-BITLFSR

127

-73

127

-73

127

-73

127

-73

127

-73

8.550

54.746

20.057

138

16.108

92.667

365

112

184 2

564

0.163

1.193

0.069

0.530

10.166

17.435

9.406

18.880

0.069

1.193

0.655

0.190

0.65 5

0.190

18.206

6.690

58.01 8

17.873

299

114

0.266

0.586

0.266

0.586

0.266

0.586

0.266

0.586

3762

14.136

0.128

0.004

30.618

0.714

16.39 7

1.782

24.4 20

267

0.234

0.320

0.169

0.184

0.234

0.320

1.470

1.193

1.19 3

1.474

196

186

IJ A

IOFF

AND2

STD DOMINO

Table20.TEMPERATURE VARATIONS (P AND V CONSTANT)

BENCHMARKCIRCUITS

9.715

12.585

0.302

0.233

7.392

13.922

28.35 2

63.166

270

504

0.266

0.586

0.266

0.586

0.266

0.586

0.266

0.586

3762

0.26 6 376 2

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PVT Variations for section III: Table21.PROCESS VARIATIONS (V AND T CONSTANT):

BENCHMARKCIRCUIT S

VTHO=0.3 TOXE=0.7 UO=0.030

VTHO=0. 4 TOXE=1.6 U0=0.8

VTHO= 0.3 TOXE=0 .7 UO=0.03 0

VTHO =0.4 TOXE =1.6 U0=0.8

VTHO= 0.3 TOXE=0 .7 UO=0.03 0

VTHO= 0.4 TOXE=1 .6 U0=0.8

0.397

0.369

7.270

1.134

11.292

33.026

126

322

464

1260

0.120

0.358

0.120

0.358

0.120

0.207

0.155

0.120

0.358

25.752

26.708

ION(ma)

0.030

0.099

IOFF(na)

POWER DISSIPAT ION(µW) ION(ma)

POWER DISSIPAT ION(µW)

POWER DISSIPAT ION(µW) ION(ma)

POWER DISSIPAT ION(µW) ION(ma) IOFF(na)

DN1PKP2

POWER DISSIPAT

ISSN: 2230-7818

VTHO =0.4 TOXE= 1.6 U0=0.8

IOFF(na)

DN1P1HV T

4-BITLFSR

VTHO =0.3 TOXE= 0.7 UO=0.0 30

0.358

0.051

0.153

0.051

0.153

41.559

1.167

13.181

38.672

107

303

513

1412

0.120

0.358

0.120

0.358

0.051

0.153

0.051

0.153

40.951

1.182

16.784

43.690

107

303

513

1412

0.120

0.358

0.120

0.358

0.051

0.153

0.051

0.153

0.030

41.359

15.148

16.762

46.690

108

303

485

1350

0.120

0.358

0.120

0.358

0.120

0.358

0.051

0.153

0.051

0.153

23.576

26.875

40.977

1.350

16.823

43.733

107

303

513

1412

0.030

0.099

0.120

0.358

0.120

0.358

0.051

0.153

0.051

0.153

0.042

0.04

0.105

0.104

1.121

2.31

108

303

513

1412

IJ A DN2GD

D-LATCH

VTHO =0.4 TOXE= 1.6 U0=0.8

IOFF(na) DN1HVT

XOR2

VTHO =0.3 TOXE= 0.7 UO=0.0 30

IOFF(na) DDSDG

OR2

DSTDK

AND2

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331 ION(µW) 0.099

0.120

0.358

0.120

0.358

0.051

0.153

0.051

0.153

IOFF(na)

0.038

0.036

0.16

1.167

0.188

1.039

107

303

513

1412

0.120

0.358

0.120

0.358

0.120

0.358

0.051

0.153

0.051

0.153

POWER DISSIPAT ION(µW) ION(ma) IOFF(na)

BENCHMARKCIRCUITS

DSTDK

POWER DISSIPATION(µ W) ION(ma) IOFF(na)

Table 22.VOLTAGE VARIATIONS (P AND T CONSTANT): AND2

OR2

POWER DISSIPATION(µ W) ION(ma) IOFF(na)

DN1HVT

POWER DISSIPATION(µ W) ION(ma) IOFF(na)

DN2GD

POWER DISSIPATION(µ W) ION(ma)

ISSN: 2230-7818

XOR2

VDD=0. 7

VDD=0. 8

VDD= 0.7

VDD=0. 8

0.321

0.160

0.590

1.221

0.267

0.250

0.267

0.250

0.148

0.167

0.267

VDD=0. 7

D-LATCH

4-BITLFSR

VDD=0. 8

VDD=0. 7

VDD=0. 8

VDD=0. 7

VDD=0. 8

17.155

123

159

444

545

0.107

0.665

1.637

3.790

1.882

176

191

728

829

0.250

0.267

0.250

0.107

20.942

11.441

0.837

4.661

22.251

176

191

728

829

0.177

0.065

0.267

0.250

0.107

0.033

46.685

0.898

8.877

16.823

22.963

176

191

730

830

0.267

0.0250

0.267

0.250

0.107

IJ A

DDSDG

0.03

DP11PKP 1

ION(ma)

0.676

4.032

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POWER DISSIPATION(µ W) ION(ma)

21.271

0.006

0.735

0.943

4.799

22.282

176

191

728

829

0.177

0.065

0.267

0.250

0.107

0.048

0.039

0.105

0.091

1.263

1.474

176

191

728

829

0.177

0.065

0.267

0.250

0.107

IOFF(na) DN1PKP2

POWER DISSIPATION(µ W) ION(ma) IOFF(na)

DP11PK P1

POWER DISSIPATION(µ W) ION(ma)

IOFF(na)

BENCHMARKCIRCUITS

0.044

0.128

0.137

82.172

0.803

0.924

176

191

728

829

0.267

0.250

0.267

0.250

0.107

AND2

POWER DISSIPATION(µW) ION (µA) IOFF(nA)

DN1HVT

POWER DISSIPATION (µW) ION (µA)

ISSN: 2230-7818

OR2

XOR2

D-LATCH

4-BITLFSR

-73

127

-73

127

-73

127

-73

127

-73

0.538

0.392

7.027

25.626

16.495

38.504

273

673

658

1515

0.266

0.445

0.266

0.445

0.266

0.190

0.266

0.586

1.82 0

1.996

3762

0.619

0.149

9.725

16.85

21.230

54.302

160

364

758

1677

0.266

0.445

0.266

0.445

0.266

0.190

0.266

0.586

1.82 0

1.996

3762

33.272

0.05

7.742

15.907

22.845

54.347

160

364

758

1677

0.098

0.133

0.266

0.445

0.266

0.190

0.266

0.586

1.82 0

1.996

IJ A POWER DISSIPATION (µW) ION(µA) IOFF(nA)

DDSDG

Table23.TEMPERATURE VARATIONS (P AND V CONSTANT)

127

DSTDK

0.250

DN1P1H VT

IOFF(na)

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 5, Issue No. 2, 319 - 331

DN1P1HV T

POWER DISSIPATION (µW) ION (µA) IOFF(nA) POWER DISSIPATION (µW) ION (µA) IOFF(nA)

DN1PKP2

POWER DISSIPATION(µW) ION(µA) IOFF(nA)

DPKP11P 1

POWER DISSIPATION(µW)

3762

0.030

10.236

68.123

0.137

25.864

23.145

160

364

730

1685

0.266

0.445

0.266

0.445

0.266

0.190

0.266

0.586

1.996

3762

1.82 0 0

33.269

76.778

7.850

16.035

22.878

54.378

160

364

758

1677

0.098

0.133

0.266

0.445

0.266

0.190

0.266

0.586

1.82 0

1.996

3762

0.049

0.058

0.111

0.04

16.02

1.876

160

364

756

1677

0.098

0.133

0.266

0.445

0.266

0.190

0.266

0.586

1.82 0

1.996

3762

0.045

ION(µA)

0.266

IOFF(nA)

3762

0.157

0.171

0.445

0.266

0.445

3762

V. CONCLUSIONS

IJ A

This work consists of four different parts. In section II, the circuits Dynamic DCVSL footed circuit, Dynamic DCVSL footless circuit; Dual-Rail Data-Driven Dynamic Logic and Dual-rail Footless domino gate with self-timed precharge scheme are successfully implemented using CMOS domino logic. The proposed circuits have offered an improved performance in power dissipation, speed and noise tolerance when compared with standard domino circuit. In section III, an attempt has been made to simulate the benchmark circuits AND2, OR2, XOR2, 16-bit full adder, 16bit comparator, D-flip-flop, 4-bit LFSR by the three reduced swing domino logic circuits. The proposed circuits have offered an improved performance in power dissipation, speed and noise tolerance when compared with standard domino circuit. As it is observed from the results, of all the three reduced swing circuits, reduced swing domino with dual supply has low power dissipation, PDP and more tolerance to noise. In section IV, the circuit techniques employing dual thresholds, dual voltages, and dual grounds are presented for simultaneously reducing power dissipation and delay in

ISSN: 2230-7818

0.164

DN2GD

1.124

1.174

160

364

75 8

167 9

0.266

0.190

0.26 6

0.586

1. 82 0

1.99 6

3762

IOFF

domino circuits and also to increase the noise immunity. The benchmark circuits AND2, OR2, XOR2, 16-bit full adder, 16bit comparator, D-flip-flop, 4-bit LFSR are simulated with the proposed different energy efficient domino logic circuit techniques in 65nm technology. From the results, it is observed that the proposed logic technique which is dual threshold, dual ground and dual supply voltage with N2 high threshold shows good performance when compared to single threshold (vt) domino logic techniques. Hence, it is concluded that the proposed designs will provide a platform for designing high performance and low power digital circuits and high noise immune digital circuits such as, processors and multipliers. In section V, an attempt has been made to study the effect of the PVT variations on the domino circuits with different techniques given in sections II, III, IV. As it is observed from the results, when process variations decrease power dissipation increases, and vice versa. When temperature variations increase, power dissipation increases and vice versa. When voltage variations decrease power dissipation decreases.

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[1] [2] [3] [4]

[5]

[6]

L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, “Cascode voltage switch logic: A differential CMOS logic family,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 16-17, 1984. P. Ng, P. T. Balsara, and D. Steiss, “Performance of CMOS Differential Circuits,” IEEE J. of Solid-State Circuits, vol. 31, no. 6, pp. 841-846, June 1996. P. Hofstee, et al., “A 1 GHz Single-Issue 64b PowerPC Processor,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 9293, 2000. J. Wang, S. Shieh, C. Yeh, and Y. Yeh, “Pseudo-Footless CMOS Domino Logic Circuits for High-Performance VLSI Designs,” in Proc. Int. Symp. on Circuits and Systems, vol. 2, pp. 401-404, 2004. R. Rafati, A. Z. Charaki, G. R. Chaji, S. M. Fakhraie, and K. C. Smith, “Comparison of a 17b Multiplier in Dual-Rail Domino and 3 4 in Dual-Rail D L (D L) Logic Styles,” in Proc. Int. Symp. on Circuits and Systems, vol. 3, pp. 257-260, 2002. S. Mutoh et al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol.30, pp. 847–854, Aug. 1995.

AUTHORS BIODATA:

[7] V. Kursun and E. G. Friedman, “Domino logic with dynamic body biasedkeeper,” in Proc. Eur. Solid-State Circuits Conf., Sept. 2002, pp.675–678. [8] “Variable threshold voltage keeper for contention reduction in dynamic circuits,” in Proc. IEEE Int. ASIC/SOC Conf., Sept. 2002, pp.314–318. [9] S. Borkar, .Low Power Design Challenges for the Decade,. Proceedings of the IEEE/ACM Design Automation Conference, pp. 293-296, June 2001. [10] P. Srivastava, A. Pua, and L. Welch, .Issues in the Design of

IJ A

1 Salendra.Govindarajulu:- He is working as an Associate Professor in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal, Andhra Pradesh, India. He presented more than 25 International/National Technical Papers. He is a Life Member of ISTE, New Delhi. He is a member of IAENG. His interest includes Low Power VLSI CMOS design.

ISSN: 2230-7818

Domino Logic Circuits, Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 108-112, February 1998. [11] G. Balamurugan and N. R. Shanbhag, .Energy-efficient Dynamic Circuit Design in the Presence of Crosstalk Noise,. Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 24-29, August 1999. [12]. S.Govindarajulu, Dr.T.Jayachandra Prasad “Design of High Performance Dynamic CMOS Circuits in Deep submicron Technology” International Journal of Engineering Science and Technology, Vol.2 (7), 2010, pp.2903-2917, ISSN:0975-5462 [13]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Low Power, Reduced Dynamic Voltage Swing Domino Logic Circuits” Indian Journal of Computer Science and Engineering, 2010 pp.74-81, ISSN:0976-5166. [14]. S.Govindarajulu, Dr.T.Jayachandra Prasad “Energy efficient Reduced Swing Domino Logic Circuits in 65 nm Technology” International Journal of Engineering Science and Technology, Vol.2 (6), 2010, pp.2248-2257, ISSN:0975-5462. [15]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Design of High Performance Arithmetic and Logic Circuits in DSM Technology”International Journal of Engineering and Technology, Vol.2 (4), 2010, pp.285-291, ISSN:0975-4024. [16]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “High Performance VLSI Design Using Body Biasing in Domino Logic Circuits” International Journal of Computer Science and Engineering, Vol.2, No.5, 2010 pp.1741-1745, ISSN:09753397. [17]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Design of Low Power, High Speed, Dual Threshold Voltage CMOS Domino Logic Circuits with PVT Variations” International Journal of Electronic and Engineering Research, Vol.2, No.5, 2010 pp.619- 629, ISSN:0975-6450.

REFERENCES

2 Dr.T.Jayachandra Prasad:- He is working as a Principal and Professor in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal Andhra Pradesh, India. He presented more than 50 International/National Technical Papers. He is Life Member in IE (I), CALCUTTA, Life Member in ISTE, NEW DELHI, Life Member in NAFEN, NEW DELHI, and IEEE Member. His interest includes Digital Signal Processing.

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ISSN: 2230-7818

Page 337