B0150810

Invention Journal of Research Technology in Engineering & Management (IJRTEM) ISSN: 2455-3689 www.ijrtem.com Volume 1 Issue 5 Ç July. 2016 Ç PP 08-10

SCR-Based ESD Protection Designs for RF ICs Chun-Yu Lin Department of Electrical Engineering, National Taiwan Normal University, Taipei, Taiwan

Abstract: CMOS technology has been used to implement the radio-frequency integrated circuits (RF ICs). However, it was known that advanced CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of ICs. Therefore, on-chip ESD protection devices must be added into the chip, including RF ICs. To minimize the impacts from ESD protection devices on RF performances, the ESD protection at RF pads must be carefully designed. A review on ESD protection designs with silicon-controlled rectifier (SCR) devices in RF ICs is presented in this article.

Keywords: CMOS, ESD, RF, SCR. I. Introduction All integrated circuits (ICs), including radio-frequency (RF) ICs, must meet the reliability specifications during mass production.

Electrostatic discharge (ESD), which is one of the most important reliability issues during mass production, must be taken into consideration [1]. All integrated circuits used in the wireless communication products need to be equipped with ESD protection designs.

However, ESD protections cause RF performance degradation with several undesired effects. Parasitic capacitance is one of the most important design considerations for RF ICs. A typical specification for a giga-Hertz RF circuit on human-body-model (HBM) ESD robustness and the maximum parasitic capacitance of ESD protection device are 2kV and 200fF, respectively [2], [3]. As the operating frequencies of RF circuits increase, the parasitic capacitance is more strictly limited.

The ESD protection devices used in commercial CMOS processes include the diode, MOS, BJT, field-oxide device, and silicon-controlled rectifier (SCR). Among the ESD protection devices, the SCR device has been reported to be useful for RF ESD protection design due to its higher ESD robustness within a smaller layout area and lower parasitic capacitance [4]. In this paper, the SCR-based ESD protection designs for 30GHz and 60GHz applications are reviewed.

II. SCR Device The device structure of the SCR device used in RF input (RFIN) pad is illustrated in Fig. 1(a). The SCR path between RFIN and VSS consists of P+, N-well, P-well, and N+. The equivalent circuit of the SCR consists of a PNP BJT (QPNP) and a NPN BJT (QNPN), as shown in Fig. 1(b). As ESD zapping from RFIN to VSS, the positive-feedback regenerative mechanism of QPNP and QNPN results in the SCR device highly conductive to make SCR very robust against ESD stresses. However, SCR has some drawbacks, such as higher trigger voltage and slower turn-on speed. To reduce the trigger voltage of an SCR device, the trigger signal can be sent into the base terminal of QNPN to enhance the turn-on speed [5].

(a)

(b)

Fig. 1. (a) Device cross-sectional view, and (b) equivalent circuit, of SCR device used in RF input pad.

III. SCR-Based ESD Protection Design for 30GHz Applications An inductor-assisted SCR (LASCR) has been presented for 30GHz applications. Fig. 2 shows the design of LASCR, which consists of an SCR, an inductor (L), and a diode string (Dtrig) [6]. The diode string is used to enhance the turn-on efficiency of SCR [7]. As ESD zapping from RFIN to VSS, the inductor and diode string will discharge the initial ESD current, and then the SCR will be triggered on to discharge the primary ESD current. Under normal RF operating condition, the inductor will resonate with the parasitic capacitance of

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SCR-Based ESD Protection Designs‌ SCR, and the signal loss of LASCR can be very small. Fig. 3 shows the simulated signal loss (S21) of LASCR. At 30GHz, the LASCR has only 0.4dB loss.

Fig. 2. SCR-based ESD protection design for 30GHz applications.

Fig. 3. Simulation results of SCR-based ESD protection design for 30GHz applications.

IV. SCR-Based ESD Protection Design for 60GHz Applications An inductor-triggered SCR (LTSCR) has been presented for 60GHz applications. Fig. 4 shows the design of LTSCR, which consists of an SCR device, an inductor (Ltrig), a MOS transistor (Mtrig), and an RC-inverter ESD detection circuit [8]. In this ESD protection scheme, the dimensions of the inductor, PMOS transistor, SCR device, and diode can be designed to minimize the RF performance degradation.

The inductor is also used to provide the trigger path between the RFIN pad and the base of QNPN under ESD stress conditions. The PMOS transistor at the trigger path, which is controlled by the RC-inverter ESD detection circuit, is also turned on under ESD stress conditions.

The Mtrig is turned off to block the steady leakage current path from the RFIN pad to the base of QNPN under normal RF circuit operating conditions. The simulated signal loss of this circuit is shown in Fig. 5. At 60 GHz, the LTSCR has only 0.9dB loss.

Fig. 4. SCR-based ESD protection design for 60GHz applications.

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SCR-Based ESD Protection Designs‌

Fig. 5. Simulation results of SCR-based ESD protection design for 60GHz applications.

V. Conclusion A comprehensive review in the field of ESD protection designs with SCR-based devices for RF ICs is presented. These designs provide the design guideline for on-chip ESD protection for RF circuits. The on-chip ESD protection designs for RF circuits will continuously be an important design task, as the operating frequencies of RF circuits increase.

Acknowledgements This work was supported by Ministry of Science and Technology, Taiwan (grant 105-2622-E-003-001-CC2).

References 1. S. Voldman, ESD: RF Technology and Circuits (John Wiley & Sons, 2006).

2. D. Linten et al., A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS, IEEE Journal of Solid-State Circuits, 40(7), 2005, 1434-1442.

3. C. Richier et al., Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 Îźm CMOS process, Journal of Electrostatics, 54(1), 2002, 55-71.

4. M.-D. Ker and C.-Y. Lin, Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs, IEEE Trans. on Microwave Theory and Techniques, 56(5), 2008, 1286-1294.

5. M.-D. Ker and K.-C. Hsu, Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits, IEEE Trans. on Device and Materials Reliability, 5(2), 2005, 235-249.

6. C.-Y. Lin and R.-K. Chang, Design of ESD protection device for K/Ka-band applications in nanoscale CMOS process, IEEE Trans. on Electron Devices, 62(9), 2015, 2824-2829.

7. S. Jang, L. Lin, S. Li, and H. Chen, Dynamic triggering characteristics of SCR-type electrostatic discharge protection circuits, Solid-State Electronics, 45(7), 2001, 1091-1097.

8. C.-Y. Lin, L.-W. Chu, and M.-D. Ker, ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process, IEEE Trans. on Microwave Theory and Techniques, 60(3), 2012, 714-723.

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