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From One Side to Another How Backside Defects Can Wreak Havoc on IC Features Laura Pressley, Ph.D., Shirley Hardin, Jeremy Bolf, Travis Kirsch, John Darilek, Mike Allen, Brian Dunham, Buster Klingemann, Teresa Mathews, Carolyn Cariss, Eric Apelgren, Dan Sutton, Kevin Harper, Laurence Kohler, Ph.D., Chris Lansford, Terri Couteau, Bryon Hance, Fab 25, Spansion LLC Rhonda Stanley, Joyce Witowski, Lisa Cheung, KLA-Tencor Corporation

This article examines the impact that backside defects can have on the frontside of wafers and, ultimately, on device performance. For example, in this study, a detailed front-end-of-line (FEOL) frontside and backside defect partition showed that several defect mechanisms were operating in the FEOL, and identiﬁed a previously unknown backside defect mechanism that was affecting every incoming silicon wafer from several silicon substrate suppliers. An evaluation of backside defect data enabled the silicon suppliers to identify the root cause.

Introduction

A key challenge for semiconductor devices patterned at 110, 90, 65 nm and below are backside defect transfer mechanisms that occur in batch processing equipment in which the frontside, device performance portion of the wafer is directly exposed to the backside of wafers during processing. Several studies of backside defectivity have been previously reported in the literature.1-10 The majority of processing equipment for IC devices utilizes single wafer processing for etch, photolithography, CVD, PECVD, and polish operations. Yet, diffusion and wet clean processes are typically performed in batches and are susceptible to defect transfer between wafers during processing. Several IC equipment suppliers have anticipated these defect transfer-related issues and have developed new methods to minimize these transfer mechanisms. For example, several IC wet clean equipment suppliers have developed immersion tools that orient wafers with the frontsides facing each other (face-to-face processing), which allows the

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wafer backsides to not be directly exposed to the IC features. Going one step further, single wafer wet clean sinks have also been developed in recent years, and single wafer cleans are progressively being introduced in the FEOL cleans by various IC manufacturers. In FEOL diffusion furnace processes, wafers are typically positioned in parallel above each other with the frontsides of wafers underneath the less characterized and typically more defective backsides of wafers. This type of diffusion furnace batch processing is susceptible to backside defects and the incidence of film flaking onto the frontside of the wafers positioned below. These mechanisms may be the result of film stress, thermal expansion/contraction, and/or lattice mismatch issues that occur during diffusion processing. Therefore, it is important to understand and characterize the backside defectivity in the FEOL batch processes to determine if these processes contribute to die yield losses. In this paper, FEOL diffusion backside defectivity characterization methods are discussed, including the chemical identification of these defects, the correlation of various backside defect signatures to a root cause, the transfer to the frontside of wafers during FEOL diffusion processes, and the possible impact to device sort yields.

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Experimental methods

Several sets of Flash memory production lots and bare Si test wafers were utilized in this study. To minimize background noise levels for defect detection, we used Si substrate material with low levels of crystal oriented pits (COPs) and double sided polished (DSP) Si for increased defect sensitivity for backside defects. Frontside and backside defects were characterized with various surface analytical techniques such as scanning electron microscopy (SEM) and energy-dispersive X-ray ﬂuorescence analysis (EDX) using Applied Materials’ SEMVision and the JEOL SEM. The equipment for backside defect metrology included KLA-Tencor SP1-BSIM and the Applied Materials SEMVision. The Applied Materials Compass and SEMVision and the KLA-Tencor AIT tools were utilized for frontside defect quantiﬁcations. Results

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This systematic, step-wise correlation from end-of-line sort yield back to frontside inline defectivity data shows that the same defect type found at end-of-line strip back was previously detected inline at several locations such as Poly 2 and the origin of the defect source is the Poly 1 module. Extensive defect partitions and investigations proved the majority of these embedded defect types were first detected in the Poly 1 process module. For the various processes and equipment tool sets that comprised the Poly 1 module, we collected frontside overlay defect maps for test wafers used for the various defect qualifications and found a similar spatial defect signature as in Figure 1 above. As Figure 2 shows, the overlay defect maps for the bare Si test wafers (particle qualification tests) for furnace film (Y) had the best spatial match to Figure 1 (c). The overlay defect maps from other furnace films used in the Poly 1 area of the line did not show a strong spatial correlation. Therefore, �� that furnace film �� (Y) was the major �� defect we suspected contributor causing the die yield edge loss.

Correlating Yield Losses to FEOL Furnaces

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Figure 1. Overlay of wafer maps showing the correlation of edge die losses with frontside inline defect spatial signature and SEM of those defects at a) end-of-line die yield, b) frontside inline defect maps of FEOL at 2nd Poly Gate, and c) frontside inline defect maps of FEOL at 1st Poly Gate.

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Figure 2. Frontside defect overlay wafer maps of bare Si test wafers for furnace defect qualiﬁcations showing the inline spatial signature for furnace ﬁlm (X), (Y), and (Z), respectively.

A scatter plot of the frontside inline production wafer defect levels vs. the furnace process (Y) test wafer qualiﬁcation defect values showed a strong correlation for furnace test wafers that are placed under production material �� in a furnace load (see Figure 3). There was no �� correlation of inline defectivity with the defect levels of bare Si test wafers placed under other bare Si test wafers. The strongest defect correlation existed for bare Si test wafers that were placed under standard, full ﬂow production wafers. Therefore, a backside transfer �� mechanism was possibly operating and causing the edge defectivity and subsequent die yield losses. ��

Improving IC wafer edge die yield is a key focus for all manufacturing facilities. Characterization of process signatures and defect types that are responsible for yield losses on the edges of wafers is important in determining the major contributors. Correlating the yield and end-of-line loss signatures with inline defect data and defect types is key in identifying the exact processes causing the yield losses. Figure 1 below is an example of such a correlation. An overlay of numerous end-of-line die yield maps and end-of-line stripback data allowed us to identify similar FEOL inline defect spatial signatures and types, as well as their origins.

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�� Figure 3. Normalized scatter plot of defect values for the test wafers from furnace ﬁlm (Y) placed under production wafers vs. inline production defect data after

Figure 5. Schematic diagram of a vertical diffusion furnace with frontside and

deposition in furnace ﬁlm (Y).

backside wafer maps showing examples of backside defects that have translated

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Figure 4. Wafer spatial correlation of (a) die yield losses at end-of-line, with (b) frontside inline production defect measurements post diffusion processing, and (c) furnace tool qualiﬁcation frontside defect data.

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Testing Backside Defect Transfer Mechanism Theory for Furnace Film (Y)

It has been previously shown that backside defect transfer mechanisms can operate in vertical diffusion processes. Below is a schematic diagram showing the loading sequence and backside defect transfer that can occur in a vertical�� diffusion furnace [from a 200 mm microprocessor fab and KLA-Tencor case study].

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a similar spatial defect pattern onto the frontsides of wafers positioned below them.

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To show a backside defect transfer mechanism occurring during the deposition of furnace film (Y), we evaluated and quantified the frontside defectivity of test wafers oriented below a) new bare Si test wafers, vs b) full flow��production material in the Poly 1 module for the furnace film (Y). As shown in Figure 6, for the bare test wafers placed under other bare Si test wafers, the frontside defect levels were significantly lower than those bare Si test � wafers that were oriented below the standard full �� flow production wafers processed for furnace film �� (Y). In �� addition, the defect overlay wafer maps showed that �� the bare Si test wafers under the production material had a predominant edge signature similar to Figure 4. Frontside overlay defect maps for each group of wafers in Figure 6a (under bare test wafers) and 6b (under full flow production wafers) show the respective frontside defect spatial signature for each test. To further prove that a backside defect transfer mechanism was operating during the processing of furnace film �� (Y), we also evaluated and quantified the frontside defectivity of full flow production wafers oriented below Figure 6a (bare Si test wafers) vs. Figure 6b (full flow production material for the furnace film (Y)). As�� shown in Figure 7, for the test wafers placed under other test wafers, the defect levels were significantly lower than the test wafers that were oriented below the standard full flow production wafers processed with furnace ��film (Y). In addition, the frontside defect overlay

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Based on the data above, we have shown that using endof-line wafer spatial yield loss patterns in conjunction with inline production and tool qualiﬁcation frontside �� is an effective method �� speciﬁc defect data for identifying process operations contributing to the yield losses. This is shown in Figure 4.

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wafer maps showed the production wafers inserted under the production material had the edge signature similar to Figure 4 above and those under bare Si test wafers did not show the predominant edge signature.

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Figure 6. Normalized overlay wafer maps for bare Si �� frontside defect levels and�� test wafers (FMs) placed under (a) bare Si test wafers (FMs), and for bare Si test wafers placed under (b) full ﬂow production wafers for furnace ﬁlm (Y).

Production wafers under production wafers show an edge-centric defect signature similar to the bare Si test wafer signature under full ﬂow production wafers in Figure 6 and similar to the frontside defect signature in Figure 4. Furthermore, the spatial signatures are similar to the edge yield loss patterns of Figure 1a, 1b, and 1c.

Partitioning Defects on the Backside of Production Wafers

Using the KLA-Tencor SP1-BSIM tool, we characterized the defect signatures of the backside of production wafers incoming to and after deposition of furnace ﬁlm (Y). Note, no comparison of other backside scan tools were made in this study. To enhance the signal-to-noise for the backside scans, we utilized double sided polished (DSP) Si starting material for characterizations of backside defects. Figure 8 below shows backside defect levels pre-FEOL processing, as well as the same wafer post FEOL post-processing up to and including STI, implants, and the Poly 1 module and deposition of furnace ﬁlm (Y).

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Figure 8. KLA-Tencor SP1-BSIM backside scan of a double sided polished wafer (a) before FEOL processing and the same wafer (b) after processing in the FEOL up to and including the furnace ﬁlm (Y) processing.

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Figure 7. Normalized JMP graph for frontside defect levels and representative frontside wafer maps for full flow production wafers placed under (a) bare Si test wafers and under (b) full flow wafers during the deposition of furnace film (Y).

Note the three-fold clustered, dense set of defects around the edge of the backside wafer map in Figure 8a. This three-fold symmetry pattern remains �� after multiple FEOL processing steps and modules in the FEOL. Also, numerous backside defect signatures are apparent on the wafer map in Figure 8b. The interesting defects from an edge yield perspective are the backside defects located around the perimeter of the wafer in Figure 8b. Our goal is the elimination of all FEOL backside defect Fall 2005

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mechanisms to prevent backside defect transfers in various batch process tools such as clean sinks and vertical diffusion furnaces. Several of the defect signatures we observed on the wafer map in Figure 8b are understood as having ongoing FEOL defect reduction projects. Yet, the three-fold symmetry pattern detected on the starting Si wafer map in Figure 8a was a new defect mechanism, of which we had previously been unaware.

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Therefore, we partitioned the FEOL for the source of these large defects. SEM inspection of the three-fold backside edge defects post Poly 1 furnace processing shows multiple, greater than 100 µm in length scratching patterns. Representative SEMs of the scratch defects �� are shown in Figure 9 below.

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Figure 10. KLA-Tencor SP1-BSIM backside scan and SEM images of the backside roughness and scratches of production wafers prior to processing. Supplier (a) did not have the three-fold scratches, whereas (b) and (c) both showed the �� three-fold symmetry �� scratch defects.

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Figure 9. Representative backside SEM images taken of the three-fold symmetry gouge/scratch defects on a production wafer.

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We partitioned these three-fold defects at 10 sequential locations in the FEOL from the furnace ﬁlm (Y) process, in the Poly 1 module, back to the beginning of processing in the FEOL. We found that these scratches occurred prior to processing in our IC manufacturing facility. Using the KLA-Tencor SP1-BSIM tool, we inspected�� and characterized the backsides of wafers from each of our silicon suppliers. The inspection revealed that two Si vendors were producing these severe scratch defects ��to our fab. Figure 10 on every Si wafer they supplied �� shows the three-fold defect spatial signature of��these gouges and low-resolution backside SEM images of wafers from multiple Si vendors. SEM and EDX elemental characterization of the scratch defects were performed and some defects were found embedded in the scratched locations. These were comprised of Si and C as shown in Figure 11. Figure 12 shows a backside �� defect wafer map overlay of 25 wafers of a lot prior to processing. It indicates random rotational orientations of the three-fold symmetry patterns on the wafers. Please disregard the wafer handling patterns in the center of the overlay wafer map. �� 28

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Figure 11. EDX spectra of backside embedded defects in the three-fold scratch patterns on production wafers.

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Figure 12. Backside defect wafer overlay map of 25 wafers prior to FEOL processing. We relayed the new defect information to our various Si suppliers and, based on the data, the backside three-fold symmetry pattern matched exactly with a marginal furnace anneal and SiC boat conﬁguration being used in the preparation of the Si wafers. The SiC EDX spectra identiﬁed the supplier boat material causing the scratches; the three-fold spatial locations matched the supplier’s furnace boat rail orientations, and the random rotation of the three-fold symmetry scratches matched up with the fact that the suppliers were not notch aligning prior to the marginal furnace anneal process.

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Degradation of Backside Scratch Defects During FEOL Processing

Figure 13 shows the effects that FEOL processing, in high temperature diffusion pre cleans and furnace processes in the poly 1 loop, can have on scratch type defects that originate on the backside of Si wafers at lot start. As shown in the SEM images, subsequent FEOL processing �� and temperature cycles can degrade the defect locations and cause scratch defects to crack, propagate, and produce particles that may be transferred to the wafer frontside in batch type �� processes or even cause �� subsequent photolithography patterning issues. These SEM images were collected on separate wafers that had received a BSIM pre-scan at lot �� start. To collect the data, we re-reviewed the same �� scratch defects after various diffusion clean/furnace processing in the poly 1 loop. Because a non-destructive review tool or methodology to collect �� true defect propagation data on the same wafers �� after multiple processing �� steps does not exist, we ﬂipped each wafer upside down on the SEM tool and removed them from subsequent processing �� because the patterned side of the wafers were severely damaged by the �� SEM chucks.

Figure 13. Backside SEM images of

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scratch defect degradation due to FEOL diffusion pre clean and furnace processing.

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Conclusions and future actions

Detailed FEOL characterizations revealed a previously unknown, Si supplier-generated backside defect mechanism. According to the various suppliers, no other IC manufacturer had brought this to their attention. Subsequently, each supplier now has corrective actions in place to reduce and eliminate these backside scratches and defects. Based on the data from this study, our manufacturing facility plans to monitor backside defectivity levels for starting Si material due to the defect transfer effects these large, gouge/scratch type defects can have in our various single wafer and batch processes. As IC manufacturers progress into 110, 90, and 65 nm technology nodes, large backside defects will cause lithography edge focus marginalities; polish, etch, and ﬁlm chucking; and edge process uniformity issues. Our plan is to continuously monitor these backside defects on incoming Si production material nondestructively with our backside scan tool. For future backside defect characterizations, a non-destructive method of SEM review of backside defects is a critical requirement. It is essential to be able to collect nondestructive, in-situ SEM and EDX characterizations for backside defects and contamination so that root causes can be identiﬁed inline and corrective actions can be quickly implemented to reduce defectivity and increase semiconductor die yields. Acknowledgements

The authors would like to thank the Spansion Fab25 CFM organization and Mike Brooks, Director of Yield Management, of Spansion, LLC for supporting these extensive characterizations. References 1. F. Kroninger, N. Streckfuss, L. Frey, T. Falter, C. Ryzlewicz, L. Pﬁtzner, and H. Ryssel, “Application of advanced contamination analysis for qualiﬁcation of wafer handling systems and chucks,” Appl. Surface Sci., vol. 63, no. 1-4, pp. 93-8, January 1993. 2. R. Miura, H. Ishigaki, and Y Matsunaga, “Backside particle reduction on PI9500 series ion implanter,” in Proc. of the Eleventh Int. Conf. on Ion Implantation Tech., June 1996, pp. 174-7. 3. F. Beaudoin, M. Meunier, M. Simard-Normandin, and D. Landheer, “Excimer laser cleaning of Si wafer backside metallic particles,” J. Vac. Sci. Technol. A, vol. 16, no. 3, pp 1976-9, May-June 1998. Fall 2005

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4. W. Frutiger, R. Eddy, D.A. Brown, and M.E. Mack, Production proven electrostatic platen for medium current implantation,” in Proc. of the Eleventh Int. Conf. on Ion Implantation Tech., June 1996, pp. 346-9.

8. Kay Lederer, Matthias Sholze, Ulrich Strohback, Andreas Wocko, Thomas Reuter, Angela Schoenauer, “Wafer Backside Inspection Applications in Lithography,” Advanced Semiconductor Manufacturing 2003 IEEE Conference Workshop, 31 Mar – 1 Apr, 2003, p. 1-8.

5. Krishnamachar Prasad, “Optoelectronic and Microelctronic Materials and Devices”, 2000 COMMAD Proceedings Conference, 6-8 Dec 2000, p. 25-28.

9. Christopher Maleville, Lisa Cheung, Dieter Mueller, “Fabricating and Inspecting Ultathin Silicon-On-Insulator Wafers”, Micro Magazine.com, 1997.

6. Lesley A Cheema, Leonard J. Olmer, Oliver D. Patterson, Susan S. Lopez, Mark B. Burns, “Wafer Backside Inspection Applications for Yield Protections and Enhancement”, Advanced Semiconductor Manufacturing 2004 IEEE Conference Workshop, 30 Apr – 2 May, 2004.

10. Kazuyuki Hozawa, Hiroshi Muyazaki, Jiro Yagami, “True Inﬂuence of Wafer-Backside Copper Contamination During the Back-End Process of Device Characteristics,” Electron Devices Meeting, 2002, IEDM ’02 Digest International 8-11 Dec, 2002.

7. Patrick Taylor, Thuy Pham, Charley Wang, “Applications for Automated Wafer Backside Inspection,” Advanced Semiconductor Manufacturing 2004 IEEE Conference Workshop, 4-6 May, 2004.

This article is based on a paper that was originally presented at ASMC 2005.

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