D E F E C T M A N A G E M E N T Copper Interconnects
Cycling Your Way to Faster Development and Integration at the BEOL Accelerating Copper Interconnect Development
Judy Shaw, Richard L. Guldi, Tae Kim, Dan Corum, and Jeffrey Ritchison, Texas Instruments Steve Oestreich, Jason Lin, Kurt Weiner, Kara Davis, and Robert Fiordalice, KLA-Tencor Corporation
Development and integration learning cycles of a 130 nm advanced logic device were accelerated using area-accelerated e-beam inspection. The devices used in this study employed a low-κ dielectric (κ<3.0), a silicon carbide (SiC) etch-stop scheme, and several levels of copper interconnect.
Introduction
With the introduction of copper interconnects at 180 nm, and the subsequent blending of low-κ interlevel dielectrics (ILD) at 130 nm, interconnect modules continue to represent the biggest challenge for achieving fast ramps and high yields of the most advanced logic devices. Moreover, technology introduction cycles of 18 months, or less, require that technology ramps be efficient and that the limited number of cycles of learning be used effectively. Leading edge microprocessor technologies at the 100 nm node will utilize eight or more levels of back-end-of-line (BEOL) interconnect, making up over 70 percent of the device processing. So, rapid BEOL process development and integration are key to a timely ramp from the development to pilot production stages. Rapid development requires that problems be identified and isolated quickly. Once the issue is identified, process and integration splits that target the root cause can be identified. The key is providing the yield and integration teams with tools that can help them identify the source of the issue quickly. At the same time, it’s important to
quantify the impact in terms of both parametric performance and yield. If the root cause can be properly quantified, the process and integration engineering teams can be confident they are working on the best solution. In addition, proper quantification of the issue provides the basis for the identification of critical metrics. Through the monitoring of these metrics, progress toward the elimination of the issue can be tracked. Two-component strategy
The strategy is comprised of two components, electron beam inspection and advanced test chip design. The merging of these two components is called eDo.1 The fundamental concept of the eDo technology is the use of an automated e-beam defect inspection tool and data filtering techniques to isolate only electrical defects, while at the same time using smart test chip design to maximize wafer throughput. The isolation of the electrical defects from the many physical and nuisance defects is critical to accelerating yield learning. This is done using voltage contrast (VC) methodology. Contrast imaging is used to differentiate floating and grounded structures. In addition to using VC filtering, smart test chip designs are utilized to dramatically improve the relative throughput of the inspection allowing for what can be Spring 2003
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Assess and ID Scan Assess Scan
ID Scan
FIB Analysis
processing time requirements may be lengthy. In contrast, eDo requires only back-end interconnect structures. Case study 1
The first experiment focused on post-ECD (electrochemical deposition) anneals. It is well known that the post-ECD anneal is a critical component of the copper interconnect process development. Performing an anneal induces copper grain growth and releases stress. eDo was used to help quickly define a thermal budget, which provided for high-yielding via chains. Figure 2 is a histogram showing total electrical defect counts in the eDo test structures after a post-copper CMP (chemical mechanical polishing) for two different ECD anneal conditions. Figure 1. On the left is a typical via chain failure as detected by the assess scan in eD o . The Electrically probable test structures ID scan confirms the exact (x,y) location of the defect for FIB analysis. confirmed that the defect types were electrical in nature, and a sharp called “area acceleration.” The inspection methodology distinction could be discerned between the two anneal is comprised of two separate e-beam scans of the test conditions. Figure 3 is a cumulative probability plot chip structure. The first scan, called the assessment showing the via chain results. Inset in the figure is a (assess) scan, inspects only a very small potion of the via FIB (focused ion beam) image collected from failure chain (typically eight percent), and provides an overall analysis. The total inspection and review took less than defect assessment with regards to the test structure. 90 minutes per wafer and, because the ID scan provides the exact defect locations, the FIB analysis took less The data collected in the assess scan is used to program than 45 minutes. Conventional defect inspection and the sites to be scanned in the second scan, which is sourcing methods typically take much longer than this. called the identification (ID) scan. It is in the ID scan that the precise x-y location of the physical source of an electrical defect is determined. This data is then ported to a SEM review tool. An example of how assess and ID scans are used to isolate electrical defects is shown in Figure 1. In summary, eDo provides: 1) Voltage contrast identification and filtering to identify electrical defects, 2) High relative scan rates through area acceleration, and 3) Exact locations of physical sources to electrical defects. The focus of this work is to use eDo to help drive process development and process integration. The ability to precisely locate the defect site quickly is an advantage over short loop development, which requires both in-line probe, and at times, extensive failure analysis. While SRAM bit-map analysis can provide precise defect locations, the device must be an electrically addressable full-flow design and the associated 32
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Figure 2. Histogram of “electrical” defect counts from e-beam inspection, comparing two ECD anneal splits.
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Sub-surface Via Void Detection
clear that the eD0 defect density values trend higher than those calculated for the probed structures for the higher numbered wafers. The discrepancy can be understood upon closer examination of the differences between the two structures.
Defects/cm
2
The electrically probed via chains used in this study were 546K vias in length. While eD0 via chain segments were 415K vias in length, more granularity is achieved with Figure 3. On the left is the cumulative distribution plot from the conventional via chain, which confirms the the addition of 70 percent high defect density, captured in the eD 0 scans. more via chains in each die. It is possible to achieve a much Case study 2 higher via chain density per unit area with the eD0 This second experiment was designed to examine the structure due to the fact that bond pads are not correlation between the defect densities reported by required. This results in a higher and more accurate eDo and those obtained with conventional inline probe estimation of the true detect density. results. Conventionally-tested via chains were printed and processed in close proximity to the eD0 via chains. In addition to the added granularity, this evaluation True electrical defect density (D0) for the probe test uncovered a new defect type, which was named “resistive structures was calculated using Poisson’s equation, vias.” It resulted in an even higher defect density as Y = e-AD0. The calculated D0 value in the eD0 structures calculated using eD0. Resistive vias are defined as single was calculated from the same equation. Figure 4 is a or multiple vias, which when electrically probed are not graph comparing the D0 from the probed and eD0 test of high enough resistance to cause an electrical limit structures for 13 wafers from various lots. failure, and are thus not captured as failures with conventional inline electrical probe. While there is certainly some correlation between the conventional probe and eDo results for wafers 1-6, it is These resistive vias image “gray” in the e-beam voltage contrast mode. The inset in Figure 4 is an example of a resistive via which imaged gray in VC mode and was captured by the eD0 strategy, but not by inline probe. 14.00 One of the primary advantages of eD0 is in the detection eD0 12.00 of single and multiple resistive via defects in a single 10.00 via chain. This enhances the accuracy of the eD0 as compared to electrical probe results. 8.00 Inline Probe Data
6.00 4.00 2.00 0.00 1
4
8
12
Wafer ID Figure 4. Comparison of via chain defect densities calculated from conventional and eD 0 via chain test structures.
The insertion of multiple bond pads could be utilized to closer approximate true defect density on conventional electrical structures. However, the “tapping” of large via chains to gain granularity requires large amounts of area due to the number of bond pads required, as well as a more complicated electrical probing scheme. In contrast, bond pads are not required for the eD0 methodology resulting in a more efficient utilization of silicon for test structure design.
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Conclusion
An advanced yield methodology, eD0, has been employed to significantly reduce the development cycle time of a 0.13 µm copper/low-κ logic technology. The defect densities determined by eD0 trend well with the defect densities calculated from the electrical parametrics. In addition, eD0 provides a means to maximize test structure area in conjunction with an increase in sensitivity over conventional inline electrical probe. Acknowledgements
This paper is based on a previously published article, “Rapid Interconnect Development Using an Area
Accelerated Electron Beam Inspection Methodology,” Proceedings of the 2002 International Interconnect Technology Conference, June 3-5, 2002, p. 33; permission to publish was granted by IITC. The authors would like to thank the KFAB Pilot line engineering staff members, as well as Doron Gal, Gaurav Verma, David Price, Peter Nunan, and Tom Long. References 1. R.Guldi, J. Shaw, J. Ritchison, S. Oestreich, K. Davis, R. Fiordalice - “Characterization of Copper Voids in Dual Damascene Processes” Advanced Semiconductor Manufacturing Conference, April 2002.
A Resounding Success As the industry was making the transition from 1x to 5x masks, KLA-Tencor and SEMATECH formed a partnership to develop the next-generation reticle inspection platform for the 100-nm node. As part of an innovative clause in the partnership, it was agreed that if the TeraStar product were a success, KLA-Tencor would pay SEMATECH a royalty on product shipments. SEMATECH would reinvest the funds so more breakthrough technologies like TeraStar can be developed to enable future technology generations. At the 2002 Semicon West show in San Francisco, KLA-Tencor CEO, Ken Schroeder, presented a check for $409,000 to Bob Helms, CEO of SEMATECH, in what 34
promises to be “the first of many checks.” “It’s time for me to perform an unnatural act, which is to give money away,” announced Ken Schroeder, “I want to thank SEMATECH for the great vision they had in seeing the roadmap, envisioning where our industry needed to go, and for their faith in us and this program.”
Royalty check presented to Bob Helms (CEO, Sematech) by Ken Schroeder at the company’s Yield Management Seminar held during Semicon West 2002.
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