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It’s A Small, Small, Small, Small World Part 1: Shrink Acceleration Through Successful Pattern Transfer Harold Lehon, Jim Wiley, William Volk, Mike Slessor, Tony DiBiase, Ingrid Peterson, and Chris Mack, KLA-Tencor Corporation Scott Ashkenaz
Repeating defects create enormous costs through yield loss, rework, lost time to market, and reduced customer satisfaction. The high cost of a repeating pattern defect has been well established, and a number of strategies have been implemented in fabs worldwide to reduce their impact. With low k1 lithography moving into volume production for many device types, it is important to understand the requirements for managing pattern transfer under the significantly changed conditions that it creates. While all of the causes for repeaters in the higher k1 regime also print at lower k1—and usually print more strongly—a number of significant new defect mechanisms have also arisen. In some cases, it is also necessary to establish new metrics to identify and describe these mechanisms and their impact. Introduction
One of the new measures that should be understood when determining reticle quality is its impact on the process window. Shrinking process windows with smaller design rules challenge the lithographer, requiring significant efforts to maximize the windows. Even a small deviation in energy on a reticle can collapse that window completely; yet, it is often difficult to identify locations on the reticle that may be probable causes, or even understand the “how” or “why” once the cause has been identified. There is an ongoing debate about which defects require action, and which can be ignored. For this paper, our discussion will focus on errors that result in (a) device failure; (b) a decrease in bin yield or performance; or, (c) a reduction in the size of the process window within which the lithography process must be maintained in order to produce high-performing devices. We will describe a method by which the impact of a defect on both the process window and yield entitlement can be quantified. Summer 2002
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This paper will examine the new challenges to pattern transfer presented by low k1 lithography, and present best practices currently being used in advanced semiconductor fabs worldwide to overcome these challenges. In several of these cases, KLA-Tencor has been working with wafer fabs to develop new tools to enhance pattern transfer management. These tools also help fabs to increase their reticle defect-learning rate—the rate at which they respond to, and reduce—the frequency of defects occurring for a specific process or application. The best practices described in this paper are: • Reticle inspection to identify and characterize defects on the reticle that may create repeating defects on the product including new types of defects arising from the implementation of low k1 lithography • Optimization of the total fab lithography window, which provides the maximum margin for reticle quality • Identification of design rule errors that do not meet the requirements of low k1 lithography and, therefore, result in reduced process windows, even when they are not classifiable as conventional reticle defects Characterizing the reticle
The first line of defense against repeating pattern defects is characterization of the reticles that will be used for patterning. Throughout its lifetime—from the first use for device creation to reuse for subsequent production lots—the reticle should be free of defects that can cause device failure or reduce the lithography process window. Reticle specifications are established by the wafer fab that typically refer to hard defects (chrome pattern errors and glass defects), soft defects (contamination, crystal growth), and critical dimension 24
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errors. Ideally, the mask fabricator certifies the out-going quality of a reticle with a reticle inspection tool that provides both pattern and concurrent all-surface contamination inspection. An example of one of these tools is KLA-Tencor’s TeraStar SLF77, which provides both die-todie and die-to-database inspection.
Incoming Qualification Once this certification is complete at the mask shop, and the reticle is shipped to the wafer fab, the fab should check this reticle into inventory, characterize it, and then begin to use it. In practice, most fabs at 0.18 µm design rules and smaller are performing varying degrees of characterization for incoming reticles— from a select number of reticles used for critical-layer development to a majority of all reticles. The frequency of this inspection depends on the value of the device being produced with the reticle. For example, if the reticle is used on critical layers such as
gates, contacts, vias, or interconnects in a high-performance device that is expected to generate significant revenue, the fab is more likely to characterize it upon receipt, and re-qualify it before repeated production use. Fabs that have implemented a specific procedure for reticle management, with clearly defined frequencies and an appropriate database, have enjoyed numerous benefits beyond prevention of yield loss resulting from repeating defects. One such example is defect yield learning, which is a specific process that is measured as an improvement rate over time and is well established in other fab process modules. Defect yield learning is driven by records that are available for evaluation and the systematic removal of defect sources. By tracking causes and their frequencies, it is possible for a fab to prioritize and focus its improvement efforts on the problems that have the greatest impact until they are eliminated. Figure 1 shows an example of
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a memory fab that identified specific sources and took specific actions for improvement. The fab identified contamination sources as being among the primary defect types. Subsequent improvements were made to reticle handling with SMIF, and with pellicles. This characterization is carried out most effectively through direct inspection of the pattern and reticle surfaces at high resolution. The four critical surfaces—pellicle outside, pellicle inside, patterned surfaces, substrate backside—are inspected to identify pattern (hard) and contamination (soft) defects.1 This is typically done in the wafer fab on a reticle inspection system such as the TeraStar SLF27 (see sidebar for a description on TeraStar.) By using high-resolution inspection, the defect can be captured in full detail, providing sufficient information to focus on eliminating its source. If the impact of the defect is uncertain, it may be carefully reviewed using methods described below. Figure 2 is an example of a hard defect on a contact that would have reduced the process window and resulted in yield loss if left undetected.
Figure 3. 130 nm Design Rule Contacts – A 6.5% energy difference was detected with TeraFlux on TeraStar. The red boxes indicate the location of the errors. By having such a tight tolerance, TeraFlux can identify errors that may not print under optimum conditions, but are likely to reduce an already tight process window. This is very effective in characterizing new reticles, and ensuring that reticles in inventor y have not degraded.
Some defect types may slightly reduce the energy transmitted through the reticle, due either to transmission issues or small pattern errors. This is especially problematic for contact and via patterns, as well as for some types of optical proximity correction (OPC) where they can mean the difference between a working device and a device that fails. TeraFlux on the TeraStar platform
Figure 2. Contact Hard Defect – A 60 nm reduction at the corner of the reticle is detected by TeraStar SLF77. Here, the reference image is in the center, the defective image is at right, and the calculated difference image is at left. The red box indicates the location of the error (from reference 1).
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(see sidebar on TeraFlux) offers the capability to find energy errors smaller than six percent during the normal reticle inspection process (see Figure 3). In some cases, the lithographer may want to understand the likely impact of a defect on the IC pattern. There are a number of tools available for this exercise, including printability analysis simulation software, where the high-resolution image from the reticle inspector is used to simulate the likely effect of the defect without actually requiring the wafer to be patterned. Printability analysis simulation software, such as TeraSim, —which is powered by the PROLITH engine—provides the flexibility to take any defect detected at high resolution and simulate the conditions of the stepper, substrate, and resist to understand the defect’s printability and its subsequent impact on the lithography process window.2 Of course, in some cases it may be preferable to use the reticle to print a wafer in order to examine the defect location directly using defect review tools or to inspect it.
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Arresting Reticle Degradation in the Fab
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STARlight Technology Simultaneous Transmitted And Reflected light STARlight signal Quartz Chrome
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Once a reticle has been characterized and checked into inventory, the fab will periodically re-qualify it to ensure that the reticle does not degrade over time. Probable causes of reticle degradation include contamination migration, new contamination, crystal growth, changes in organic residues induced by highenergy photons, and static discharge. Fabs are also beginning to conduct more frequent re-qualification in cases of lower wavelength exposure, where energy-related damage may occur. The rate of re-qualification depends on the fab and the criticality of the reticle.3 A study conducted by Grenon Consulting suggests that as the wavelength is reduced, re-qualification should increase significantly, as measured by the number of wafers exposed between qualifications (see Figure 4). This may be explained by a combination of factors. Movement to a lower wavelength is driven by smaller design rules and higher product value, and this also results in a decrease in critical defect size. Lower wavelengths—and, therefore, higher photon energies—may increase the rate of degradation. While much of the anecdotal data suggest that reticle-handling events are the major cause for degradation, there are also Reticle Maintenance Frequency
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Figure 4. Reticle Maintenance Frequency—The frequency of requalification, as measured by wafer exposures between inspections, increases with decreasing wavelength (Source: Grenon Consulting, Inc.).
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a significantly higher percentage of degradation events related to the number of exposures being implemented using a given reticle. With 300 mm wafers, for example, the increased number of exposures that are needed per wafer may contribute to an increased degradation rate. The smaller lot sizes, or increased handling per wafer exposure that are associated with these larger wafers, may also be a contributing factor.
In an advanced fab, active management of the lithography process window is critical to the overall yield, speed binning, productivity, and profitability. To quantify the impact that a defect from a critical-layer reticle can have on the process window, the lithographer should first calculate the process window. Only then is it possible to quantify any reduction in yield entitlement and make appropriate decisions based on benchmarked data.
The Common Process Window By using CD metrology tools, combined with integrated analysis,
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TeraFlux description
Low k1 lithography and high MEEF increase process sensitivity to small errors on the reticle. This is especially true on small closed features such as contacts, gates, and vias.11, 12, 13 While the errors may fall within the CD specification, the error of transmitted energy may still be sufficient to cause a wafer contact to not clear, or severely constrict the process window. TeraFlux was developed on the TeraStar platform to address the special needs of increased sensitivity for these features with high MEEF values. TeraFlux compares the transmitted energy to a reference with this equation: ∆flux = Σx,y (It - Ir)/[(It+Ir)/2] where: It = Intensity at pixel x,y on test die Ir = Intensity at pixel x,y on reference die and the inspection mode is die-to-die.
Maximizing the usable process window
Implementing low k1 lithography and controlling the lithography process within collapsing process windows is a constant struggle. While a number of techniques such as off-axis illumination (OAI), optical proximity correction (OPC), phaseshift masks (PSM), and lower wavelength exposure, help to open the window, the reduced process margins present a significant challenge. With a focus on the reticle, there are a number of issues, including classically defined defects, which can reduce that window. While adjustments to the sigma and numerical aperture (NA) of the scanner can help optimize the process window, understanding and optimizing reticles rules may still be necessary in order to maximize the usable window.
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Classical corner, intrusion, extrusion defects CD errors Semi-transparent defects FIB repairs CD SEM staining
lithographers have simplified the process of taking basic process window measurements. Measuring the common process window, which is common across all critical features on a device layer, remains the most Summer 2002
important—and challenging—task at hand. To accurately measure the common process window, lithographers must account for: • Pattern variations across the reticle (process and writing variations)
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• Small reticle defects that affect printed line widths (attenuator, substrate, contamination) • OPC and PSM methods and errors • Scanner dose uniformity across the scanned field
additional process window variations to consider, especially in advanced production fabs. While today’s scanners have impressive closed-loop controls and compensations, process window variations can
still occur over time as a result of the variables listed above and, when coupled with small fluctuations in the resist track performance, can have a significant impact on the process window. The total common process window is the overlap of these variations over time, and, in all cases, represents a reduction in the net process window. The lithography cell’s manufacturable process window must take these variations into account, or risk reduced yield or speed bin value. To maximize the total common process window, many fabs are beginning to actively monitor and manage the process window over time. By tightly managing the fluctuations, this process window can be increased, resulting in improved productivity and yield in the lithography cell.
Process Window Monitoring Several fabs are using both optical and SEM-based CD metrology systems with integrated process window management5 (PWM) capability to
• Scanner focus uniformity across the field • Field-to-field repeatability of focus and dose • Wafer-to-wafer repeatability of focus and dose Having access to this comprehensive set of process window data also allows the lithographer to use advanced lithography simulation and analysis software to accurately tune the simulation to achieve the best process.4 This approach is also valid for process development, defect printability, test reticle design, and design verification.
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Figure 6. Example of Common Process Window – The overlap of isolated lines and dense lines or spaces depicts the total common process window, which was measured with KLA-Tencor’s 8XXX
The Total Common Process Window
CD SEM and automatically calculated with integrated ProDATA, process window analysis soft-
Although this approach is useful in providing an accurate representation of a single process cell for a given point in time, there are a number of
ware. Here, the x-axis represents focus, and the y-axis represents dose. The contour lines (shown
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as thin lavender and thin red lines) depict the regions where the described features meet the CD requirements. The heavy blue line encompasses the area of overlap where both feature types are within specification, and the inscribed red rectangle is the combined process window.
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track and manage the stability of the process window over time. By running a periodic PWM procedure, the lithographer can quickly identify deviations in the process window, and obtain the quantitative information needed to make an informed decision to either: (a) correct it if the problem is simply a shift of best focus; or, (b) shut down the lithography cell if the depth of focus has changed unacceptably. Figure 7 is an example of the focus stability for a litho cell, showing the best focus and depth of focus over time. The frequency of the PWM procedure could be daily or once per shift, and is dependent on the process tolerance level (see sidebar for PWM procedure).
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PWM procedure
1. Process focus-exposure matrix wafer on the critical layer lithography cell. This application typically utilizes daily test wafers, to isolate result from product-wafer topography and films variations. 2. Measure wafer on 8x50-PWM or SpectraCD-PWM, using automated FEM metrology. 3. Following completion of automated measurement job, FEM data is automatically processed according to predefined specification limits and analysis conditions/parameters to produce a focus-exposure process window for that lithography cell, on that day. 4. Process-window data and reports for all PWM-monitored lithography cells are from anywhere on a company intranet, both inside the fab and at office-area desktops.
A high-volume production fab will have several critical scanners on the fab floor. To achieve maximum productivity, a fab should implement a strategy that enables any given wafer lot to be routed to multiple scanners, depending upon tool availability. However, if scanners have not been matched for a given process window, the yield or performance may vary depending upon which scanner the lot is diverted to. To address the problem, the lithographer must look at the combined process window of all of the lithography cells in a scanner family and maximize their common window. This is the total fab process window. By managing the stability of each scanner, and carefully matching the process windows of a scanner family, the lithographer will provide the best environment for yield and productivity, and provide the widest tolerance for the reticle issues that are covered in this paper. If scanners are not matched accurately, then it is necessary to either dedicate a reticle to one litho cell, or characterize it on only one cell. While this is adequate for development or for a single run, it is very costly in a manufacturing environment.
Figure 7. Daily process window stability for DUV scanner performed with KLA-Tencor 8450-PWM system. The blue line shows fluctuations in best focus, whereas the red line shows fluctuations in the size of the process window around best focus (from reference 5).
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Figure 8. Three-Scanner Process Window Matching (dose). PWM shows that dose adjustment allows all three lithography cells to be brought within the reference dose window (from reference 5).
This procedure for lithography cell matching and management may also be extended between “brick and mortar” fabs and virtual fabs. PWM provides a usable quantitative tool for ensuring that a device will encounter the same process window no matter where it is produced.
will have been identified and stabilized, providing the maximum window for a given process. The next area of focus is to ensure that each critical reticle functions within that process window.
Verifying the Design Significant effort has been invested in ensuring device design for manufacturability. TCAD products have been developed, which allow verification of the compatibility of device
The MEEF Advanced lithography processes with low k1 values enhance the impact of errors on reticles. The deviation in critical dimensions between the intended reticle image and the image printed on the wafer due to errors on the reticle is known as the Mask Error Enhancement Factor.10 The enhanced errors contribute to the loss in process window, or, as in the case of the example in Figure 9,
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Figure 8 shows dose matching of three DUV litho cells, represented by a web chart. The green line represents the reference. The blue line shows the location of each of the three scanners relative to the reference and the zero-window position (identified by the outer red line). Process window monitoring with the 8x50-PWM shows that all three scanners can be brought within the reference with the indicated dose adjustment to maximize the total fab process window.
patterns with design rules for enhanced lithography.6, 7, 8 Verifying the design, however, is very challenging when advanced lithography processes with low k1 values are being used to produce the actual device. Lithographers in advanced fabs have often observed that patterns may not print accurately over the entire process window, resulting in yield loss or performance loss. Unfortunately, it is not always easy to identify the locations that may cause a reduction in the total fab process window due to design issues. These design issues may include simple rule violations, errors in model or rule-based RET application, fracturing errors, grid errors, writing errors, or mask process biases.9 Some, but not all of these, may be identified by direct reticle inspection in either the mask fab, or in the fab characterization process described above.
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design to be printed much smaller than intended, resulting in complete process window failure. A 365UV HR reticle inspection system is used to detect the source of the error and PROLITH simulation software is used to verify the process window and pattern transfer.
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total failure in the overlap of the process windows. These errors may occur at any point on the reticle, and identifying them is the challenge. Quite often, these marginal design errors will not be detected during reticle inspection because the reticle was built correctly and perfectly matches the writer data. Design rule modifications for resolution enhancement that have not been based on adequate process models are, in fact, the actual cause for these failures. These erroneous modifications result in patterning failure within the process window. For example, sub-resolution scattering bars—which are often printed at lower doses—are a common source of process window reduction due to resolution enhancement techniques. Regardless of the source of these errors, it is the lithographer who is responsible for yield in the lithography cell, and who must ensure that the reticle is compatible with the established process window.
Identifying Patterning Failures Assuming that the error cannot be detected by the most advanced reticle pattern inspection (either die-todie or die-to-database), but is still significant to the pattern transfer and device process window, it is desirable to identify the possible patterning failure. Once the failure is identified, it is then possible to understand the impact, and make a decision for disposition of the wafer lot. A method has recently been developed which uses wafer inspection to identify marginal design errors that might fail only at the corners of the process window. These defects, which reduce the usable size of the process window, are often transient and show up as soft (or intermittent) repeaters at probe. This is sufficient to flag the weakness and allow the
Figure 10. Pattern Failure within Process Window – The KLA-Tencor 2351 high-resolution imaging tool was used to determine that a pattern design error caused a process window failure.
lithographer to work with the product engineer or designer to make a disposition. This method enables the lithographer to identify problems that cause failure within the known good process window, or just outside of it. It has been effective in identifying problems with scattering bars, serifs, model-based OPC, and PSM errors. In some cases, the window was severely restricted, making the reticle unviable for manufacturing. In other instances, it was determined that the reticle had a slight impact on the process window. In the latter case, it might be feasible to use the reticle for prototype or small production runs, or limit its use to one lithography cell. Another outcome is that these areas also become primary locations for production CD monitoring, since these marginal errors are likely to be the first to cause process window failure. The defect location, as reported by the wafer inspector, may be used as the location for easily generating a CD SEM recipe. Part II of this article will discuss this methodology in greater detail. Summer 2002
Bringing it all together
This paper has provided an overview of complementary strategies that the lithographer can use to support the fab’s transition to more advanced lithography processes. By employing a comprehensive reticle management strategy that assures incoming quality and continuously monitors the reticle for degradation, the lithographer can minimize the impact of repeating defects on yield and avoid costly crises. When defects are identified, the high-resolution images may be used to simulate their printability and impact on the process window. This paper has also demonstrated that it is possible to ensure the manufacturability of a new reticle through the use of wafer inspection, when built on top of the foundation of a stable process window achieved through the implementation of process window management. In cases where there may be an issue with a reticle, these qualification methods provide a well-quantified benchmark for decisions to be made, and can even direct the designer to weaknesses that will limit manufacturability. By understanding the
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Figure 11. Best known methods for preventing repeating pattern defects.
amount of process window that is lost to a limiting reticle, to the lithographer can more easily make quantified decisions about the reticle’s overall impact on the process window entitlement. Lithography is becoming more challenging with each generation of design rule and shrink. While it continues to grow in complexity and cost, lithography is also contributing to the increased value in the products produced within a fab. The strategies and best practices described in this paper provide conclusive and quantitative tools that enable the lithographer to maximize the productivity of expensive scanners and litho cells. These tools provide definitive and rapid information to make decisions about reticles and their impact on yield and bin sort results. By minimizing the impacts and delays of more critical requirements of smaller design rules, the lithographer is empowered to accelerate new technology shrinks, and reap the financial rewards that accompany their timely introduction to the marketplace.
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Acknowlegements
The authors gratefully acknowledge the assistance and support of International SEMATECH, Infineon, Atmel, and TSMC. The authors would like to thank Moshe Preil for his contributions and input. References 1. W. Volk et al, Multibeam high-resolution die:database reticle inspection, BACUS Symposium on Photomask Technology, Monterey, CA, USA, October, 2001. 2. L. Pang, K. K. Chan, Q. D. Qian, Comparison of attenuated PSM mask defect printability analysis using virtual stepper system and aerial image microscope system, SPIE Microlithography, Santa Clara, CA, USA, March, 2002. 3. V. Samek, et al, Cost effective reticle quality management strategies in wafer fabs, IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), Boston, MA, USA, September, 1999. 4. J. Byers, C. Mack, R. Huang, S. Jug, Automatic calibration of lithography simulation parameters using multiple data sets, micro and nano-engineering, Grenoble, France, September, 2001.
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5. R. Routh, et al, Automated lithography process window monitoring with 8250-PWM, KLA-Tencor Lithography Users Forum, Santa Clara, CA, USA, February 2002. 6. P. LaCour, E. Y. Sahouria, Y. Granik, Chip level linewidth prediction methodology, SPIE Microlithography, Santa Clara, CA, USA, March, 2002. 7. M. L. Rieger, J. P. Mayhew, Z. Tang, Verifying RET mask layouts, SPIE Microlithography, Santa Clara, CA, USA, March, 2002. 8. K. Liu, J.Cheng, J. Z. Wu, A. Jain, M. Mehrotra, M. Rodder, Improving device performance and process manufacturability through the use of TCAD, SPIE Microlithography, Santa Clara, CA, USA, March, 2002. 9. A. Berbert, et al, Adjustment of optical proximity correction (OPC) software for mask process correction (MPC), BACUS Symposium on Photomask Technology, Monterey, CA, USA, October, 2001. 10. W. Maurer, et al, Process proximity correction using an automated software tool, SPIE Microlithography, Santa Clara, CA, USA, March, 1998. 11. Y. H. Kim, J. H. Park, K. H. Lee, H. K. Cho, H. S. Yoon, Detectability and printability of programmed defects in the contact layer for 256Mb-DRAM grade reticle, BACUS Symposium on Photomask Technology, Monterey, CA, USA, October 1996. 12. H. J. Kim, J. S. Hong, J. W. Kye,D. H. Cha, H. Y.Kang, J. T. Moon, Defect inspection and printability of deep-UV halftone phase-shifting mask, BACUS Symposium on Photomask Technology, Monterey, CA, USA, October 1996. 13. K. Takeuchi, Y. Miyahara, Defect detectability and printability of contact hole pattern of KrF halftone reticle, Photomask and X-Ray Mask Technology, Kanagawa, Japan 1999 .
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complexity. As a result, in a 6-month period, engineers were able to move from zero yield on one of every four devices manufactured to finding every critical reticle defect. And bring their 0.13µm ramp yield issue under control faster and more efficiently than they ever thought possible. To see what you’ve been missing, please visit www.kla-tencor.com/tera, or call 1-800-450-5308. ©2001 KLA-Tencor Corporation
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