Magazine summer04 advanced substrates by KLA Corporation

S New Ideas for New Materials U

Advanced Substrates and Devices for Nanoscale CMOS Bich-Yen Nguyen, Aaron Thean, Ted White, Alexander Barr, Bruce Xie, Stefan Zollner, Mariam Sadaka, Xang-Dong Wang, Anne Vandooren, Leo Mathew, Melissa Zalava, Da Zhang, Debby Eades, Zhong-Hai Shi, Victor Vartanian, Shawn Thomas, Tab Stephen, Brian Goolsby, Ran Liu, Thien Nguyen, Veer Dhandapani, Jack Jiang, Raghav Rai, David Theodore, Mike Kottke, Rich Gregory, Michael Canonico, Ross Noble, Sriram Kalpat, Michael Mendicino, Marius Orlowski, Joe Mogab, Suresh Venkatesan, Freescale Semiconductor

The semiconductor industry has achieved exponential growth over the last thirty years, largely due to its ability to continually scale the CMOS transistor dimension to meet demands for density and performance. As device dimensions reach the sub-50-nanometer level, serious doubts are being raised regarding the ability to scale the gate lengths of conventional bulk silicon transistors below 30 nm. This has led to the integration of new materials and device architectures into CMOS devices. In this paper, we will discuss the progress and challenges of strained Si and SiGe materials being introduced into nanoscale CMOS devices.

Introduction

It becomes more difficult to scale CMOS transistors and still maintain high drive currents, while simultaneously dropping the supply voltage (Vdd) to prevent raising the electric field (which reduces carrier mobility) and avoid reliability issues. The threshold voltage and gate oxide thickness cannot be scaled at the same rate as Vdd without leakage currents exceeding stand-by power requirements. Thus, the maximum gate overdrive factor, Cox(Vdd-VT), is rapidly reduced with transistor scaling.1 At the same time, higher channel doping concentrations and more abrupt, shallower source-drain junctions have been used to control short channel effects (SCE) at very short gate lengths. These factors cause detrimental effects, such as degraded mobility, higher dopant fluctuations, and increased series resistance. In order to circumvent some of these scaling issues, new materials and device architectures are being integrated into CMOS devices to maintain the historic CMOS performance 48

Summer 2004

Yield Management Solutions

trend. These include enhancing carrier mobility by using biaxially stressed strained silicon (Si) with relaxed silicon germanium (SiGe) virtual substrates2 or uniaxially stressed Si using tensile or compressive stressors.3 Though the strained-Si (sSi) augmentation of conventional MOSFETs seems minimally disruptive, the use of SiGe virtual substrates in CMOS devices introduces new process and device issues that need to be addressed in order to prove successful manufacturability. Strained Si and silicon germanium channel engineering

When a thin Si layer is grown pseudomorphically on a relaxed SiGe alloy buffer (Figure 1) with its larger lattice spacing than that of Si, the Si layer conforms to the SiGe template by expanding laterally and contracting vertically. The resulting biaxial stress enhances the transport properties of the Si layer due to the altered band structure and electronic properties. It reduces inter-valley and inter-band phonon scattering, hole effective mass due to band warping, and preferential thermal population of electron states with light transport effective mass. Improvement of both electron and hole mobility by using the biaxial tensile sSi as a transistor channel has been demonstrated. However, sSi by

Strained Si Channel

Biaxial TensileStrained Si Layer

Constant Si1-xGex Graded Si1-xGex

Gate Source

Drain

Si1-xGex

Si substrate

Relaxed Si

Strained Si

Relaxed SiGe

Figure 1. Strained Si/SiGe virtual substrate

nature is a meta-stable material system independent of the fabricating approaches, and has several intrinsic limitations as compared to unstrained Si. These limitations need to be examined under the context of CMOS

b) TDs

process integration to achieve high-yielding and reliable strained Si CMOS technology. The material challenges for sSi on relaxed SiGe alloy include: (a) misfit dislocation generation at the hetero-interface, (b) dislocation propagation to the active region, (c) surface roughness, (d) induced strain non-uniformity, and (e) thermal stability of sSi material during CMOS processing.4,5 Figure 2a shows a cross-sectional TEM image for a typical sSi layer grown on a composition-graded SiGe buffer. The dislocations are mostly confined to the composition-graded buffer layer region. The misfit dislocations (MD) in the buffer, which act as leakage sites, can turn to threading segments (TD), which also act as leakage sites and must be reduced to an acceptable level, preferably below 1x104/cm2. Figure 2b is a plan view TEM, revealing TDs intersecting the sSi channel region. By etching the wafer, TDs appear as dot contrasts and MDs emerge as line contrasts (Figure 2c). Furthermore, cross-section TEM and plan-view TEM (Figures 3a and 3b) reveal misfit dislocations at the interface between the sSi channel and SiGe buffer layers. Such MDs are quite detrimental to the device performance, since they are within a few tens of nanometers to the active region and can become current leakage paths. A recent photoemission microscopy study has directly correlated the leakage sites to these types of misfit dislocations.6 This factor sets an upper limit for the thickness of sSi for a given strain in the channel known as the critical thickness. CMOS processess can play a role in MD generation. Figure 3c shows a plan-view TEM image a)

1 Âľm

b) MDs

Before annealing

After annealing

Figure 2. (a) A cross-section TEM image for a typical composition-

Figure 3. (a) Cross-section TEM image showing misfit dislocations (as

graded SiGe buffer layer. Most of the defects are confined in the

pointed out by the arrows) at the interface between strained Si channel

graded SiGe buffer region. (b) A plan-view TEM image shows thread-

and SiGe buffer. (b) A plan-view TEM image of the same sample

ing dislocations intersecting the wafer surface. (c) An optical image

showing MDs. (c) After annealing the sample at 900Â°C for 60 seconds,

for a sample being delineated to show TDs and MDs.

the density of the MDs increases.

Summer 2004

www.kla-tencor.com/magazine

a) b)

]

c) ]

[110]

Figure 4. (a) An AFM image of a typical surface for an as-grown SiGe relaxed buffer layer without a CMP process implemented. An RMS roughness of 7.2 nm has been obser ved. (b) Spatially resolved UV-Raman stress mapping in the Si cap. A cross-hatch pattern along [110] types of directions has been obser ved. The stress varies in the range between 1.10 to 1.20 GPa. (c) an AFM image from a wafer grown under the same condition as (a) but with CMP. The RMS reduces by a factor of seven to about 1.0 nm.

for the same sample after being annealed at 900°C for 60 seconds. The spacing between MDs decreases from 4.5 µm before the anneal to 2.0 µm after the anneal, suggesting approximately a two-fold increase in MD linear density. Another challenge is the surface roughness of the thick SiGe epitaxial film on the silicon substrate. Surface roughness develops via either strain relaxation, or as a result of non-uniform mass transfer on the surface in the vicinity of the existing dislocations and strain fields (Figure 4a). The AFM image of an as-grown strained Si layer on SiGe buffer layer shows a surface roughness of 7.2 nm. Such roughness, or cross-hatch pattern, causes spatial strain variation, and correlates well with microRaman mapping in Figure 4b. The scales of spatial variation in AFM and Raman mapping are on the same order, and along the same crystalline directions. Surface roughness has been known to reduce the mobility of sSi. In addition, surface roughness can also promote dislocation formation at localized high-stress regions on the surface. The chemical mechanical polishing (CMP) process has been implemented to smooth the SiGe surface, followed by additional SiGe growth and then sSi growth. Enhanced electron mobility has been demonstrated for sSi transistors using CMP.7 Figure 4c shows an AFM image of an sSi wafer having such a CMP step inserted. Surface roughness is seen to reduce by one order of magnitude to about 0.5 nm or better.

sSi on silicon-on-insulator (SOI) is a natural extension, combining the advantages of SOI and carrier mobility enhancement of the tensile-strained Si for high-performance, low-power applications.8 Many wafer fabrication processes have been investigated to fabricate sSi on SOI. A compliant substrate approach was first examined9 by growing SiGe on SOI, with the hope of simultaneously achieving both the desired strain relaxation in SiGe as well as low defect density. Then, a strained Si channel was grown on top of the relaxed SiGe. It has been found that growing relaxed SiGe on bulk silicon or SOI is generally accompanied by the generation of high defect density. In the case of SOI, the defects are located closer to the channel region. Thus, they have a more pronounced impact on leakage current, limiting the practical application of the compliant substrate approach. A second approach is germanium (Ge) enrichment,10 where similar challenges are present. The fundamental reason is that SOI is not a “fully-compliant” substrate. Thus, some defects are likely to be generated during SiGe relaxation. Alternative approaches include separation of the highquality relaxed SiGe layer from the heavily misfit dislocation region by using the oxygen implant and anneal (SiMOX) process.11 In SiMOX processing, the anneal is generally conducted at a temperature above 1000ºC. The Ge content allowed in the relaxed SiGe is about 10 percent, limited by the SiGe melting point at a given Ge content.11 The SiMOX process introduces additional defects, such as threading dislocations and stacking faults at the interface between oxide and Si or SiGe.12 Recently, the layer transfer technique has been utilized to produce sSi on insulator with a relaxed SiGe layer— silicon germanium on insulator (SGOI)13—or without a SiGe layer—strained silicon on insulator (sSOI),14 in order to achieve the maximum possible strained and low threading dislocation density that is comparable to strained Si/SiGe on bulk (Figure 5). This technique Strained-Si Directly on Insulator (sSOI) Wafer bonding

Si substrate removal

Si Substrate Graded SiGe Relaxed SiGe Strained Si

Relaxed SiGe Strained Si

Summer 2004

Yield Management Solutions

Strained Si

SiO2

Si substrate

Figure 5. sSOI substrate using layer transfer, removing the SiGe virtual substrate. The misfit dislocation at the sSi/SiGe interface and threading dislocations in the SiGe can be removed.

SiGe removal

Strained Si thickness map

a) Strained Si SiGe BOX

c) Relaxed SiGe thickness map

50 nm

Figure 6. (a) TEM cross section of an SGOI substrate. (b) Strained Si thickness uniformity across a 200 mm wafer (c) Relaxed SiGe thickness uniformity across a 200 mm wafer

may be a more appealing and promising option for highperformance circuit applications. However the SGOI and sSOI substrates are still in the early development stages with limited quantities, long lead times, high defectivity levels, and high costs. At best, the quality of the SGOI using either SiMOX or the layer-transferred technique is equivalent to the as-grown relaxed SiGe layer. Thus, achieving a high-quality relaxed SiGe buffer layer on bulk Si substrate is the first step towards successful sSi technology. The subsequent SiMOX or layer transfer processes impose additional challenges. Compared to an un-strained Si donor wafer, the

Raman Intensity

Untrained Si-Ref sSOI no anneal sSOI, 900°C, 30 min sSOI, 1000°C, 90 sec

520

530

540

Raman Shift (cm-1)

The introduction of new materials always poses process control challenges in Si CMOS manufacturing. This is especially true for SOI and sSi substrates, with or without SiGe alloy buffers. The parameters to be measured include thickness, composition (Ge content), dislocation density, interface conditions, roughness, and strain. Materials parameters such as refractive index often depend on processing conditions, crystallinity, and strain, which may influence the measurement. Traditionally, spectroscopic ellipsometry (SE) has been the method of choice for measuring thickness. Capabilities and limitations of this technique have been described elsewhere.15 It seems clear, however, that new, nondestructive inline metrology and inspection techniques will be needed, including UV Raman spectroscopy for strain characterization, infrared photoluminescence for defect inspection, X-ray reflectivity (XRR) for thickness measurement, X-ray fluorescence for Ge content, and possibly X-ray diffraction for both Ge content and strain measurement. Figure 8a shows an example of an XRR measurement and a fit to the data based on a model of the film stack

Intensity (cps)

510

Strained-Si/SiGe process control

a) Oxide: 1.4 nm thick, 71% density, 0.4 nm Rms Si: 17.2 nm thick, 100% density (fixed), 0.3 nm Rms SiGe: 26% Ge (fixed), 95% density, 0.5 nm Rms

105

500

strained-Si/SiGe donor wafers have a larger surface roughness, more adhesion issues, and limited thermal budgets for the bonding process. Despite these challenges, several SOI substrate vendors have provided SGOI and sSOI wafers capable of supporting CMOS device and process development. Figure 6 shows a cross-section TEM with no observable dislocations, (a), and acceptable strained Si and SiGe thickness uniformities, (b) and (c). Figure 7 shows excellent thermal stability of the sSi layer on insulator (SSOI)—up to 950°C for 30 minutes and 1000°C for 90 seconds— compatible with SOI CMOS integration.

106

490

b) epoxy

104 103

102 101

XRR

100

SiGe -0

1000 2000 3000 4000 5000 6000 7000 8000 9000

omega-2theta (sec)

Figure 7. UV Raman spectra of an unstrained Si substrate and three sSOI substrates with a 400 Å sSi layer with and without annealing

Figure 8. (a) High-resolution X-ray reflectivity (XRR) data for a strained

conditions. The strain is proportional to the frequency shift of the Si-Si

Si layer on a thick relaxed SiGe alloy buffer (black) in comparison to

vibration, yielding a convenient method for inline measurement of the

a model (red) of the film stack shown in (b). The structure near 8000”

strain.

is an artifact from the instrument.

Summer 2004

www.kla-tencor.com/magazine

shown in Figure 8b. The results of fitting the model to the data include thickness, density and roughness each film in the stack. The interference fringes are an excellent method to determine the thickness and roughness of the strained Si layer. The data are less sensitive to the parameters of the native oxide and the density of the layers. All of these process control techniques have challenges and limitations on SOI, especially with ultra-thin and stacked films. Further development of analytical methods is required, and inline metrology and inspection tools using these techniques are just becoming available. Determining composition and strain on the deep submicron device length scale remains an unsolved problem.

Concentration (cm-3)

1x10

Concentration (cm-3)

1x10

B in Si

1x1019 18

1x10

B in SiGe

1x1017

0.1

0.2

Depth (µm)

B in SiGe

B in Si

1x10

0.1

0.2

0.3

0.4

Depth (µm) Figure 10. Diffusion of B in Si and sSi-SiGe heterostructure after a

Strained Si/SiGe integration and device performance

Due to dramatic dopant diffusion differences in Si and SiGe (Figures 9, 10), extensive source-drain and channel re-engineering is necessary to achieve optimized shortchannel devices. We have shown that the enhanced arsenic (As) diffusion is sensitive to the presence of the sSi-SiGe hetero-interface. The variation in sSi cap thickness (TsSi) can cause major changes in the sourcedrain extension profile, leading to variation in effective channel length.16 Through careful implant design, the dopant diffusion can be controlled and the sensitivity to TSSi can be minimized, even with high-temperature anneals. Due to the retarded boron (B) and enhanced As diffusion in SiGe, the SSi n-channel devices show a more abrupt halo profile and deeper source-drain junctions with respect to the optimized Si devices. The

Concentration (cm-3)

1x10

Ge concentration

10-second high-temperature anneal. Inset is dopant diffusion at 900°C (Color:Simulated; Black: SIMS).

same dopant diffusion has an opposite effect on the p-channel devices. Scanning capacitance microscopy (SCM) analyses clearly show a more abrupt transition between the extension and the deep source-drain doping in the sSi-on-SiGe devices (Figure 11). As TsSi is reduced to meet critical thickness requirements with increasing strain, Ge up-diffusion during CMOS processing is expected to be a major concern. Besides strain and structural degradations, Ge in the gate oxide may lead to increased interface trap density.17,18 Though Ge is a slow diffusing specie, we show that Ge up-diffusion can be exacerbated during thermal cycles after low-dose source-drain and channel ion-implantations due to point defect increases (Figure 12). As much as 40 percent of the initial sSi can be effectively lost due to Ge up-diffusion.

As-Implanted (As in SiGe) As in Si

As in SiGe

With optimized source-drain and halo doping, sSi devices demonstrate superior short-channel control.

Without sSi

Source

Drain

Source

Drain

0.05

0.1

Depth (µm)

Diffused doping contour profile

Abrupt doping contour profile

Figure 9. Diffusion of As in Si and sSi-SiGe heterostructure after a

Figure 11. Source/drain and extension doping profile of the short-

10-second 1025°C anneal (Color:Simulated; Black: SIMS).

channel pMOSFET for (a) Si control device and (b) sSi device by SCM.

Summer 2004

Yield Management Solutions

Cumulative Probability (%)

15nm sSi 10

Ion-implanted

SiGe

Ge concentration (%)

100

0.1

Un-implanted 0

100

Si Control

sSi TDD = 3x105 cm-2

sSi TDD = 3x107 cm-2

40 20 0 1.E-12

0.01

1.E-10

1.E-08

1.E-06

1.E-04

Diode Leakage Current (A/µm2)

Depth (nm) Figure 12. SIMS profiles of Ge concentration in the 15 nm sSi cap on SiGe after 10 second high-temperature anneal for implanted and un-

Figure 14. Comparison of reversed-biased current of large-area diode test structures between Si and sSi.

implanted samples.

They exhibit a drain-induced barrier lowering (DIBL) metric of only 30 mV/V and an inverse sub-threshold swing of 77 mV/dec, while the equivalent Si device shows a threefold larger DIBL (Figure 13). The sSi device exhibits a 46 percent increase in drive current and a 20 percent increase in saturation trans-conductance over the Si device at one-volt gate overdrive. However, the Si off-state leakage is as much as three orders of magnitude higher than the Si device. The smaller bandgap of SiGe (25 percent Ge) alone cannot account for the magnitude of the diode current. Characterization of large-area diode test structures for different wafers shows the dependence of diode current on threading dislocation density (TDD) (Figure 14).

Improving the TDD, from 1x107cm-2 to 1x105cm-2 (for the same Ge composition and strain), leads to three to four orders of magnitude reduction in diode current. sSi junction current with respect to Si at low TDD is still limited by the SiGe bandgap. To minimize the diode current enhancement, it is necessary to situate most of the high-field source-drain extension regions in the sSi channel and avoid the SiGe regions. Misfit dislocations at the sSi-SiGe hetero-interface that arise from sSi relaxation can pose serious yield and reliability problems.18 The likelihood of a misfit dislocation at the sSi-SiGe interface intercepting the source and drain across the wide channel is high. Dopant diffusion from the source and drain can be further enhanced along the defect, creating a weak buried channel and causing excessive leakage in devices.

1.E-04

sSi

1.E-05

1.E-07

1.E-03

GM (Sat) (A/V-µm)

IDS (A/µm)

1.E-06

1.E-08 1.E-09 1.E-010

1.E-03

sSi

8.E-04

~40%

~20%

6.E-04 4.E-04

2.E-04 0.E+00

1.E-011

0.2

0.4

0.6

0.8

VGS-VT(Sat) (V)

1.E-012

-0.5

0.5

Cumulative Probability (%)

1.E-03

100

Si/CoSi2 + Elevated S/D

80 60

sSi/CoSi2 + Elevated S/D Si/CoSi2

40 sSi/CoSi2

~10X

0 1

VGS — VT(Sat)(V)

100

1000

Silicide-N+ Sheet Resistance (Ω/ )

Figure 13. Id-Vg cur ves for 60 nm sSi and Si devices. Inset:

Figure 15. Silicided N+ sheet resistance for various source-drain

Saturation transconductance at Vds=1.2 V.

structures and silicides.

Summer 2004

www.kla-tencor.com/magazine

The impact of Ge segregation during S/D cobalt silicidation has been characterized by sheet resistance (Rsheet) of silicide-on-n-doped test structures (Figure 15). By elevating the source-drain with the use of selective epitaxial growth of Si, sheet resistances comparable to CoSi2 on Si can be achieved. Without the use of elevated source-drain or nickel silicidation, we get a tenfold increase in source-drain resistance. SGOI provides high performance through enhanced mobility devices in a thin strained Si layer on relaxed SiGe19 with junction capacitance lower than that obtainable with devices on bulk Si. We have observed extremely high electron mobility enhancements in strained Si devices on bulk wafers. Given this enhancement on bulk Si, simulations demonstrate that SGOI devices surpass ITRS high-performance and low operating power targets for a physical gate length of 30 nm. As the top Si/SiGe layers continue to thin, eventually there will be no room for the SiGe. Another structure, sSOI,20 where the SiGe is removed, may be ready to step in and take full advantage of the tensile biaxial strained Si for mobility enhancement, without the issues associated with the SiGe hetero-structure. Moreover, the benefit of fully depleted devices can add more advantages to the sSOI approach. Most importantly, the process for making sSOI is simpler than the process for SGOI substrates. Thus, it offers the possibility of driving the sSOI substrate costs down fasterâ&#x20AC;&#x201D;with lower defectivity than those of SGOI substratesâ&#x20AC;&#x201D;to realize a more cost-effective solution. Figure 16 shows the calculated maximum allowable silicon dislocation densities as a function of kill rate for microprocessors.21 Today, sSOI substrates are available with at least one order of magnitude lower TDD (less than 1x104/cm2) than the SGOI substrate (1-5x105/cm2).

Threading Dislocations (/cm2)

1E+7

1E+6

1E+5

1E+4

and high-k gate dielectrics on UTBSOI substrates operating in a FDSOI mode (solid colored lines) and devices with doped poly-Si gate and SiO 2 gate dielectric on bulk Si (solid black lines). Universal mobilities are shown by the dashed lines.

An advantage of ultra-thin body SOI (UTBSOI) devices is their high mobilities, particularly when coupled with metal gates, high-k gate dielectrics, undoped channels, and operated in a fully-depleted SOI (FDSOI) mode. Figure 17 shows electron and hole mobilities as a function of the vertical effective electric field.22 Devices with metal gates and high-k gate dielectrics on UTBSOI substrates operating in an FDSOI mode show degraded electron mobility at fields above 0.5 MV/cm when compared to devices with doped poly-Si gate and SiO2 gate dielectric on bulk Si. However, the peak mobility of the UTBSOI devices is 19% higher. High-field hole mobility of both devices is virtually identical and essentially the same as the universal hole mobility. FDSOI devices with metal gates and high-k gate dielectrics show low-field mobility nearly double that of devices with poly-Si gate and SiO2 gate dielectric on bulk Si. The combination of advanced processes and advanced substrates provides other superior device characteristics, such as short channel effects, device leakage, low active power, low device-to-device matching, and low distortion.22

1E+3

Microprocessors @ CD = 0.25 microns 1E+2 1E-8

1E-7

1E-6

1E-5

1E-4

R (Kill Rate) Figure 16. Calculated maximum allowable silicon dislocation densities as a function of kill rate for microprocessors.

Figure 17. Electron and hole mobilities for devices with metal gates

Summer 2004

Yield Management Solutions

Ultra-thin SOI wafers present new process control challenges. Silicon thickness variation in UTBSOI wafers can affect device characteristics, such as threshold voltage (VT), through charge sharing and DIBL effects.23 The relative across-wafer thickness variation of standard SOI wafers increases as the wafers are thinned (Figure 18a).

Thickness Variation (%)

45 40 35 30 25 20 15 10 5 0

the progress made in defect reduction (Figure 19a). Clearly, UTBSOI substrate Si thickness and surface defectivity have improved substantially. Improved process control, novel deposition techniques, and/or gas cluster etching may result in even better thickness and defectivity control.

Vendor 1

Conclusion Vendor 1 Vendor 2

100.0

300.0

500.0

700.0

Average Thickness (Å)

50 nm 260 Å

354 Å

Si BOX Figure 18. (a) Relative across-wafer Si thickness variation of conventional SOI wafers thinned by oxidation and etching and UTBSOI

Significant progress in the development and quality improvement of strained Si on bulk and on insulator substrates has been achieved. Material and integration issues pertaining to Ge diffusion, threading and misfit dislocations, and silicide in sSi devices have been addressed. Implementing strained silicon is not just a substrate change with some defectivity issues. It requires extensive work as transistor scaling continues. Biaxially sSi devices that meet the ITRS high performance target have been demonstrated. As generally viewed by the industry, strained Si/SiGe CMOS technology will be implemented in the 90 nm and 65 nm technology nodes.

wafers prepared by a couple of wafer vendors. (b) TEM cross-section of conventional SOI wafers thinned by oxidation and etching. The

1600

different colors and symbols represent different measurements and

This is the result of an initial fixed uniformity being conveyed to the thinner SOI. The variation can be as high as 25 percent in the ultra-thin regime (less than 300 Å). More recently, SOI vendors have improved their processing of UTBSOI wafers to the point where the relative, across wafer non-uniformity is comparable to that of SOI wafers commonly used for manufacturing PDSOI circuits. Local Si thickness non-uniformity is equally important to devices. Figure 18b shows a TEM cross-section of a thinned SOI wafer, where the Si thickness varies by nearly 100 Å or 30 percent in as little as 100 nm. This non-uniformity remains too high for high-volume manufacturing of large monolithic circuits at deep sub-11 nm geometries. Defectivity is another SOI wafer characteristic that increases as the Si thickness of conventional SOI wafers decreases. Figure 19a illustrates that the increase in defect count on a wafer with decreasing silicon film thickness is gradual. The defect count increases sharply when the silicon film thickness is below 200 Å, where the most common type of defect is the so-called HF defect. Typical images of these defects are shown in Figure 18b. Defect counts of recent UTBSOI wafers from a vendor demonstrate

Particles per Wafer

wafers. 1200

800

400

Vendor 1 0

100.0

150.0

200.0

250.0

300.0

350.0

Average Thickness (Å)

-1 µm -100 nm

Figure 19. (a) Particle counts of conventional SOI wafers thinned by oxidation and etching and UTBSOI wafers prepared by a wafer vendor. (b) SEM image of defects in conventional SOI wafers thinned by oxidation and etching. The different colors and symbols represent different measurements and wafers.

Summer 2004

www.kla-tencor.com/magazine

Acknowledgements

We wish to thank Dan Noble Center-MOS13, APRDL, PALTX, PALAZ, and CMOS Device Platform groups for their technical and management support. References 1. 2. 3.

Y. Taur, Tech. Dig. Int. Symp. VLSI Tech, p.6 (1999). K. Rim, et al., IEDM Technical Digest, p.707 (1998). T. Ghani, et al., IEDM Technical Digest, p. 11.6.1 (2003). 4. E. A. Fitzgerald, et al., J. Vac. Sci. Technol., Vol. 15, p.1048 (1997). 5. Y.B. Bolkhovityanov, et al., Physics-Uspekhi, Vol. 44, p.655 (2001). 6. J.G. Fiorenza, et al., IEEE International Reliability Physics Symposium Proceedings, Vol. 42, p. 493 (2004). 7. N. Sugii, et al., IEDM Technical Digest, p.737 (2001). 8. H.S P. Wong, IBM J. Res. & Dev., Vol. 46, p.133 (2002). 9. Y.H. Lou, et al., Appl. Phys. Lett., Vol. 78, p.1219 (2001). 10. T. Tezuka, et al., Appl. Phys. Lett., Vol. 79, p.1798 (2001).

11. T. Mizuno, et al.,, IEEE Trans. Electron Devices, Vol. 48, p.1612 (2001). 12. P. Roitman, et al., Proc. 1998 IEEE International SOI Conference, p.20 (1998). 13. Z. Y. Cheng, et al., IEEE Electron Device Lett. Vol. 22, p.321 (2001). 14. L. Huang, et al.,, IEEE Trans. Electron Device Vol. 49, p.1566 (2002). 15. S. Zollner, et al., Thin Solid Films Vol. 455-456, p.261 (2004). 16. A. V-Y Thean, et al., Proceedings of SISPAD 2003, p.195 (2003). 17. M.L. Lee, et al., IEDM Technical Digest, p.69 (2003). 18. H.C-H. Wang, et al., IEDM Technical Digest, p.61 (2003). 19. B.H. Lee, et al., IEDM Technical Digest, p.946 (2002). 20. K Rim, et al., IEDM Technical Digest, p.3.1.1 (2003). 21. M.L. Alles, et al., Proc. 1997 IEEE International SOI Conference, p.128 (1997). 22. A. V-Y Thean, et al., Tech. Dig. Int. Symp. VLSI Tech (2004), to be published. 23. A. Vandooren, et al., 1998 IEEE International SOI Conference, 25 (2002).

To register online for the upcoming YMS, please visit us at: http://www.kla-tencor.com/seminar Date: Time: Location:

Friday, August 13, 2004 11:00 am â&#x20AC;&#x201C; 6:00 pm Singapore

YMS at a Glance

Summer 2004

DATE

LOCATION

August 13 August 17 September 13 November 18

Singapore Hsinchu, Taiwan Monterey, California, USA Shanghai, China

Yield Management Solutions