Magazine summer04 surfscansp2 enable cost by KLA Corporation

S New Ideas for New Materials U

Surfscan SP2: Enabling Cost-Effective Production at the 65 nm Node and Beyond Wayne McMillan, KLA-Tencor

Each time the semiconductor industry has moved forward to the next node, and looked beyond to future nodes, new materials have played important roles in enabling the shrinking of critical dimensions. The 65 nm and 45 nm nodes will likely be marked by the introduction of metal oxides, organic porous and nonporous low-k dielectrics, metal gates and new silicides. Engineered substrates, such as silicon on insulator and its derivatives, will see significantly increased market adoption.

New materials on the horizon

Integration of organic low-k dielectrics with copper dual-damascene interconnect structures will be one of the challenges in the back end of the line. While critical for their insulating properties, low-k dielectrics have less desirable mechanical properties, such as poor hardness and elasticity. This means the films have a higher probability of delaminating, deforming and, thus, generating defects under the load of the multilayered interconnect film stacks. Also in the back end, new etch stop and capping layers may be introduced to solve other issues, and new slurries and CMP techniques are likely to arise. In the front end, the 65 nm and 45 nm nodes promise not only new materials, but also new structures. Some manufacturers, such as Intel and TSMC, are looking at moving to a tri-gate or “3D” transistor1 (Figure 1). This radical new design would use silicon dioxide and, potentially, a high-k dielectric, as the gate insulator. High-k dielectrics, such as hafnium oxide, zirconium oxide, or lanthanum aluminate, would be introduced in order to reduce current leakage—a serious issue as gates become smaller and thinner. As usual, however, the benefit doesn’t come 14

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without penalties: high-k materials have the drawback of mobility degradation for carriers in the channel below, creating serious problems for setting the threshold voltage. Furthermore, high-k dielectrics seem to be incompatible with polysilicon, forcing a simultaneous material switch to metal gate electrodes. Intel has reported that at the 45 nm node, they will move from doped polysilicon for the gate electrode, to two different metals for the NMOS and the PMOS transistors. Other manufacturers, such as UMC, are planning to remain with planar transistors and address the 65 nm node requirements solely through a change in materials. They will introduce high-k dielectrics and metal gates followed by selective epitaxial growth (SEG) in the

Figure 1. Tri-gate or “3D” transistor. Source: Intel.

elevated source/drain structure. While a SEG layer would add a few steps to the process flow, it would not add much cost to the device, and the benefit that would result from reduced source/drain junction leakage and reduced contact resistance make the added process steps worthwhile. However, growing the SEG layer without interfering with the dopants beneath the gate remains a challenge. Another revolutionary change at the 65 nm and 45 nm nodes is in the substrate itself. While high-volume production of silicon-on-insulator (SOI) wafers has been underway for more than five years, and some leading-edge manufacturers have already been using SOI for high-end ASICs and microprocessors, SOI and other composite, engineered substrates are expected to enter mainstream device manufacturing by the 65 nm node. Thin film SOI substrates are well-suited for partially depleted MOSFETs, while ultra-thin silicon film SOI (XUT SOI) wafers are optimal for fully depleted devices. Further examples of engineered substrates under development include strained SOI (sSOI); germanium on insulator (GeOI); silicon on germanium on insulator (SGOI); and novel SOI crystal orientations for FinFet optimization. Most of these more complex engineered substrates are aimed at the 45 nm node and beyond. Defect detection challenges at the 65 nm node and beyond

Hand in hand with new materials come new defect types. Hand in hand with shrinking design rules comes the need for detecting smaller defects. These defects must be detected, identified, and correlated with yield to determine the extent to which they are yield-critical. Fundamentally, higher sensitivity defect detection on all of the new film materials is essential.

yield-killing defects at the 65 nm node and beyond. Wafer and IC manufacturers must move to UV inspection systems in order to meet their requirements for defect sensitivity. A UV inspection system provides the key to multi-node extendibility—critical for capital cost and cost of ownership containment. To address these issues, KLA-Tencor has introduced the Surfscan SP2, a new inspection system offering significantly increased sensitivity on all substrate and film types, as well as increased throughput under all conditions. Featuring UV illumination, the Surfscan SP2 treats the top silicon layer of a layered substrate as an opaque film, providing maximum performance independent of silicon- or BOX-layer film thickness. For traditional silicon substrates, the Surfscan SP2 delivers the highest performance with the lowest cost of ownership of any wafer inspection system. It also provides significant sensitivity improvement on all film types as shown in Table 2. Overall, the Surfscan SP2 enables current and next-generation substrate qualification, as well as process tool qualification and monitoring at the 65 nm and 45 nm nodes, with extendibility to the 32 nm node. Surfscan SP2: Designed for cost-effective inspection at the 65 nm node and beyond

The main goals in designing a new wafer inspection system were:

• Increased sensitivity to meet wafer manufacturer and process tool qualification and monitoring requirements for the 65 nm and 45 nm nodes, extendible to the 32 nm node

• Lower cost of ownership via increased throughput • Sensitivity on engineered substrates independent of top-layer and BOX-layer thickness

Defect detection on engineered substrates is challenging for several reasons. As with defect detection on films, critical dimensions are smaller at the 65 nm and 45 nm nodes, and thus killer defects are smaller. Second, traditional wafer surface inspection systems, utilizing visible wavelength illumination, are hampered by interference effects arising from multiple reflections from interfaces between silicon and buried oxide (BOX) layers. These cause false and inconsistent defect readings, and reduce overall defect sensitivity. Traditional, visible-wavelength wafer inspection systems will no longer have the capability to capture the smallest

Increased sensitivity Beginning with the first goal, increasing the defect detection sensitivity was addressed in several ways, in accordance with the following well known scattering equation.2

where dP/dΩ is the power within any given solid angle, Pi is the incident power, λ is the wavelength of the radiation, θi and θs are incident and scattered angles, Summer 2004

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respectively; Q is a polarization factor, and PSD is the power spectral density. First, the visible-light laser of the Surfscan SP2’s predecessor, the Surfscan SP1, was replaced with ultraviolet (UV) illumination. The new laser delivers a shorter wavelength at significantly higher power, and the Surfscan SP2 offers smaller spot sizes, which together increase the power density delivered to the defect site. Finally, the solid angle spanned by the collection optics, Ω, has been increased so that more of the scattered light from the defect is captured. As a result, the Surfscan SP2 typically detects a 200x increase in scattering intensity over the Surfscan SP1, making it fully capable of meeting the defect detection specifications shown in Tables 1 and 2. Supporting evidence is given by Figure 2, which demonstrates the strong capture of 38 nm polystyrene latex spheres (PSLs) on an epitaxial Si wafer.

Throughput vs. Sensitivity for Edge Handling Configuration 90 nm node 65 nm node Sens Spec Sens Spec SP2

Throughput (wph)

SP1DLS SP1TBI

Sensitivity (nm) Figure 3. Comparable sensitivity can be obtained operating either the

Higher throughput — lower cost of ownership

SP2 in high-throughput (HT) mode or the SP1 DLS in high-sensitivity (HS)

The second goal of the Surfscan SP2 program is to deliver significant improvement in cost of ownership. Throughput has been enhanced by introducing a faster handling system and data processing infrastructure. In addition, in many cases, the Surfscan SP2 can deliver the same or better sensitivity as the Surfscan SP1 but

mode—with greater than a fivefold increase in edge-handling throughput. In the example above, the sensitivity required for defect detection on polished wafers for the 65 nm node is the reference.

in a higher throughput mode, as shown in Figure 3. Such “spot migration” effects may result in more than a fivefold throughput increase for 65 nm node wafer qualification and more than a twofold or threefold throughput increase for tool qualification and monitoring, depending on layer. A related element to throughput is time-to-results. After the defects have been captured, they often must be classified before they provide useful information. In addition to real-time defect classification (RTDC) based on the angular distribution of the scattering signals, the Surfscan SP2 provides improved defect coordinate accuracy for faster, easier review by a scanning electron microscope (SEM) or atomic force microscope (AFM). New hardware and new calibrations enable a more than a twofold improvement in defect coordinate accuracy over the Surfscan SP1DLS at comparable throughput. Faster defect review means that the root cause of a defect issue can be found more quickly.

Figure 2. New SP2 inspection system demonstrates capture of 38 nm polystyrene latex spheres (PSLs) on an epitaxial silicon wafer. The different sizes of PSLs are color-coded, with the white spheres representing the 38 nm particles.

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Besides throughput, cost of ownership is strongly dependent upon parameters related to stability and reliability. For this reason KLA-Tencor worked with a partner company to develop a UV laser specifically for this application. The Surfscan SP2’s air-cooled laser was developed to have a long lifetime and exceptional stability. This laser is also extendible to even higher power, should it be required for future nodes.

The third goal of the Surfscan SP2 program—sensitivity on engineered substrates independent of top-layer and BOX-layer thickness—will be discussed in the section on engineered substrates, below. Applications of the Surfscan SP2 fall into three general categories: process tool qualification and monitoring; process control of engineered substrates, such as SOI; and process control of traditional substrates, such as polished silicon and epitaxial silicon wafers.

Defect detection requirements on films Integrated circuit manufacturers have forecast defect detection requirements according to whether defects occur in critical front-end of line processes, or back-end of line processes. The results are summarized in Table 1 as a function of design rule in PSL equivalent size. NODE (nm)

Rule

FEOL critical processes (nm) BEOL (mm)

~0.6-0.8*DR ~1.5*DR

55-70 140

40-50 100

30-36 70

<30 50

Table 1. Defect detection requirements by node for critical front-end of the line (FEOL) processes and back-end of the line (BEOL) processes.

Process tool qualification and monitoring

Economic pressures necessitate that fab ramps be accomplished in the minimum possible time. New process equipment must be qualified quickly in order to begin making product wafers and profits as soon as possible. Efficient and effective process tool qualification and monitoring have begun to receive more attention from yield groups and fab managers. The defect performance of fab equipment is a key to fab profitability. As chip makers begin to manufacture devices having smaller critical dimensions, what is identified as a critical defect becomes smaller as well. Figure 4 shows various sized particles at the 130 nm node, and their impact at the 65 nm node. This clearly illustrates the need for increased sensitivity. Furthermore, new materials and new processes have always introduced new defect types. A prime example of this is the introduction of copper voids that accompanied the transition from aluminum to copper interconnect material. The new defect types must be detected, identified, traced back to their source, minimized, and then monitored. Detection of new defect types requires the best possible sensitivity, since it is not possible to tune the system to capture defect types that are as yet unknown.

Defect size is referenced to PSL equivalent.

The Surfscan SP2’s design provides significantly improved sensitivity on all film types. Figure 5 shows scattering intensity as a function of oxide (a) or nitride (b) thickness, for both the Surfscan SP2 (UV) system and the Surfscan SP1 (visible-light) system. What this figure demonstrates is that the scattering intensity measured by the Surfscan SP2 is about 100 times stronger for all thicknesses of oxide and nitride. The superior defect sensitivity of the Surfscan SP2 over the visible-light system arises from the combination of the Surfscan SP2’s UV laser and optics, optical filters and advanced algorithms. Table 2 shows typical sensitivity improvements seen on different film types with SP2 versus SP1. Process control of engineered substrates

SOI, the first example of an engineered substrate addressing mainstream MOSFET requirements, consists of a silicon wafer with a thin layer of oxide buried within it (Figure 6). This layer is created either by oxygen implantation or by bonding two wafers, with the interface oxide becoming the % SP2 Sensitivity Layer

130 nm node–130 nm 1/2 pitch DRAM 130 nm

260 nm

65 nm

Pitch

65 nm node–65 nm 1/2 pitch DRAM 130 nm

65 nm 32 nm

130 nm Pitch

Organic Low k SOI Nitride Oxide Oxide CMP Bare Silicon EPI Silicon Copper Gate Poly

Improvement 40-60% 40-60% 30-50% 30-50% 25-40% 25-35% 20-30% 15-30% 10-30%

Figure 4. The difference in impact of various sized particles at the 130 nm node, and at the

Table2. Typical sensitivity improvements seen

65 nm node.

with SP2 over SP1 during SP2 characterization.

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Calculated Scattering Signal of PSL vs. Oxide Thickness

Calculated Scattering Signal of PSL vs. Nitride Thickness 1 Scattering Intensity (arb. units)

Scattering Intensity (arb. units)

0.1 SP2 SP1 0.01

0.001

0.1 SP2 SP1 0.01

0.001 0

200

400 600 Oxide Thickness (nm)

800

1000

200

400 600 Nitride Thickness (nm)

800

1000

Figure 5. Calculation of scattering signal as a function of (a) oxide and (b) nitride thickness for both the Surfscan SP2 (upper cur ve) and Surfscan SP1 (lower cur ve) for a 40 nm polystyrene latex sphere (PSL). Note that for all dielectric thicknesses the Surfscan SP2 signal exceeds the SP1 signal by ~100x.

buried oxide (BOX) layer. The result is a composite substrate having a top silicon layer, where active transistors will be manufactured, isolated from the bulk silicon. The BOX layer functions as a barrier to reduce electrical leakage from the transistors. SOI substrates also eliminate “latch up” between CMOS devices and decrease the effect of parasitic capacitance by providing superior isolation between adjacent devices. In the past five years, the use of SOI substrates has contributed to making faster, more power-efficient laptop and desktop computers, workstations and servers; wireless communications devices; integrated optical components; and automotive electronics. The other advanced composite substrates rely on introducing germanium, silicon-germanium films (Figure 7), and/or strained silicon (Figure 8). All of these techniques

have a single goal: to increase the electron and hole mobilities of the top film, which then translates into increased MOSFET performance. Perhaps the two most promising materials of this class on the near horizon are ultra-thin strained SOI, and GeOI. Ultra-thin strained SOI is expected to be critical for fully depleted MOSFETs at 45 nm. GeOI substrates show great promise beginning at the 45 nm node for high-speed logic applications; in fact, they may speed transistor switching by as many as four times that of comparable silicon devices. Many IC manufacturers are currently evaluating such substrates, to understand their benefits for the 45 nm node and beyond. The Surfscan SP2 has Silicon

“Strained” silicon

Silicon germanium

Top or active Si layer Buried Oxide: "BOX" Figure 7. When germanium is introduced to make a SiGe film, the

Bulk Silicon

lattice constant grows in proportion to the fraction of Ge present (left). As the lattice constant increases, the electron and hole mobilities increase. If silicon is grown epitaxially on top of a SiGe film, the

Figure 6. SOI wafer, a silicon wafer with a thin layer of oxide

lattice constant of the Si film will be increased, resulting in “strained”

(“BOX”) buried within it.

silicon, with increased mobilities. Source: IBM Corporation.

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Current Flow

Faster electron flow

Normal Silicon Lattice

Strained Silicon Lattice

Figure 8. Strained silicon lattice increases the flow of electrons and holes, resulting in increased transistor performance.

Fab area 1

Fab area 2

Polished Wafer Ingot pulling Slicing Lapping Etching Polishing Defect Inspection Final Polish Final Clean Defect Inspection

been involved in many of these evaluations, in helping to uncover and understand defect mechanisms.

Strained Silicon Transistors

Normal electron flow

EPI Wafer Ingot pulling Slicing Grinding Etching Polishing Defect Inspection Final Polish Final Clean Defect Inspection Clean EPI Si growth Defect Inspection

The industry also has a near-horizon need for SOI having a thinner top silicon layer. Wafer manufacturers are currently working to produce production volumes of XUT SOI wafers having a top silicon layer less than 50 nm thick, for 65 nm node applications. Challenges include thickness uniformity of the top silicon layer, which is specified at an accuracy of 1 nm because it is tightly correlated with device performance in a fully depleted transistor architecture, and defect detection and control.

SOI process flow and defect types Both the SIMOX SOI process and the bonded SOI process have many more steps than the traditional silicon or epitaxial silicon wafer manufacturing processes. Strained silicon wafer manufacturing has an intermediate sSi Ingot pulling Slicing Grinding Etching Polishing Defect Inspection Final Polish Final Clean Defect Inspection Clean Graded SiGe EPI Polish Defect Inspection Relaxed SiGe EPI Defect Inspection sSi EPI Defect Inspection

SIMOX SOI Ingot pulling Slicing Grinding Etching Polishing Defect Inspection Final Polish Final Clean Defect Inspection Clean Defect Inspection Implant Defect Inspection Implant Defect Inspection Implant Defect Inspection Anneal Final Clean Defect Inspection

Bonded SOI Ingot pulling Slicing Grinding Etching Polishing Defect Inspection Final Polish Final Clean Defect Inspection Clean Defect Inspection Oxidation Defect Inspection Implant Defect Inspection Bond Anneal Split Clean Defect Inspection Polish Final Clean Defect Inspection

Table 3. Simplified process flows for traditional polished silicon wafer, epitaxial silicon wafer, strained silicon wafer, and both SIMOX and bonded SOI wafers. The comparison also shows the relative numbers of defect inspections required by the different processes.

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number of process steps. Table 3 compares a simplified version of the process flows of the various wafer types. Because SOI processes have many more process steps than traditional silicon wafers, two to four times as many defect inspections are necessary. For this reason, throughput of the wafer inspection system is of primary importance for SOI wafer manufacturers, as throughput will contribute strongly to the inspection systemâ&#x20AC;&#x2122;s cost of ownership. To meet IC manufacturing sensitivity requirements at the 65 nm and 45 nm nodes, SOI wafers and other engineered substrates need to have a thin, defect-free top silicon surface, high top-layer thickness uniformity and a high-quality buried oxide layer. Leading materials challenges include top-layer thickness uniformity, BOX thickness uniformity, and critical defects including top silicon voids, and other surface defects generally associated with traditional silicon that affect device performance. An example of a SOI top silicon void defect is given in Figure 9. Many of the SOI defects are traceable to particles trapped in the multilayered structure during processing, or at the surface during implantation. Optimization of wafer processing and cleaning Figure 9. SEM image of a top silicon steps, followed by void. This is a defect type specific to monitoring for defects, SOI. is essential to production of SOI wafers that will meet the needs of integrated-circuit manufacturers for the 65 nm and 45 nm nodes.

Substrate Type/NODE(nm)1/2 pitch

Bare Si sensitivity (nm) Epi sensitivity (nm) SOI sensitivity (nm)

65 100 100

50 90 90

40 65 65

35 45 45

Table 4. Defect detection requirements by node for traditional bare silicon wafers, epi wafers, and SOI wafers. Defect size is referenced to PSL equivalent.

epi inspection in order to detect all critical defect types.

Where traditional wafer inspection falls short Inspection of engineered substrates, such as SOI, poses problems not encountered in bulk substrates. The layered nature of the substrates, together with the visible wavelengths used in traditional wafer inspection systems, results in interference between signals from underlying layers affecting defect sensitivity (Figure 10). As a result, traditional wafer inspection systems will deliver defect sensitivity that varies with SOI layer thickness. Figure 11 illustrates the problem using KLA-Tencorâ&#x20AC;&#x2122;s own Surfscan SP1DLS system. A visible wavelength will penetrate the top layer and BOX layer of the SOI substrate, and reflections from the interfaces will interfere constructively or destructively at the collectors, depending on the thicknesses of the individual layers. Figure 6 shows the variation of scattering intensity on a log scale, as a function of active Si layer thickness, with BOX thickness held constant at 145 nm (a common thickness in use today). S polarization shows a dramatic fluctuation in scattering intensity, traversing three orders of magnitude. P polarization is a better

Vis Lig ible ht

Interference at collection optics

SOI defect detection requirements In terms of defect detection requirements, engineered substrates essentially are treated like traditional silicon wafers. As the nodes advance, defect requirements tighten. The following table captures defect detection requirements by node, comparing traditional silicon wafers with SOI:

Top layer Si BOX layer Bulk Si

Figure 10. Inspection of layered substrates, such as, SOI poses problems not encountered in bulk substrates. The layered nature of the substrates,

Defect detection requirements for SOI wafers are identical to those for epi wafers. That is, defects sized close to the design rule must be detectable. One difference is that normal illumination incidence is a requirement for 20

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together with the wavelength used in conventional wafer inspection systems, allows interference between signals from underlying layers to affect the defect sensitivity. As a result, conventional wafer inspection systems will deliver defect sensitivity that varies with SOI layer thickness.

Penetration Depth (Âľm)

Scattering Intensity (arb. units)

100

P polarization

0.01

S polarization

0.001

Si Penetration Depth

Calculated Scattering Intensity vs. SOI Top Si Thickness (145 nm BOX; 488 nm wavelength)

0.1

<360 nm

1 0.1 0.01

Top Si Thickness Roadmap

0.001 0

100

200

0.0001

300

400

500

600

700

800

900

Wavelength (nm)

Figure 13. Relationship between silicon penetration depth and illumi-

0.00001

nation wavelength. With a wavelength <360 nm, the SP2 laser beam 0.000001 0

100

Top Si Thickness (nm)

exactly as a polished silicon wafer.

Figure 11. Variation of scattering intensity as a function of active Si layer thickness, with BOX thickness held constant at 145 nm, for the 488 nm SP1 DLS inspection system. S polarization shows a dramatic fluctuation in scattering intensity, traversing three orders of magnitude. P polarization is a better choice for SOI inspection under these conditions, giving a higher overall response, with variation in scattering intensity reduced to a factor of 10.

choice for SOI inspection under these conditions, giving a higher overall response, with variation in scattering intensity reduced to a factor of 10. For other BOX thicknesses, different top-layer silicon thicknesses may provide optimal scattering responses for defect detection, as shown in Figure 12. P polarization continues to provide both a higher overall scattering response and a more uniform response. These

results will shift for systems using other visible-light wavelengths; however, P polarization will always provide more uniform results than S polarization. In all cases, separate recipes will need to be created whenever top-layer or BOX-layer thickness is changed. Note that the SOI top thickness is customized for each IC customerâ&#x20AC;&#x2122;s application, making recipe and calibration curve management a priority for wafer manufacturers. Recipe and calibration curve creation and management add complexity and cost to the manufacturing process. A more elegant solution is to design a system which treats the top silicon layer as opaque, and thus provides sensitivity independent of any variation in top-layer or BOX-layer thickness.

Sensitivity independent of SOI thickness

Scattering, S-pol (arb. color scale)

Scattering, P-pol (arb. color scale) 200

200

150

BOX Thickness (nm)

penetrates only the top layer of Si, so that the SOI wafer behaves

100

0 0

20 40 60 80 Top Si Thickness (nm)

100

20 40 60 80 Top Si Thickness (nm)

100

Figure 12. Scattering intensity as a function of both top silicon thickness and BOX thickness, for the 488 nm SP1 DLS system. P polarization (left) continues to provide both a higher overall scattering response and a more uniform response. These results will shift for systems using other visible-light wavelengths; however, P polarization will always provide more uniform results than S polarization. In all cases, separate recipes will need to be created whenever top-layer or BOX-layer thickness is changed.

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Addressing the third goal of the Surfscan SP2 program, Figure 13 shows the relationship between silicon penetration depth and illumination wavelength. With a wavelength of less than 360 nm, the Surfscan SP2 laser beam penetrates less than 10 nm of the top layer of Si, so that the SOI wafer behaves exactly as a polished silicon wafer. SOI top-layer silicon thicknesses today are on the order of 55 nm, with roadmaps indicating that this number may reach 10 nm within 5-8 years. This means that the Surfscan SP2 delivers, and will continue to deliver, constant defect sensitivity, independent of top-layer

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Calculated Scattering Intensity vs. SOI Top Si Thickness (145 nm BOX) Scattering Intensity (arb. units)

1 0.1

engineered substrates as well. The Surfscan SP2 enables the entire engineered substrate roadmap, and allows these substrates to be manufactured cost-effectively.

P polarization

Process control of traditional polished silicon and epi substrates

0.01

S polarization

0.001 0.0001 0.00001

55 nm

70 nm

88 nm

0.000001

100

Top Si Thickness (nm) Figure 14. The scattering responses for S and P polarizations as a function of active-layer silicon thickness for the SP2 system illustrate its flat response to top-layer silicon thickness.

(and BOX-layer) thickness. One recipe can be used for all SOI thicknesses within a given SOI process, diminishing the time-consuming recipe management and costly calibration-curve needs.3 Figures 14 and 15 show the scattering responses for S and P polarizations as a function of active-layer silicon thickness and BOX layer thickness. Figure 16 shows detection of 60 nm PSL spheres on three thicknesses of top-layer silicon—all virtually identical results. The penetration depths of strained silicon and various compositions of SiGe at the wavelength of the Surfscan SP2 are also about 10 nm or less. Therefore, the benefits that the Surfscan SP2 provides to SOI extend to other

With none of the pizzazz of exotic new materials or engineered substrates, traditional polished silicon wafers and epitaxial silicon wafers will nonetheless benefit tremendously from the technology of the Surfscan SP2. SP2 enables the defect sensitivity requirements of Table 2 to be met through the 45 nm node for both types of wafers, with extensions planned for the 32 nm node. Throughput enhancements from hardware and software changes as well as by means of spot migration, will benefit manufacturers of traditional wafers directly in cost of ownership. Calculations show that spot migration effects together with wafer handling improvements may result in as much as a fivefold throughput increase for 65 nm node wafer final inspection. Conclusions

With new engineered substrates; gate materials and geometries changing radically in the front end; and organic low-k dielectrics appearing in the back end, the 65 nm and 45 nm nodes promise to be a challenge for defect detection. Today’s inspection systems, built with visible-light optics, will fall short of meeting defect detection requirements for many of the new substrates and new films for these nodes.

BOX Thickness (nm)

The Surfscan SP2 inspection system has been introduced to fulfill a need for higher sensitivity and higher throughput Scattering, P-pol (arb. color scale) Scattering, S-pol (arb. color scale) inspection at the 65 nm and 200 200 45 nm nodes, with extendibility to the 32 nm node. With its 150 150 UV technology it can provide the sensitivity required to meet IC manufacturers’ and wafer 100 100 manufacturers’ requirements for these nodes. Throughput 50 50 enhancements allow it to accomplish these inspections with up to a fourfold cost of 0 0 0 20 40 60 80 100 0 20 40 60 80 100 ownership decrease for the Top Si Thickness (nm) Top Si Thickness (nm) 65 nm node compared to the system’s predecessor, the Figure 15. The scattering responses for P (left) and S (right) polarizations as a function of active-layer silicon Surfscan SP1DLS. For engineered thickness and BOX thickness for the SP2 system. Above a top-layer silicon thickness of 20 nm the scattering substrates, the use of UV response is virtually independent of SOI layer thicknesses. Summer 2004

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Figure 16. SP2 detection of 60 nm PSL spheres on three thicknesses of top-layer silicon on SOI wafers (indicated by vertical magenta lines on Figure 14) using P polarization. All give virtually identical results, confirming the model predictions of Figure 14.

illumination at <360 nm wavelength allows high sensitivity to be achieved independent of top-layer and BOX-layer thickness, and without changing recipes within a given process. Finally, a twofold improvement to the defect coordinate accuracy facilitates SEM or AFM review, allowing more rapid determination of root cause.

References 1. David Baldwin, â&#x20AC;&#x153;65 nm Production Sets New Challenges for TSMC, UMC,â&#x20AC;? Nikkei Electronics Asia, January 2004. 2. Stover, John C., Optical Scattering: Measurement and Analysis, McGraw Hill, New York (1990). 3. Assuming surface roughness is reasonably similar.

KLA-Tencor Trade Show Calendar September 1

IC China, Shanghai, China

September 13-15

SEMICON Taiwan, Taipei, Taiwan

September 14-15

BACUS, Monterey, California (USA)

September 21-22

Diskcon USA, San Jose, California (USA)

September 27-October 2

SEMICON Expo CIS, Moscow, Russia

October 6

FSA, San Jose, California (USA)

For a more up-to-date calendar, please go to: http://www.kla-tencor.com/events Winter 2004

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