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The Dollar Value of Accelerated Shrinks Kevin Monahan, Adil Engineer, Georges Falessi, Matt Hankinson, Sung Jin Lee, Ady Levy, Mike Slessor, KLA-Tencor Corporation
Previously, we have developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.
Introduction
In this work, we use a simplified microeconomic model for the profitability, or rate of profit, generated by the semiconductor manufacturing processi. Let P = −R +
∑ WT (Y y d b i
i i i ij pij
−bij Ci )
ij
where R is the factory overhead rate, W is the number of wafer starts, T is the time interval, Y is the metrology-limited yield entitlement, y is the die yield expressed as a fraction of the entitlement, d is the number of dies per wafer, b is the bin yield expressed as the fraction of good dies in each performance bin, p is the average selling price per die, C is the manufacturing cost per wafer, i is the product index, and j is the bin index. This business model represents the gross rate of profit attributable to a factory. It does not include variable costs associated with packaging, marketing, or sales of the product. Some of the basic strategies for maximizing gross profit are discussed below. The first term represents the fixed costs associated with capital investment, operation,
and depreciation of the facility that are independent of capacity utilization. The traditional strategy for minimizing the relative contribution of fixed costs is to reduce manufacturing cycle time and operate near maximum capacity. In a supply-limited environment, this means filling the factory with the highest margin products. Demand-limited environments may induce loading the factory with low-margin products. Such cases reduce average gross margins and can generate actual losses during times of rapid price erosion. Table 1 shows April 2001 estimates of yield-normalized cost per die, revenue per die, revenue per megabit, and revenue per wafer for several DRAM products. The 16-, 64-, and 128-megabit chips were nearly perfect commodities at one dollar per 16 Mb. Gross margins were negligible for 180 nm design rules. Since April 2001, average selling prices have sunk below the cost of manufacturing2. Table 1
Cost and Revenue in Dollars
Date: 4/12/01 16Mb SDRAM 64Mb SDRAM 128Mb SDRAM 128Mb DDR 128Mb RDRAM 256 Mb SDRAM
Cost($) 1.00 2.00 4.00 5.00 6.00 8.00
Price($) $/16Mb 1.02 1.02 2.15 1.08 4.35 1.09 7.90 1.98 10.00 2.50 13.95 1.74
$/Wfr 2040 2150 2175 3950 5000 3488
Gross Margins 180 nm 0.02 0.15 0.35 2.90 4.00 5.95
150 nm 0.33 0.76 1.57 4.43 5.83 8.39
Table 1.
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Inspection of the table shows that DRAM profitability can be recovered in at least three ways:
• Increased capacity: 256 Mb memory prices are falling, but they currently sell at a per-bit premium relative to 128 Mb memory. • Increased density: At constant yield, shrinks improve margins by decreasing the cost per die (e.g., 30 percent for a 180 to 150 nm shrink).
+185
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• Increased performance: 266 MHz double data rate (DDR) memory sells at a per-bit premium compared to 133 MHz (SDR) memory.
Spot Prices per 128 Mb 16 14 12 10 8 6 4 2 0
128Mb DDR-266 256Mb SDRAM 128 Mb SDRM
+107
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Figure 1. In 2001, DRAM spot prices declined eight-fold in six months. The ASP advantage for DDR SDRAM and 256 Mb SDRAM declined from 185 and 107 percent to 32 and 29 percent, respectively.
Microeconomics of shrinks
The second term in the profitability equation above is the rate of revenue, adjusted for manufacturing cost per wafer. For the sake of simplicity, we can ignore speed bins (b) and estimate a yield-normalized die cost (c) given by ci ≡
1 Ci S2 Ci ≅ Yi yi di yi d0i D2 Yi
[ ][ ]
Here, S is the shrink ratio (e.g., 150 nm/180 nm), D is the wafer diameter ratio (e.g., 300 mm/200 mm), and d0 is the initial density. Substituting into the profitability equation, the term to the right of the sum becomes the product of salable die output and the variable margin for each product:
T∑ i
P = −R + 1
Wi di Yi yi −(pi −ci)
As shown above, the normalized die cost in the second term falls off sharply with larger wafer size, improved yield, and smaller design rules. For the purposes of this work, a demand-limited market is defined as a nearly constant revenue opportunity for a given product, so that excess production results in a reduction of average selling price as shown in Figure 1. • The benefit of increased wafer size is lower die cost, offset by excess production-driven price reductions and the cost of 300 mm facilities and equipment. • The benefit of a metrology-driven shrink is lower die cost, offset by the cost of the metrology, statistical analysis, control applications, and an advanced process control framework.
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The investment required for metrology-driven die-cost reduction is 1-2 orders of magnitude lower than that required for 300 mm solutions, with the notable exception of existing pilot lines. Clearly, existing 200 mm factories must pursue aggressive die-cost reduction or face closure. The most economically defensible strategies will leverage metrology-driven shrinks initially, followed by ramp of 300 mm lines as the market recovers. Metrology-driven shrinks
The bulk of this paper is dedicated to the systems, tools, software, and methodology required for enabling metrology-driven shrinks. In order to maintain yield, one full generation of design-rule shrink (0.7x) requires a 30 percent reduction in CD and overlay variation, plus a large drop in the levels of macro and micro defects. For the purpose of this work, we shall focus on factorywide systems that enable shrinks by improving CD control in the lithography and etch areas. In the near future, performance of such systems will not be measured at the component level (e.g., metrology precision). Instead, performance will be measured at the systems level, with the metric being improvement in CD variation given a specified process capability. Since these specifications must be data-driven, rigorous factorywide stochastic analyses will be required beforehand. Currently, such stochastic analyses are provided as a service to support factory-wide sample planning and advanced process control (APC). Key steps in the implementation of a factory-wide gate CD Control System (CD-CS) are outlined below:
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Figure 2. An APC scheme incorporating feedback and feed-for ward of post-development CDs, feedback of etch CDs, and feedback of etch-time to adjust the CD target in the lithography cell.
• Utilize factory-wide, generalized, nested ANOVA to separate systematic and random, plus spatial and temporal, components of variation by site, field, wafer, lot, and cell. Determine the overall process capability and CD control opportunity. • Utilize factory-wide APC simulation to evaluate model-based, feed-forward and feedback control as a means of reducing temporal CD variation in cell-tocell, lot-to-lot, or wafer-to-wafer data. Determine the specific APC opportunity. • Implement the factory-wide APC framework, conforming to SEMI E-93 standards (Catalyst). Facilitate control system integration (Figure 2). • Implement a pre-integrated CD Control System consisting of SEM or spectroscopic CD tools, data and recipe server, data analysis modules, and basic control applications. Optimize tool-specific control applications. DRAM CD control opportunities
DRAM shrinks are limited by the requirement for tight control over the physical parameters that affect the physics of the device. An approximate expression3 for saturation current in an MOS transistor illustrates this problem: Ids ≅ W • µ • ε •(Vgs - Vth)2 2 L D
( )( )( )
Here, W is the gate width, L is effective gate length, µ is the carrier mobility, D is the thickness of the gate
dielectric, ε is the permittivity of the gate dielectric, Vgs is the gate voltage, and Vth is the threshold voltage at which switching begins to occur. At small L, shortchannel effects reduce Vth non-linearly, so that small variations in L have large effects on current. Matching of L-effective is, therefore, critical to the operation of differential circuits such as the sense amplifiers and comparators used in memory devices. Moreover, the equation above is an approximation; leakage current does not go to zero in the sub-threshold region. At small L, variations in L can have large effects on leakage from the DRAM storage nodes. Due to these and other parametric limitations, the DRAM roadmap for 1 Gb production has fallen off the historical trend line, and further attempts to lower bit-cost are at risk4. As a result, control of L-effective in DRAM is becoming more important as design rules decrease and as performance requirements increase.
Advanced Analytical Methods Gate CD control for DRAM is quite different from that seen in logic factories. Lithography cells are not specifically dedicated to gate layers. For the purpose of controlling overlay, cells are typically dedicated to a series of critical layers on a specific product. These usually include the active, gate, contact, and first-metal layers. Each critical layer is aligned and exposed using the same stage and lens. Therefore, CD control in a high-volume DRAM factory entails controlling cell-tocell variation over a large number of lithographic cells. In addition, the etch processes used in DRAM manufacture may induce more field-to-field variation across the wafer and more site-to-site variation across each field. Generalized ANOVA is required to identify the Winter 2002
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exposure dose. In the case of etching, adjustments are typically made to etch-time.
ANOVA 3.69 0.42 NEG 8.50
Table 2.
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Feed forward corrections for random error. After resist patterns are developed, “random” CD errors become systematic and may be corrected by adjusting parameters such as etch-time.
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sources of correctable systematic variations, as shown in Table 2 above: Without generalized ANOVA, systematic and random errors are confounded (right-hand column). As a result, a semiconductor manufacturer could make the costly and erroneous conclusion that he had achieved entitlement for his process toolset.
After a pattern is etched, CD errors are not correctable; there is no subsequent patterning step. If the CD errors arise from chamber offsets, one could adjust the etch-time of individual chambers.
Ideally, more than 80 percent of a generic APC script should be re-useable anywhere in the factory. Otherwise, unique code will be created for each application.
Advanced Process Control
Factory-Wide Framework
The essence of advanced process control (APC) is the automated correction of systematic process error. The strategy of APC is to de-confound and correct as much systematic error as possible. Several tactics can be employed to support this strategy, as shown in Figure 2.
CD control systems for DRAM require multiple integrations of control applications, metrology tools, and process tools for both lithography and etch cells. The implementation of a standard factory-wide APC framework solves this problem. With a framework, the task of integrating with the factory MES system is performed only once.
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Feed back corrections for systematic error.
Catalyst APC Framework
MES/ Equipment Manager
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Figure 3. Open factor y-wide framework for advanced process control.
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The multiple data types provided by SCD enable both process and metrology fault detection. Without such information, profile variations that change L-effective could go undetected, compromising performance of the APC system and reducing die yield. The sub-nanometer matching and precision of SCD tools enables APC architectures for controlling critical dimensions below 50nm. Significantly above these dimensions, the contribution of metrology error would be negligible.
In addition to simplifying MES integration, the framework provides middleware for managing the complex interactions among the control executor, control database, control history, control documents, GUI workbench, and application interfaces. The middleware enables rapid extension of APC into overlay, etch, films, and CMP. It can also support integrated metrology and control on process tools. Failure to use a framework can generate recurring costs that persist for multiple product generations and compromise availability (e.g., >0.9999).
CD Process Window Monitors Advanced Metrology Tools
The algorithms used for CD-APC often depend on factors such as stepper focus offsets and illumination settings, which are not explicitly called out in the equations. For example, a generic proportional control algorithm with EWMA filtering (λ) might be written as
The L-effective of DRAM transistors is sensitive to both gate CD and gate profile. To address the need for CD and profile optimization, control systems based on spectroscopic ellipsometry have been developed to supplement the traditional SEM-based metrology. Spectroscopic CD tools (SCD) can measure CD, sidewall angle, height, and film thickness, simultaneously. Although measurements are made in 50-micron diffraction gratings located in the scribe lanes, line and space dimensions can be adjusted to mimic the proximity behavior of gate structures in either dense arrays or relatively isolated logic areas. Intra-field targets may be used when the economic benefits are compelling. Some typical SCD metrology results are shown in Figure 4.
Zn = Zn-1 −
λ [X − Xt] m n-1
where Zn is the updated process adjustment, Zn-1 is the last process measurement, Xt is the process target, and m is the estimate of the local slope of X as a function of Z. In the specific case of CD control, we could have Dosen = Dosen-1 −
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Figure 4. The high precision and multiple data types of SCD enable both advanced process control and CD process window monitor applications (CD-PWM).
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Klarity ProDATA Computed Best Focus (µm)
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• Advanced SCD and SEM systems that address CD and profile metrology requirements for APC
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Figure 5. PWM tracking of focus offsets on a 248 nm lithography tool. The residual 3σ is 12 nm. PWM is a web-enabled, automated system that can track common process windows and identify matched stepper groups across entire high-volume factories.
The stability of the APC algorithm depends on the estimate of the local slope (m), which in turn depends on the focus offset of the lithography tool. Periodic monitoring of the lithographic focus-exposure window is essential to detect process drift that could compromise the integrity of an APC system, particularly for the tight CD control requirements associated with 0.13 and 0.10 micron design-rules.
In the near future, we predict that factories will not be competitive without APC architectures that are based on factory-wide integration of network-enabled hardware, software, and control methodology. Considering the high return on investment provided by factory-wide APC architectures, semiconductor manufacturers are advised to continue such investments through industry downturns. This strategy will enhance the performance and extend the life of both current and future process tools, contributing to efficient use of scarce capital resources. Principal author biography
Dr. Kevin Monahan is a Vice President of Technology and Director of Parametric Solutions in the Customer Group of KLA-Tencor Corporation. His professional interests include patterning and parametric process control architectures for high-volume manufacturing. References
Conclusions
We have shown that, in most cases, metrology-driven shrinks are the most economic and effective means for reducing die-cost in demand-limited DRAM markets. We have also identified five technologies that can be combined to achieve shrink-enabling levels of CD control for sub-0.18 micron product generations: • Generalized ANOVA methods for identification of correctable, systematic CD error • Advanced control applications for automated correction of CD error in photo and etch cells • A factory-wide open framework to support integration and management of APC applications
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1. K. Monahan, G. Falessi, and A. Chatterjee, “Accelerated yield learning in aggressive lithography”, Proc. SPIE 3998, p. 492 (2000), Invited Paper. 2. Source: www.dramexchange.com 3. C. Meade and L. Conway. Introduction to VLSI Systems. Menlo Park: Addison-Wesley, 1980, pp 1-5. 4. K. Itoh. VLSI Memory Chip Design. New York: SpringerVerlag, 2001, pp. 1-99. 5. R. C. Elliott, R. K. Nurani, S.-J. Lee, L. Ortiz, M. Preil, J. G. Shanthikumar, T. Riley, and G. Goodwin, “Sampling plan optimization for detection of lithography and etch CD process excursions”, Proc. SPIE 3998, pp. 527 (2000) . A version of this article was originally published in the 2001 ISSM/IEEE proceedings International Symposium of Semiconductor Manufacturing Conference, October 8-10, 2001, San Jose, California, USA.