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Challenging the Monitor Reduction Paradigm to Reduce Costs by Randy Williams, Intel Corporation Sridhar Seshadri, Leonard N. Stern School of Business, New York University J. George Shanthikumar, Ph.D., IEOR Department, University of California, Berkeley Dadi Gudmundsson, Raman Nurani, Meryl Stoller, and Arun Chatterjee, KLA-Tencor Corporation
Increasing competition within the semiconductor industry is forcing many manufacturers to consider and implement aggressive cost reduction measures across many operations. In addition, defect inspection steps are often perceived as being “non-value add” metrology operations, and are frequently the primary focus for further monitor reduction and/or elimination to reduce operational costs. In this paper, the highlights of a joint research project between Intel Corporation and KLA-Tencor Corporation are discussed, with the primary focus on the use of advanced statistical and stochastic models. These models utilize defect, yield, and financial inputs to fully characterize the overall costs associated with the monitoring and control of random defect excursions in an advanced semiconductor manufacturing process. The Sample Planner program used for the evaluation proved to be an effective tool in challenging the paradigm of monitor reduction to achieve lower product costs in an advanced semiconductor manufacturing line.
The competitive environment in the semiconductor industry has prompted many manufacturers to examine their operations closely for potential cost reduction opportunities. A key area of leverage is to minimize the operational costs associated with metrology operations, especially since these metrology steps are frequently perceived as being “non-value add” process steps. This highlights the importance of correctly identifying those process activities that do not add significant value in semiconductor manufacturing and development, and then evaluating if these activities should be reduced in sampling frequency or eliminated. However, the actual value for these metrology operations is often dynamic, and the optimum inspection strategy is subject to change, based upon the process maturity and future yield learning. Figure 1 illustrates the typical life cycle of a defect monitor, as it evolves from its initial creation during product development, its 32
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employment as a critical monitor during the production ramp, its use as a process control monitor during full production, and finally to eventual monitor reduction and elimination as the production process reaches maturity. Because most defect monitors are indispensable during process development and ramp-up, these monitors are
F i g u re 1: Defect monit or life cycle.
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generally recognized as a value-added asset during these early operational phases. But as the production process matures, the value of most defect monitors becomes unclear. In order to address this issue, an advanced methodology called Sample Planner was developed by KLA-Tencor to assist in the development of cost-effective defect inspection sampling strategies, and to provide an accurate assessment of whether monitor reduction and/or elimination should be pursued for future cost savings in advanced semiconductor manufacturing or development. In this paper, the results from a collaborative project between Intel Corporation and KLA-Tencor are discussed. Several defect inspection scenarios and resource allocations were analyzed for an advanced semiconductor manufacturing process, in order to evaluate the defect inspection sampling plans for potential opportunities for defect monitor reduction and/or elimination. Although these monitor reduction efforts can often result in significant reductions in the defect inspection costs for product and/or test wafers, the associated risk and yield impact is often ignored or poorly assessed. In this project, Sample Planner provided an advanced methodology to evaluate the effectiveness of the current inspection sampling plan that was being utilized by Intel, and provided an accurate comparison to alternate monitor reduction scenarios. Solution methodology
The Sample Planner program is based upon advanced statistical and stochastic models developed to estimate the required defect inspection capacity, to provide an efficient allocation of defect monitors, and to optimize the sampling strategy for semiconductor fabs to control yield excursions. Until recently, these complex problems had only been partially addressed 1, and provided the motivation for ongoing research projects between KLA-Tencor and key semiconductor manufacturing partners. In this project, the primary parameters in Sample Planner include the type of in-line product inspection tools that are utilized, the defect inspection tool capacity, the placement of the defect monitors within the process flow, the inspection frequency and sampling plans, the critical parameters that are tracked and responded to through Statistical Process Control (SPC), fab logistics, and key financial data. All of these parameters are inter-related, and each one gives rise to an additional set of variables that needs to be comprehended for input into the model2. Overall, the problem is so complex that a comprehensive solution methodology did not exist until the development of Sample Planner, which can be used to quickly evaluate and develop an optimal defect inspection strategy with reasonable effort, accuracy, and confidence.
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The sampling problem grows even more complex, since a semiconductor fab’s inspection requirements are often dynamic, continuously evolving throughout a given fab’s operational phases. During the process development and yield learning phases, the inspection requirements are typically much higher than during the full production and process maturity phases. Defect excursion types and frequencies, production volumes, and device average selling prices are just a few of the key drivers that frequently change and affect the optimum inspection strategy for each operational phase. The outputs of Sample Planner, for a given inspection sampling plan, include the yield impact for each defect monitor, the material at risk, the cost impact due to defect excursions, the cost of root cause analysis and corrective action, and the cost of reacting to non-excursions (false alarms). In addition to helping guide engineering and development resources to determine optimum defect inspection sampling plans, Sample Planner can also be used to evaluate future sampling strategies as a given fabrication process matures, or prior to the implementation of future semiconductor processes or tools. Monitoring requirements
It has become well accepted that defect inspection tools are a critical component in the yield management strategies for advanced semiconductor manufacturing and development. However, when the defect monitors are not used to guide process development, or to assist in the identification of specific yield issues, the value of the defect monitors is not as tangible, and is more difficult to assess. Consequently, the required inspection capacity, and the corresponding optimal inspection sampling plan, are difficult to assess with any reasonable degree of certainty. The optimal sampling plan actually results from the trade-off between the total inspection costs for all of the defect inspection operations, and the resulting yield impact due to defect excursions that will be missed by the inspection sampling plans. Fortunately, the inspection costs associated with a particular inspection sampling strategy are much easier to quantify than the resulting excursion costs. The inspection costs include the actual costs associated with the implementation of the defect inspection monitors, which includes the depreciation of the inspection tools, direct and indirect labor, service contracts, vendor training, and spare parts. This total cost is then allocated across all of the defect inspection monitors according to the wafer and lot sampling rates that are utilized for each defect monitor.
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Excursion control
The Sample Planner program is designed to evaluate and enhance the excursion control methodologies that are employed in advanced semiconductor manufacturing and development. The program models the inspection costs that are required to detect defect excursions, and the costs incurred by the yield impact from the defect excursions. In its simplest form, the cost model methodology is based upon a recurring in- and out-of-control cycle that occurs at each monitor step in the process, as shown in Figure 2. A new cycle starts when a given monitor in the process is assumed to have an in-control mode of operation, and a corresponding baseline product yield level. After a random length of time, an excursion takes place at one of the defect monitor steps, causing an impact to product yields. At this point, the inspection sampling strategy determines how quickly the excursion will be detected and fixed, and the in-and out-of-control cycle is re-initialized. In order to minimize the resulting yield impact and financial loss from a defect excursion, the excursion must be quickly detected, and the necessary corrective action must be taken. The ability to detect an excursion quickly (by minimizing the detection delay) is governed by the existing inspection capacity and the allocation between all of the defect monitors, which is the essence of the cost tradeoff analysis that is performed. However, this approach does not account for any additional benefits that can be derived from the use of the defect monitors to assist in baseline yield improvement efforts.
program, and Intel provided the required inputs and proposed scenarios that were needed for the analysis†. After a sufficient amount of data was collected to establish statistically valid sampling parameters for the defect monitors being evaluated, the data was processed using statistical models and hypothesis tests to quantify the mean and variance of defect levels during in- and out-of- control states, excursion types, and the excursion frequency. The next step in the project was to assess the relative importance of each defect monitor, by determining the excursion loss experienced by each monitor. The “excursionary” yield impact is dependent upon the excursion frequency, the duration of the yield excursion, and the projected yield impact during the defect excursion. Obviously, the higher the excursion rates and/or projected yield impact, the more critical the defect monitor is in the overall defect inspection sampling plan. Results from this project revealed significant differences in both the excursion frequency (Figure 3) and the observed yield impact resulting from defect excursions for the selected defect inspection monitors (Figure 4). Sample Planner uses a stochastic algorithm to process the input data to calculate the overall inspection costs, and the associated costs for each defect monitor in the inspection sampling plan. The cost for each monitor is composed of the costs due to the inspection operations and the resulting excursion losses. Based upon the results of this project, the excursion costs were found to be dominant, and accounted for greater than 80 percent of the total costs associated with the defect inspection monitors. These results are reflective of the inspection strategy that is required for an advanced semiconductor
F i g u re 2: Fund amen tal parameters of sa mple plann er.
Defect monitor assessment
F i g u re 3: Monitor excurs ion fre q u e n c i e s .
A key use of the Sample Planner program was to evaluate the effectiveness of the current defect inspection sampling plan employed by an advanced semiconductor manufacturing line at Intel. In a joint project, KLA-Tencor provided access to their proprietary Sample Planner
† All data disclosed in this paper has been filtered and normalized to maintain confidentiality, while ensuring that the presented data continued to represent the key observations and results of this project. In reality, additional defect monitors were also included in the actual evaluation.
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F i g u r e 6: Moni tor excursion fr equen cy vs. yield i mpact. F i g u re 4: Moni tor yield impact.
manufacturing process, and the excursion costs may be significantly lower for more mature semiconductor processes. Upon evaluation of the three previous graphs (Figures 3, 4, and 5), it becomes evident that defect monitors D and F have relatively low overall costs, due to the relatively low sampling costs, excursion frequencies, and projected yield impact. Consequently, these monitors should be considered as current or future candidates for sampling reduction or elimination. Conversely, the excursion costs (material at risk) will increase significantly with the reduction in sampling or elimination of any of the other defect monitors (A, B, C, and E).
frequencies and high yield impacts are easily observed (monitors B and E). Conversely, the defect monitors that have a low excursion frequency and low yield impact are “non-critical” monitors (monitor F), and should be considered for future monitor reduction or elimination. The remaining defect monitors appear as either “high impact” (monitors C and D) or “excursionary” (monitor A), based upon the relative excursion frequencies and yield impacts. This graphical approach can be quite useful. As an example, critical monitors that exhibit a higher excursion frequency (higher out-of-control rate) and/or larger yield impact, should require a greater sampling rate to detect the defect excursions to minimize the material at risk. Some care should be taken in the interpretation of the other defect monitors, since the separate quadrants show only the relative importance between the various defect monitors. In order to accurately assess the importance of the defect monitors, the absolute levels for the excursion frequencies and yield impact needs to be considered. However, the scatter-plot approach can serve as a helpful guide for allocating more inspection capacity for the critical monitors when unplanned changes in the inspection capacity occur, or when re-allocation of the sampling rates within the inspection sampling plan are required to support various yield or logistics issues. Alternate sampling scenarios
F i g u re 5: Dist rib uti on o f costs acr oss the selec ted defect ins pection monitors.
Another graphical method of assessing the relative criticality of each of the defect monitors is to graph the excursion frequency versus the yield impact in a scatter-plot, as shown in Figure 6. The scatter-plot is then separated into four quadrants, which can be used to illustrate the relative importance of each defect monitor. The “critical” monitors that have high excursion
Another key objective of this project was to compare the inspection sampling plan utilized at Intel to several alternate monitor reduction scenarios. These alternate scenarios would provide significant reductions in the required inspection capacity, and hence would result in substantial reductions in the associated inspection costs. Through multiple iterations, the Sample Planner algorithms can evaluate multiple defect inspection sampling scenarios to determine the most cost-effective inspection strategy. Two alternate monitor reduction scenarios were evaluated, which provided a 50 percent Spring 2000
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and a 75 percent reduction in the sampling requirements versus the current sampling plan. The first sampling scenario involved the decreased sampling of selected defect monitors, while the second sampling scenario involved the elimination of non-critical defect monitor(s) along with the decreased sampling of selected defect monitors. Using the related financial data, the cost associated with the various inspection sampling plans can be determined with reasonable accuracy. While both monitor reduction scenarios exhibited significant cost savings due to the decreased sampling requirements, the cost analysis indicated that these cost savings were insufficient to offset the increased yield losses that would result due to excursions missed by the decreased sampling plans. The results of this project show that the excursion costs were found to be dominant, and accounted for greater than 80 percent of the total costs associated with the defect inspection monitors.
The use of advanced statistical and stochastic models such as those in Sample Planner enables the overall costs of a complex inspection strategy to be fully characterized in terms of the costs associated with defect inspections, and the resulting yield loss due to defect excursions that would be missed by the inspection sampling plan. The project results confirmed that the current inspection sampling plan that was being utilized by Intel (with minor modifications), provided a cost-effective allocation of the existing defect inspection capacity. In addition, future monitor reduction opportunities were identified, and will be prime candidates for future cost savings as the process continues to mature. Consequently, the Sample Planner program proved to be an effective tool in challenging the paradigm of monitor reduction to achieve lower product costs in an advanced semiconductor manufacturing line. Acknowledgments
This paper is the result of a six month project and continuing collaboration on defect inspection sampling plan optimization between Intel Corporation and KLA-Tencor Corporation. The authors of this paper would like to acknowledge the project support provided by Anthony Cabbibo, Jeremy Kranz, and Vivek Jain from Intel Corporation, and Ruj Nasongkhla, Alan Welco, and Kevin Monahan from KLA-Tencor Corporation. References 1 . Nurani, R K., Akella, R., Strojwas, A. J. “In-line Defect Sampling Methodology in Yield Managament: An Integrated Framework”. IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 4, November 1996. F i g u re 7: A comparison of the total monitor costs of the current sampling plan compared with the two p roposed moni tor reduction scen ari os.
Summary
Because of increasing cost pressures within the semiconductor industry, many semiconductor manufacturers are being forced to consider and implement aggressive cost reduction measures. Since defect inspection steps are often perceived as being “non-value add” metrology operations, these metrology operations are frequently the primary focus for further monitor reduction and/or elimination to reduce operational costs.
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2 . Nurani, Raman K., Stoller, M., Gudmundsson, D., and Shanthikumar, J.G. “Evaluating Inspection Strategies Using Advanced Statistical Methods”. KLA-Tencor Yield Management Solutions, Vol 1, Issue 3, Spring 1999, p. 12-14. ( Available upon request from KLA-Tencor Corporation).
Reproduced with permission from ASMC ‘99.