Summer02 art of war in litho by KLA Corporation

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The Art of Defect War in the Litho Cell Ingrid Peterson, Meryl Stoller, Dadi Gudmundsson, Raman Nurani, Scott Ashkenaz, and Louis Breaux, KLA-Tencor Corporation

The latest technology advances and new processes in the lithography area, coupled with the increasing market pressures, have placed greater demands on defect management. Thinner resists, new resist chemistries, and tighter process windows along with shorter product life cycles and the need for faster return on investment create the necessity to focus more attention on defectivity. In order to be competitive, fabs must detect, identify, and resolve defects in the lithography area before committing product wafers to production.

Introduction

At present, the application of available advanced defect management technology in the lithography area has lagged compared to other areas in the semiconductor fab. Optimizing the defect management strategy with the large range of possible defect mechanisms and related yield impact that can occur within the lithography area is a relatively complicated task. With the variety of available defect inspection technologies, the capital and labor support costs associated with defect metrology and the ability to correct problems by rework, there is a need to approach the problem of defect management in a systematic manner to measure the cost effectiveness of the defect management strategy. In this paper the Sample Plannerâ&#x201E;˘ cost model was applied to the full range of available defect inspection technologies and sampling strategies based on the commonly known defect mechanisms that occur in the lithography area. From this a recommended optimum sampling and monitoring strategy was obtained.

cell. From a defect management perspective, the lithography cell has some unique characteristics. First, defects in the photo process module routinely have the widest range of sizes, from full-wafer to sub-optical, and with the largest variety of characteristics. Some of these defects fall into the categories of coating problems, focus and exposure defects, developer defects, edge-bead removal problems, contamination and scratches usually defined as lithography macro defects as illustrated in Figure 1. Others, as illustrated in Figure 2, fall into the category of lithography micro defects. They are characterized as having low topography such as stains, developer spots, satellites, and are very small such as the cases of microbridging, microbubbles, CD variation and single isolated missing or deformed contacts or vias. Second, photo is the only area of the fab besides CMP in which defect excursions can typically be corrected by reworking the wafers. The opportunity to fix defect

Defect management in the lithography cell

Today, the semiconductor process itself contributes the largest number and variety of defects, and a significant portion of the total defects originate within the lithography

Figure 1. Examples of lithography macro defects.

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Model inputs and assumptions

Sample Planner Model Overview

Avg. 94 nm

Avg. 136 nm

Figure 2. Examples of lithography micro defects.

problems without scrapping wafers is best served by a defect inspection strategy that captures the full range of all relevant defect types. Third, to some extent, the litho cell remains a defect frontier. In most areas of the fab, leading-edge defect management tools and methodology have already been adopted, but in the lithography area defectivity is often under-managed. For example, recent studies have shown that replacing manual inspection for macro defects by automated inspection can result in an increase of 1 to 2% in real yield1. This complex problem requires a sophisticated model of the costs and risks involved in order to evaluate the effectiveness of a variety of scenarios and strategies for defect management in the lithography area. The Sample Planner 3 model developed by KLA-Tencor in partnership with UC-Berkeley, Carnegie-Mellon University, and Stanford University has the capability of analyzing the cost effectiveness of defect management strategies for the lithography area.

The Sample Planner 3 Cost Model is based on several cost components which can be separated into two main cost factors: the costs of inspection operations and the cost-based risk of yield loss due to missed defect occurrences. The first set of costs are those investments that are made in order to perform defect inspection and the time involved in isolating and fixing defect issues. These are costs incurred by the fab, and increase as higher rates of sampling and defect inspection are implemented. The latter costs are the revenue gained by taking action and resolving defect issues so that subsequent lots yield higher or, alternately, the revenue lost by not capturing a defect problem sooner. These “costs” will likely be large at first compared to no sampling, so that performing a minimum level of sampling will result in revenue gained. As inspection sampling is increased at some point, the incremental revenue to be gained will diminish. For the sample planning model, the potential revenue loss is expressed by the number of lots at risk of a certain level of yield loss while a defect excursion event is in progress, until that event is captured and eliminated. This is illustrated in Figure 3. The inspection operations costs consist of several components including the capital costs of the inspection tools needed, the cost of labor to operate the tools in terms of shift personnel, labor costs for engineering to act on defect issues (real or false), other direct and indirect labor costs, facilities costs and, where applicable, the costs of test wafers and test wafer processing. The revenue loss due to defect excursion events is a function of the frequency of excursions, the duration of an excursion, the yield impact of the excursion and the die price for the particular fab. In this model, the baseline yield level is assumed to be at entitlement, so that any defect excursion event results in yield loss and, thus, revenue loss. What this means is that in the model the full impact of excursion will be realized on a lot, and not masked by other yield loss mechanisms.

Figure 3. Sample Planner model definition of “material-at-risk” during a defect excursion event.

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Inputs for Lithography Area Modeling Fab-level.

To perform the model for the lithography area, an appropriate fab model had to be chosen. For this study, an “average” 300 mm fab model was chosen to represent the costs. To model such a fab, the lot size was set at 12 wafers and the wafer starts at 5,000 wafers per week. The potential revenue for this fab was based on a fictitious device which had 600 dice per wafer and an ASP of $25.00 per die. This, on average, underestimates the potential revenue savings by yield improvement, although DRAM devices will likely have a lower potential revenue per die. This fab is assumed to operate 24 hours per day, 7 days per week with 3 shifts per day. These last inputs are necessary for the model, but typically do not impact the model results in any appreciable fashion compared to a fab that operates on 2 – 12 hour shifts per day. In this model, the cycle times used were based upon actual 200 mm cycle times that, on average, are common in the industry. These times would include the process times for the various lithography steps including the wait and queue times. In modeling tool monitors, such as a photocell monitor (PCM), it was assumed that the tracks would continue to process wafers while the monitors were being evaluated; thus, there were no “opportunity costs” associated with lost time on the tools other than the time to process the tool monitors.

monly occur in lithography areas worldwide was established. This list was developed by pooling the experience and data from knowledgeable resources within KLA-Tencor that have worked on lithography defectivity through consulting projects and other past work experience for many years up to the present. Some of these defect types are represented in Figures 1 and 2. A complete listing of the defects used for the model are presented in Tables 1 and 2 along with some of the pertinent parameters used to model the frequency of occurrence of excursions for such defects (for simplicity all are set at 5% probability of occurrence) and their impact on the yield, and the exposure of lots and wafer within lots to these defect types during an excursion event. The exposure of wafers to an excursion is based on an assumption of an excursion event occurring for only one resist or developer cup on a track. Multiple resist cups and developer cups are assumed per track (minimum of two), so that for defect mechanisms that are limited to single cup events, the wafer exposure is a percentage of the total wafers in a lot.

Lithography defectivity. To model the lithography area defectivity a set of 31 typical defects that com-

Table 2. Micro-level defects used in Sample Planner model with the associated excursion frequencies and impacts.

Inspection technologies and strategies.

Table 1. Macro-level defects used in Sample Planner model with the associated excursion frequencies and impacts.

The model was used to compare the best combination of defect inspection strategies and tool types for the lithography area. A block diagram that shows the various possible defect inspection points and likely tools used is shown in Figure 4. The inspection possibilities included the use of automated low sensitivity (≥ 50 µm) “macro” inspection on product wafers (such as use of KLA-Tencor’s 2430), brightfield high sensitivity “micro” inspection (such as use of a KLA-Tencor 2351), and darkfield inspection (such as use of a KLA-Tencor AIT XP). Not

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(macro DI), brightfield and darkfield micro DI, and brightfield PCM.

Figure 4. Block diagram of possible lithography defect inspections modeled.

considered by this model is the use of unpatterned wafer inspection such as would be performed on resistcoat only wafers or other unpatterned monitors. The primary goal of this study is the evaluation of inspection technologies on patterned wafers. Included in the patterned wafer grouping is the use of PCM,2-4 which are tool monitors that see the entirety of the lithographic process, but on an initially unpatterned substrate. Therefore, the combination of inspection strategies modeled were macro after-develop inspection

Inspection points modeled were after full patterning and typically performed after the CD and overlay measurement steps. Also included in the model was a brightfield micro inspection step after the etch step, which captured issues that were potentially missed by the post develop inspections. In the etch inspection case, the defectivity caused a yield loss; whereas the defectivity caught after the post-develop step was resolved by rework of the lot or lots affected. Prior cross-platform studies on product and photo-cell monitor wafers, as well as hands-on experience, were referenced to estimate the ability of a particular inspection technology to capture the various defect types in Tables 1 and 2. In general, the capture rate for this study was either “YES” or “NO,” i.e. captured or not captured. Table 3 shows the capturability used for this model by inspection monitoring for the 31 defects considered. Results from model scenarios

Several scenarios for performing lithography area monitoring were considered. The scenarios were based on the various combinations of inspection technologies and methods described above, as well as the frequency at which these monitors were performed and the sampling of lots and wafers as applicable. A listing of the sampling scenarios considered is provided in Table 4 below. For all of the potential scenarios the possibility of not performing each monitor was considered. The outputs of the model for each scenario would be the operational costs of performing the monitoring which is the sum of capital equipment costs, test wafer materials and processing costs (if applicable), and

Table 3. Capturability of defect types modeled by inspection tech-

Table 4. Inspection scenarios considered for modeling. For the PCM

nology and technique.

monitoring and wafers at risk, a 2-cup track scenario is used.

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direct and indirect labor costs and the “excursion costs” which is the potential revenue lost due to yield loss from excursion events not captured or the number of die negatively impacted by excursion events that were not recoverable (by rework, for instance). The costs were annualized in some cases producing an annual costs summary. The goal is to minimize both the operational costs and excursion costs and achieve the lowest excursion costs with the least added operational costs.

Figure 5. Comparison of inspection operation and excursion costs for selected scenarios for lithography area defect monitoring. For comparison, the cost of no monitoring is $64,500,000 per year.

Figure 5 shows the combination of costs for selected scenarios. Not shown is the cost for performing no monitoring. For reference purposes, that annual cost is entirely excursion-related and amounts to about $64,500,000 for this particular fab. As can be seen from Figure 5, just performing macro DI inspection results in minimal added operational costs, while reducing excursion costs (costs of yield loss) to under $35,500,000. Without macro DI monitoring, all other monitoring scenarios considered had an additional $10,000,000 or more in annual total costs. This is mostly due to the greater risk of excursion yield loss since the operational costs of macro DI are minimal. Also from Figure 5, it is seen that the least total annual cost occurs for the scenario with a combination of macro DI (100% of lots), PCM at three times a day and a brightfield inspection after develop (DI) at a low sampling of 6.25% of lots. Eliminating the brightfield DI inspection, as low as it is, reduces the inspection costs; but, that is more than offset by the increased risk from missing some excursion events. Darkfield inspection after develop (DI) at a high sampling rate can

reduce excursion costs, but not significantly more than a lower sampling rate for brightfield DI, and the inspection costs will be higher. From the model results it is seen that PCM, nonetheless at a relatively high monitoring rate, is worth the investment (test wafer costs, etc.) even for 300 mm, as long as it is capable of capturing the defect events. Conclusions

In a lithography area, the defectivity and yield loss mechanisms are diverse and complicated. In order to understand the optimum methods for defect monitoring it is necessary to consider the overall strategy as a system. The ability to perform rework in the lithography area adds an additional benefit in that potential yield problems can be corrected. As a result of the typical cycle times through a lithography area, it is more beneficial to use a high sensitivity brightfield inspection for both DI inspections and PCM inspections in spite of the slower overall inspection throughput. While a darkfield approach may appear cheaper, that advantage is more than lost by the defect types which are missed. As long as an excursion event is captured in a reasonable time before etch, a large enough number of lots can be saved to justify the inspection costs. However, using a lower sensitivity darkfield inspection can result in missed excursions and higher yield loss, even with a very high sampling rate. The model indicates that it is better to use macro DI inspection in combination with frequent brightfield PCM and brightfield DI at a low sampling rate for optimum lithography area monitoring. References 1. A. Yanof, et. al., “Implementation of Automated Macro After Develop Inspection in a Production Lithography Process,” SPIE 25th Annual International Symposium on Microlithography, February 2000. 2. E.H. Bokelberg and M.E. Pariseau, “Tracking the performance of photolithographic processes with excursion monitoring,” MICRO, January 1998. 3. S. Ashkenaz, et. al., “Effective Defect Management in the Lithography Cell,” Yield Management Solutions, Vol. 3, Issue 4, Fall 2001. 4. I. Peterson, et. al., “Lithography Defects: Reducing and Managing Yield Killers Through Photo Cell Monitoring,” Yield Management Solutions, Vol. 2, Issue 3, Summer 2000, pg 17-24.

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Shrinking process windows are a challenge. Hitting them doesn’t have to be. With the transition to 0.10 µm, optimizing your lithography process window is tougher than ever. And there’s no second chance to make a good first shot. Fortunately, by providing reticle, CD, defect and overlay control – as well as simulation – our sub-wavelength lithography solution is the most comprehensive one available. So you get unprecedented control over the entire process, from reticle to wafer. Commonality between tools. The ability to pinpoint targets in shrinking process windows. And a nice big score on ROI. For more information, visit www.kla-tencor.com/litho, or call 1-800-450-5308.

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