Summer04 strained silicon substrate by KLA Corporation

S New Ideas for New Materials U

Strained Silicon Substrate Technology: Commercialization Fundamentals Mayank Bulsara, AmberWave Systems Corporation

Strained silicon substrate technology, encompassing bulk strained silicon and strained silicon-on-insulator, has made the ascent from laboratory-scale experimentation to evaluation by leading wafer and device manufacturers for commercial implementation. The rapid commercialization climb has expanded and modified the requirements for strained silicon technology; however, the underpinnings of strained silicon substrate and transistor manufacture are closely related to fundamental innovations that were established early during strained silicon technology research. This article highlights the essential bulk strained silicon and strained silicon-on-insulator technology developments that have placed them on the forefront of materials innovations for the semiconductor industry.

Introduction

The 2003 International Technology Roadmap for Semiconductors (ITRS) for the first time forecasted the necessity of mobility/transconductance improvement for nearterm high performance logic application1. With mobility enhancement techniques forging into fundamental transistor architectures, strained silicon (Si), which is practically synonomous with mobility improvement, is being investigated by many manufacturers. Although strained Si generically refers to a Si crystal that is elastically deformed, the techniques for straining Si generally comprise three methods: (1) strain induced during transistor processing2,3,4, (2) mechanical or packaging-level strain5, and (3) substrate-level strain induced by relaxed silicon-germanium (SiGe) alloys6,7,8,9,10,11. Of the three methods, substrate-level strain is by far the best researched and characterized in terms of technological benefits and key economic factors for commercialization. Substrate-level strained Si technology is addressed by the 2003 ITRS section on Emerging Materials, which outlines key substrate design criteria for strained Si and its

embodiments. A schematic of these three embodiments is shown in Figure 1: (a) bulk strained Si, (b) strained Si on insulator with an intermediate relaxed silicongermanium (SiGe) layer (SGOI), and (c) strained silicon on insulator without a relaxed SiGe layer (sSOI). Among the key criteria listed for consideration are: strained Si film thickness, germanium (Ge) content in relaxed SiGe layer, threading dislocation density (TDD), dislocation pile-up density (DPD), and short- and long-range surface roughness. All of these criteria can be addressed adequately by innovations that are already being implemented. The remaining questions must be answered by full-scale transistor and chip developments and the qualification of economic wafer manufacturing methodologies that have the requisite inline metrology to ensure the highest quality. Strained Si Strained Si

Relaxed SiGe

Strained Si

Relaxed SiGe

SiO2

Si Substrate

(a) Bulk Strained Si

(b) SGOI

Figure 1. Strained Si embodiments in the 2003 ITRS Emerging Materials section.

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Early developments in strained Si substrate technology

The concept of straining Si via the use of SiGe alloys rapidly gained acceptance in the research community in the 1980s, but the performance of strained silicon channel layers lagged theoretical predictions for many years12,13. This was in large part due to suboptimal accommodation of the lattice mismatch between the epitaxial SiGe thin films and the starting bulk Si substrate. Improperly applied SiGe alloy thin films can result in two deleterious effects on the performance of the strained silicon channel layer: 1. Rampant dislocation nucleation can lead to strained silicon films of poor crystalline quality, negating the expected benefits of the strained silicon film. 2. Failure of the SiGe alloys to attain their equilibrium atom spacing (i.e., incomplete relaxation) during processing, thus imparting less strain in the strained silicon film. Both of these problems plagued the earliest demonstrations of strained Si technology. The critical breakthrough that enabled truly high mobility strained Si technology14 was the advent of compositionally graded SiGe alloys that were completely relaxed and of high crystalline quality15. Compositionally graded SiGe alloy technology fundamentally uses growth temperature and low strain rates to control dislocation nucleation kinetics16. Essentially, growing SiGe thin films at high temperature (700-900°C in the early 1990s) while gradually increasing the Ge content in small increments led to fully relaxed, low dislocation density films. These new strain-inducing SiGe films enabled high Si electron mobility that was 5x higher than was previously reported, but the SiGe thin films that incorporated compositionally graded SiGe alloys were also 15-30x thicker than previous films. This point will be discussed later in the strained silicon substrate production section. Once SiGe graded layer technology was established as the best path for high crystalline and electronic quality strained silicon, the next challenge was the demonstration of strained silicon structures in actual MOS transistors, as previous structures were not designed for CMOS applications. The first strained Si NMOS17 and PMOS18 transistor results were published in 1994 and 1993, respectively. These devices demonstrated that strained silicon could support sufficient quality thermal oxides for gate stacks, and that the substrate structures 36

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could undergo other traditional CMOS processing steps (implant, anneal, etc.), while at the same time providing significant improvements in carrier mobility (80%), drive current (15%), and transconductance (50%). However, these demonstration MOSFETs were large geometry devices (Lg>10 µm). Concerns still existed that more modern transistor structures would not experience any benefits due to velocity saturation effects. In 1998, the first submicron transistor results (Lg~0.1 µm) were presented that showed significant transconductance enhancement (45%)19 and demonstrated the potential of strained Si as a state-of-the-art device solution. State-of-the-art strained Si transistor developments

After 1998, the impetus for commercial evaluation of strained Si technology increased. In 2001, IBM for the first time reported that strained Si NMOS transistors can maintain significant mobility enhancement20 and operate at the high vertical fields (1.5 MV/cm) that are observed in modern MOSFETs. In 2002, IBM further demonstrated that sub-100 nm PMOS transistors maintained mobility enhancement characteristics, which translated into drive current (Ion) enhancement6. Several additional reports of state-of-the-art strained Si transistor performance have recently emerged. TSMC reported strained Si n-MOSFET Ion-Ioff enhancements of 15% (without correction for self-heating effects) at a gate length of 60 nm10. In tandem with higher channel mobility of strained Si, Toshiba implemented sourcedrain engineering techniques to take advantage of the lower series resistance enabled by the SiGe alloys and fabricated 40 nm gate length strained Si p-MOSFETs with 11-19% Ion-Ioff enhancements11. IBM, Intel, and AMD have demonstrated the compatibility of strained Si with high-κ gate dielectrics and metal gate electrodes6,9,7. Furthermore, the same reports show how the mobility enhancement provided by strained Si can compensate for the inherent mobility loss resulting from the implementation of high-κ gate dielectrics. In general, the discrete elements of strained Si transistor performance benefits and integration capability with standard and advanced CMOS processing techniques have been demonstrated. The two elements that are currently being evaluated are the assembled benefits of NMOS and PMOS performance in a single integrated chip and the yield and long-term reliability of the optimized strained Si chip.

Bulk strained Si substrate production

With the basic building blocks of strained Si substrate technology established in the 1990s, the remaining criteria for bulk strained Si substrate production are: 1. Strained Si substrate quality sufficient for high yielding chips 2. Economic processing of strained Si substrates 3. Rapid and accurate inline metrology of strained Si substrates The strained Si-specific quality metrics can be categorized as those related to ULSI surface quality and those related to defects (TDD, DPD, misfit dislocations). Compositionally graded SiGe alloy structures have a characteristic rough, or ‘crosshatched,’ surface (see Figure 2), which is actually indicative of a very high crystalline quality film. This surface can create problems for lithography and surface inspection. This challenge is readily addressable via the insertion of industry standard polishing processes in the strained Si substrate fabrication sequence. This results in a three-step manufacturing process for strained Si substrates: 1. Fabrication of the relaxed SiGe layer via compositionally graded SiGe alloys 2. Polishing of the relaxed SiGe layer to remove the crosshatched surface roughness 3. Deposition of the strained Si channel layer 50

20 50.00 nm 10

0 0

10 µm 40 µm

It is well-known that strained Si substrates contain a finite number of threading dislocations that extend from the relaxed SiGe layer through the strained Si layer to the substrate surface. Although crystalline perfection is always the limit that wafer and device manufacturers strive for, in practice the TDD must be controlled and minimized, but the threshold for yielding high performance chips is far from zero. The effect of threading dislocations on junction leakage has been investigated in large-area strained Si diodes fabricated with a 130 nm-node CMOS process8. Diode junction leakage was evaluated for a range of bias conditions, and while the strained Si diode leakage was marginally higher than that of the control Si diodes, even at a bias of 1.2V the leakage was less than 10 fA-µm-2. Even assuming a worst-case scenario of all leakage being attributed to threading dislocations, the contribution of threading dislocations to strained Si junction leakage was found to be negligible. Moreover, state-of-the-art strained Si substrates have threading dislocation densities in the 105 cm-2 range, an order of magnitude lower than that of the strained Si substrates used in the reported study. Similar experiments indicate that strained Si MOSFET gate leakage is comparable to or even slightly less than gate leakage of control Si MOSFETs. Additionally, time-zero dielectric breakdown (TZDB) measurements performed on large area strained Si MOS capacitors with approximately 900 threading dislocations intersecting each capacitor, showed the strained Si TZDB behavior to be comparable to that of the control Si devices, implying no deleterious impact of threading dislocations. Finally, the evolution of silicon-on-insulator (SOI) substrate technology is an excellent reference point for benchmarking the suitability of the residual TDD in modern strained Si substrates for production application. The 2001 ITRS listed crystalline defect density targets for SOI substrates to be less than 2x105 cm-2, which translated to 95% chip yield. Although SOI substrate quality has improved over the past several years, it is commonly overlooked that the first SOI chip products operated sufficiently with substrates that contained a TDD of greater than 106 cm-2. An empirical circuit yield model, developed for various substrate defects, predicts that a TDD of less than 106 cm-2 would have no impact on strained Si circuit yield21.

20 µm 30 µm 20 µm

30 µm 10 µm 40 µm 0

Figure 2. 40 µm x 40 µm AFM topographic image of a compositionally graded SiGe alloy structure depicting the ‘crosshatched’ surface. The

Although threading dislocations at low densities are seemingly harmless to transistor performance and yield, misfit dislocations at the strained Si/SiGe interface have been shown to have deleterious effects on state-of-the-art device performance. Misfit dislocations can arise in strained Si layers thicker than the critical thickness, which

typical RMS roughness is 5-10 nm and the lateral periodicity is 1-10 µm.

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is the thickness at which incremental strain is relieved by dislocation glide at the strained Si/SiGe interface. Specific studies of strained Si n-MOSFETs, targeted at understanding the behavior of misfit dislocations and strain relaxation in strained silicon substrates, have shown that devices on strained Si layers with a finite density of misfit dislocations display an extremely high off-current floor22. Further characterization indicated that misfit dislocations cause highly localized leakage across the device channel. The same studies showed that strained Si substrates with strained Si thickness below the critical thickness are not afflicted by enhanced leakage. The economics of strained Si substrate manufacturing are most affected by the rate at which the epitaxial films can be deposited. As stated earlier, the use of compositionally graded layers greatly improves the crystalline quality of strained Si substrates, but also results in thicker films. For traditional research methods of strained Si substrate fabrication, the additional film thickness was considered cumbersome because the films could not be grown at high enough temperatures (>1000°C) to attain sufficiently high growth rates for fast strained Si substrate processing. This can be attributed to the limitations of equipment sets and the fact that the GeH4 Ge precursor, the traditional Ge precursor used for various Ge deposition processes, is not well suited to high temperature growth application. Developments with GeCl4 have recently enabled growth of relaxed SiGe films at temperatures exceeding 1050°C, allowing for the growth of several µm thick, relaxed SiGe layers in less than five minutes23. In addition to the very fast processing time, the implementation of GeCl4 also

improves the quality of final strained Si substrates by minimizing parasitic reactor coating inherent with the use of GeH4, which traditionally results in a greater LPD density. Figure 3(a) shows a picture of an ASM E2000 CVD reactor chamber after growth of a several µm thick, compositionally graded SiGe alloy film at 1075ºC with GeCl4—no deleterious coating is present and, as expected, the LPD is very low (10s of particles), as shown in Figure 3(b). Modern CMOS transistor manufacturing requirements necessitate excellent in-line substrate metrology. Strained Si substrate technology has been shown to be compatible with standard surface inspection equipment (e.g., KLA-Tencor SP1TBI surface inspection equipment) and physical characterization techniques (e.g., site flatness, nanotopography, etc.). The unique aspects of strained Si substrate inspection involve mapping of the Ge content and strained Si thickness, and these parameters can be measured with spectroscopic ellipsometry techniques that are commonplace since the introduction of SOI substrates. X-ray diffraction and reflection (XRD and XRR) techniques are also being developed to facilitate measurements of Ge content and strained Si thickness. Strained Si on insulator substrate technology

Another emerging application for strained Si substrates is their use as donor substrates for the creation of SGOI and sSOI substrates. First demonstrated in 2002, the SiGe-free sSOI structure consists of a strained Si layer

(b)

(a)

Figure 3. (a) Picture of ASM E2000 reactor chamber after 4.5 µm relaxed SiGe growth process with GeCl 4 . Note the lack of parasitic deposition on quartz chamber. (b) LPD density on a strained Si wafer meets state-of-the-art specifications with the implementation of a GeCl 4 process.

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12.5 > 12.0 - 12.5 11.5 - 12.0 11.0 - 11.5 10.5 - 11.0 10.0 - 10.5 9.5 - 10.0 9.0 - 9.5 8.5 - 9.0 < 8.5 nm

Strained Si

BOX

100 nm

5 mm edge exclusion Spectroscopic Ellipsometry

(a)

(b)

Figure 4. Cross-section transmission electron microscope image (a) and spectroscopic ellipsometr y map of sSOI wafer. The strained thickness is 100 Å with a ±6 % variation across wafer.

directly bonded to an oxidized handle wafer24. The strained Si donor substrate is optimized with the low surface roughness demanded by the wafer bonding process. With state-of-the-art strained Si donor substrates in tandem with typical hydrogen-induced exfoliation and selective chemical etching processes, sSOI substrates with low defect density, low surface roughness, and high thickness uniformity have been demonstrated (see Figure 4). In addition, sSOI layer strain has been shown to be stable, even in the absence of the strain-inducing SiGe layer, during thermal anneals of up to 950-1100ºC25. Furthermore, sSOI MOSFETs fabricated with strained Si layers above the critical thickness exhibit no symptoms of misfit dislocation-induced off-state leakage26. While studies of sSOI MOSFET behavior are continuing, well-tempered sSOI devices would provide instant performance benefits to partially-depleted SOI products in volume production today and fully-depleted SOI products in the near future. Conclusions

Strained Si substrate technology fits the important criteria for implementation in high performance products today and in the future. The key to both bulk strained Si and SSOI substrate technology is the implementation of well-designed substrate fabrication sequences that enable high quality levels in an economic manner. All the essential manufacturing steps are already in place and can be readily ramped to meet production volume needs. The production volume demand will come from

device manufacturers that adopt strained Si substrate platforms after the assembled performance and yield standards are validated internally. In comparison to other methods for enhancing CMOS product performance, strained Si substrate platforms are not only very mature in terms of production readiness, but they augment the implementation of other high performance process introductions, such as high-κ gate dielectrics.

References 1. http://public.itrs.net 2. S. Ito, et al. Proc. IEDM, 247 (2000) 3. S. Thompson, et al., Proc. IEDM, 61 (2002) 4. C.H. Ge, et al., Proc. IEDM, 73 (2003) 5. R.E..Belford, Device Research Conference (2002) 6. K. Rim, et al., VLSI Tech. Dig., 98 (2002). 7. Q. Xiang, et al., VLSI Tech. Dig., 101 (2003). 8. J.R. Hwang, et al., VLSI Tech. Dig., 103 (2003). 9. S. Datta, et al., Proc. IEDM, 653 (2003). 10. H.C.-H. Wang, et al., Proc. IEDM 61 (2003). 11. T. Sanuki, et al., Proc. IEDM 65 (2003). 12. H.-J. Herzog, et al., Thin Solid Films, Vol. 184, p. 237 (1990). 13. K. Ismail, et al., Appl. Phys. Lett., Vol. 58, p. 2117 (1991). 14. Xie, et al., Mat. Res. Soc. Symp. Proc., Vol. 220, p. 413 (1991). 15. Fitzgerald, et al., Mat. Res. Soc. Symp. Proc., Vol. 220, p. 211 (1991). 16. Fitzgerald, et al., J. Vac. Sci. Technol. B, Vol. 10, p. 1807 (1992). 17. Welser, et al., Appl. Phys. Lett., Vol. 15, p. 100 (1994). 18. Nayak, et al., Appl. Phys. Lett., Vol. 62, p. 2853 (1993). 19. Rim, et al., IEDM Tech. Dig., p. 707 (1998). 20. Rim, et al., VLSI Tech. Dig., 98 (2002). 21. A. Lochtefeld, presented at Semicon Japan, (2003). 22. J.G. Fiorenza, et al., Semicond. Sci. Technol. 19, L4 (2004). 23. R. Westhoff, et al., to be published in Proc. Electrochem. Soc., (2004). 24. T.A. Langdo, et al., IEEE SOI Tech. Dig., 211 (2002). 25. T.A. Langdo, et al., Proc. SSDM, 814 (2003). 26. I. Lauer, et al., IEEE Electron Dev. Lett. 25, 83 (2004).

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