Winter02 the best laid plans of 300mm fabs by KLA Corporation

Cu/low P

κ U

The Best Laid Plans of 300 mm Fabs Anantha Sethuraman, Sagar A. Kekare, Raman Nurani, and Dadi Gudmundsson, KLA-Tencor Corporation

The move to 0.13 µm, and the introduction of new materials and processing methods such as copper, low-κ materials, and phase shift reticles, are byproducts of the demand for more powerful ICs. As a result, the yield management challenges are difficult, but somewhat anticipated for a move to a smaller design rule. Some of the associated defect samples planning aspects, such as employing e-beam inspection in addition to optical techniques, have been explored 3. For the first time in recent memory, the semiconductor industry is witnessing the convergence of shrinking design rules, the transition to 300 mm, and implementation of new materials in the interconnect scheme such as copper and low-κ dielectrics. The fact that the 300 mm transition is taking place, along with other transitions, creates unique challenges and opportunities in yield management that warrant a new focus in defect sample planning.

Although the transition to new materials and smaller design rules are definitely technology-enabling endeavors, such efforts are not without their characteristic yield management challenges. However, many of these challenges would have been encountered without the 300 mm transition taking place simultaneously. Supposing no 300 mm transition were taking place, previously established sample planning exercises could be performed effectively, with only moderate changes in focus, to establish effective yield management strategies. This paper has been organized to reflect those challenges and provide some insights to surmounting them. The first half of the paper covers in detail some of the 300 mm process-induced challenges, while the second half covers the classical defect inspection sampling problem from a 300 mm standpoint. The detailed discussion of 300 mm processinduced challenges provides a guideline to where new defect inspection points may emerge. Besides suggesting the incorporation of these potential inspection points into 300 mm sampling plans, the latter half of the paper addresses how sample planning in 300 mm fabs needs to take place alongside layout and automation plans for optimal effect.

300 mm technological & processinduced challenges

Films Module Films processes are generally viewed as two somewhat separate categories: planar films stacked on a substrate, and films targeted towards optimal gap-fill to avoid translation of topography. The planar film-stacks such as STI nitride, gate poly-silicon, or refractory metal for silicidation are mostly affected by defects like particles, flakes, pinholes and voids. In addition to these defects, the gap-fill films may have other unique defects when they fail to achieve their primary function of filling a gap between features. Many times such unique defects may not be captured right after deposition, as they stay hidden deep into the folds of these films. Examples of these films are STI HDP oxide, spacer nitride, PMD doped silica glass, IMD doped silica glass for Al interconnects, etc. With advent of copper dual damascene technology, a much larger fraction of films in modern fabs have gap-fill function as their prime objective. Absorption and adhesion between each of the films within a desired film stack is a prime factor that controls the continuity and conformity of such film stacks. Electrochemically deposited copper is especially sensitive to the existence of a sputtered seed layer during the nucleation stage for the copper film. Voids are almost the predominant defect in copper films due to this tendency. New methods in Winter 2002

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processing bring about a new set of defects to a module. The circular motion of the wafer in a non-optimal electrochemical bath may result in concentric swirl patterns in deposition. Variations in film deposition rate would be magnified with 300 mm wafers. Larger area coverage would accelerate film stress related failures like warping and cracking. Stresses could induce stacking fault type defects at the silicon-STI interfaces near the edges of the wafer.

may result in damage to the substrate, which may be intolerable. Non-uniformity in removal rate may leave behind under-etch residues and stringers. High aspect ratio features are ubiquitous with the increasing adoption of copper dual damascene technology. Shrinking design rules combined with high aspect ratio allows for small process drifts to result in gross defectivity such as through under-etch or distorted features. Difficulty in removal of passivating etch byproducts from the high aspect ratio features is another source of defectivity.

Litho Module Lithography is clearly the most complex process module in modern fabs. Along with the quantum leaps in exposure tools and ancillary systems, this module faces a rapid introduction of new consumables and film substrates. These conditions, combined with radically new mask technologies, present a significant challenge for defect control and yield entitlement.

Etch chamber design has evolved from the baseline 200 mm configuration into the 300 mm configuration. Gas flow, plasma induction, and location of the exhaust port contribute to the non-uniformity of etch action. With a larger wafer area, these issues can be expected to remain important, if not grow in significance.

CMP Module Resist backsplash, developer spots, focus hot-spots, missing pattern, resist collapse, etc. are some of the most common defects encountered in the litho module. The integration of the new tools, materials and consumables is a formidable task for litho module optimization. Photo-resist poisoning from inorganic ARC, thin pattern lines broken due to micro bubbles, CD variation across the chip due to grid snap, OPC errors during mask making, and partial printing of sub resolution assist features are only a few examples of the current defectivity that stem from the integration challenges in the litho module. Process development efforts that combine the parametric and defectivity aspects of module optimization will achieve early yield. Bake-oven temperature non-uniformity and variation in the focus offset across the wafer are two principle causes for across-wafer CD variation. With the 300 mm wafer size, the oven-related variation should contribute a much larger fraction of CD variation across the wafer. When combined with sensitive techniques like OPC and phase shift reticles, such variations may become the root cause for a significant portion of litho defectivity.

Etch Module Etching is controlled removal of part of a film stack using exposed photo-resist pattern as the masking layer. Hence many of the defects from lithography will potentially be carried through the etch step. In addition to these defects, etch tools may flake off the passivation layer condensed on the chamber walls. Loss of selectivity 32

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Chemical mechanical planarization was introduced to recover a planar wafer surface through removal of undesirable topographic features. The dielectric layers were amenable to this technique, with tungsten plugs being mostly defined by CMP in the last few device generations. Due to the unique combination of chemical dissolution and mechanical abrasion, the defects generated during CMP were quite unique in themselves. The defects ranged from the simple residual slurry and scratches to more complex interactions like delayed corrosion and coring of interconnects. Additionally, CMP also brought to light the film defects caused by inefficient gap-fill. Copper dual damascene technology has shifted the focus of process development from dielectric CMP to metal CMP. Copper CMP is being brought to high volume IC manufacturing for the very first time. This shift in the objectives of BEOL CMP from planarization to full-fledged interconnect definition brings about a slew of defectivity and process control issues. All films in the copper module belong to the gap-fill category. Moreover the dual damascene features have higher aspect ratios than previously encountered in IC processing. This gives rise to seams and folds forming along the feature during deposition. CMP exposes these hidden defects in the form of co-axial voids. CMP may also generate voids through the copper grain rip-out phenomenon. Any unbalanced chemistry of the slurry compound may result in delayed corrosion of the copper features.

N-well mask

1-2 Âľm Figure 1. Typical SRAM cell showing opened N-well region between two P-well regions masked with photo-resist.

When polishing a larger area, however, the preliminary reports seem to suggest that removal rates become more uniform across the wafer. Since multiple techniques of CMP are still in the evaluation phase, it will be difficult to state this observation to be universally applicable.

state of the art stepper/scanner platforms. This validates the need for following the dual-pronged approach to early process development and characterization on the well layers (refer to Figures 1 and 2).

Gate Dielectric Deposition Emerging defect inspection points

N/P Well Lithography The N/P well region masks contain extremes in feature size. In the memory regions, where the wells are placed very close to each other in a very regular array, the mask features are long lines under 2 microns wide, whereas in the peripheral control logic, the mask may feature larger rectangles tens of microns wide on both sides. Typically, the process development for this layer is low priority and a nominal process window is decided with a single data point collected per field from a focus exposure matrix wafer using a CD SEM. Since this data collection point does not truly represent the process windows for the entire range of features on the mask, there is always a risk of some feature falling out of the usable process window with a minimal drift in focus offset. However, with shrinking minimum allowable dimensions of well layer, this risk has assumed a greater significance.

As the operating voltages scale down, power consumption specifications tighten and performance requirements shoot up, and the gate dielectric quality becomes extremely important for the device. The inspection at pre-gate dielectric growth/deposition should focus mainly on the physical phenomenon that affect the dielectric quality. These are crystal-originated pits (COPs), scratches from STI CMP, and any other surface contamination. Although 300 mm wafers handling will be fully automated, the transition from 200 mm to 300 mm

Long thin area

This risk can be mitigated early on during the process development phase. An approach that looks at both, the parametric as well as the defectivity performance of a given process is the correct way to provide early mitigation of this risk. Older 200 mm-stepper platform designs will be ready to process 300 mm non-critical layers with some additional modifications of the chuck and auto-focus systems. However, these systems may have a greater challenge in maintaining across wafer focus offset as compared to the

True process window

Large open area

Figure 2. Schematic of process window for two distinct features on a given reticle, indicating the overlap region as the true usable process window.

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Weak sites possibly due to COPs

Figure 3. a) A cumulative probability plot of a highly defective gate dielectric indicating unacceptable proportion of weak sites. b) An AFM rendering of cr ystal-originated pit type defects.

may inherently cause the wafer to possess more COPs type of defects as incoming material. Scratches that translate through the STI nitride into the substrate silicon are known to affect the device characteristics adversely. This log point will serve to weed out defective wafers at an early stage in the process, thereby saving considerable processing costs (refer to Figure 3.)

contact resistance levels. An inspection log point at Silicide RTP 2 will capture the evolution of such defects for an early root cause analysis8 (refer to Figure 5). The above sections have outlined emerging 300 mm processing issues that may point to the need for amended or expanded defect inspection plans in 300 mm processing. Being aware of those issues is one part of the puzzle

N+ / P+ Implant Lithography

Silicide RTP 2 Cobalt silicidation is extremely sensitive to the presence of any oxide on silicon. However, any native oxidation arising from rinse dry spots, etc., is not detectable prior to silicidation. Similarly any remaining inorganic ARC on top of the gate poly-silicon is not detectable prior to silicidation. Yet, these may result in a population of unsilicided sections, each as large as the smallest design rule gate CD. Unsilicided regions usually have high 34

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Tighter process windows warrant stringent process centering

Process Window

Similar to the N/P Well masks, these two masks also contain a large range of feature size. A region of butting implants may not get silicided if each implant is pulled back due to the litho CD widening. Similarly resistance to junction breakdown may suffer if the litho CD is shrunk. An early optimization of process window through a defectivity and parametric characterization will prove extremely beneficial in avoiding these integration roadblocks (refer to Figure 4).

0.25 Âľm

0.18 Âľm

0.13 Âľm

Figure 4. A schematic of shrinking process margins, indicating an ever-increasing challenge for parametric process control as the design rules shrink further.

similar. However, we are not producing one die at a time and, therefore, excursions will occur at shorter intervals then in 200 mm processing. This may require every lot to be sampled at some layers, where that was not justified in 200 mm processing.

Sheet Res. Ohm/Sq.

0 0

Over-Etch (Arb. Units) Figure 5. a) Silicide sheet resistance as a function of over etch in wet clean step, indicating a threshold for removal of oxide residue from top of gate pattern. b) A SEM image of residual oxide on polysilicon gate pattern, where silicide formation was inhibited.

in creating an effective sample plan in a 300 mm fab. Combining these emerging issues with known inspection points in 200 mm processing, the space of inspection points can be defined (to the extent it is possible without extensive actual 300 mm processing data). Now a larger scale methodology needs to be applied to identify capable inspection equipment, calculate inspection capacity required, and allocate it effectively across the fab. The following paragraphs address these issues. Defect detection challenges in 300 mm

A variety of new challenges to defect detection are introduced during the move from 200 mm to 300 mm. First, there is the need for detection over a larger surface area. This requires modification of existing hardware. Second, and more importantly, is the use of new materials. This will change both the composition and type of defects encountered, requiring new techniques for their capture and automatic classification. Third, the size of â&#x20AC;&#x153;killerâ&#x20AC;? defects decreases with the move to a smaller design rule, requiring an increase in tool sensitivity. Fourth, new inspection requirements, such as wafer backside inspection, become important, prompting the redesign of inspection tools. Finally, from a broader perspective, there are issues such as the need for seamless information exchange between defect detection and review tools, processing of greater amounts of data, and the need for automation of the defect sampling process, in keeping with the overall fab-automation initiative. In addition to the above, it is expected, and initial pilot line/ramp experiences confirm, that excursion rates can be higher. To some degree this is merely the fact that excursion frequency is measured in wafers. If one were to measure the frequency in number of dies between excursions, then the rates may be somewhat

The yield management industry is well on its way in providing the tools and techniques necessary to deal with the above-mentioned challenges, but this capability needs to be deployed correctly. With major 300 mm fabs in the planning stages, a unique challenge and opportunity in yield management arises. By including yield management in the planning stage a fab can be predisposed to deliver superior yields. Further emphasizing the need to include yield management in the planning process is the fact that 300 mm fabs will have processing and inspection tools bound together with various automated material handling systems. This will, inherently, make fab layouts and material flow less flexible, and emphasizes the need for setting the fab up correctly the first time. Towards that goal, the following sections address the concepts and methods that should be employed to effectively include defect sample planning in the fab planning stage. Process integration-induced defectivity in copper interconnects

Spin-on and CVD low-Îş dielectric films are replacing the PECVD doped silicate glass films for BEOL interlayer isolation. These new films possess characteristics that make their integration markedly different. These films do not fulfill a gap-fill role. They are planar films that are patterned with trenches and holes later to be filled with electroplated copper. The patterning is done with DUV process, with alignment of subsequent photo steps gaining critical importance. Electroplated copper is highly sensitive to surface conditions and needs a high quality seed layer of copper for uniform film growth. Copper being a deep level impurity, a thorough encapsulation of all interconnects is necessary to prevent the copper from diffusing into the silicon. Tantalum nitride or tantalum barrier films are deposited prior to the seed layer to achieve this objective. Once filled with copper, the etched pattern is redefined by planarizing the excess copper through use of CMP. The process steps mentioned above are complex in themselves. In addition to that, they need to be optimized for their combined process margin. One element of this optimization is the need to eliminate possible defect generation through interaction of these processing steps. Winter 2002

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A few striking examples of how killer defects are generated through such interactions are discussed below with schematics in Figure 6 (a) through (i). Photoresist poisoning from PECVD low-Îş dielectric films

In the dual damascene scheme of etching, the second patterning step is exposed to the dielectric film with- Figure 6a. Missing via. out a capping layer. The amine radicals from the nitrogen containing film alter the development reaction of the DUV photoresist. This leads to curious defects such as mushroomed or missing vias. Film discontinuity due to etch profile non-ideality

An overhanging or barreled via profile leads to shadowing in the path of sputtered barrier and seed Figure 6b. Barreled via profile leads to a hidden void in copper. layer films. Absence of seed layer will lead to incomplete filling of copper into via holes. Such a void will remain hidden from optical inspection and will prove to be a truly silent killer defect. Pattern density dependence of copper polish rate in CMP

Dense regions tend to demonstrate a propensity for slower polish rate. Slower polishing increases the probability of Figure 6c. Copper puddles. copper puddles or residues between a dense array of lines, which may lead to bridging shorts and circuit failure. Translation of previous layer topography into the current layer

Variation in metal polish rates due to pattern density 36

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dependence may lead to flatness variation in the next inter-metal dielectric layer. Such variations could prove fatal for the already shrinking process windows for DUV lithography. It Figure 6d. Scratch filled with copper. becomes imperative to implement dielectric surface polish steps to bring the overall flatness within an acceptable range. A scratch from such dielectric CMP may get filled with ECP copper and act as a stringer or a bridging short. Defects from metal deposition process exposed during CMP

Electrochemical plating of copper is extremely sensitive to hindrances to nucleation and growth. These hinFigure 6e. Voids and seams in copper. drances could be non-uniformity of seed layer or it could be residues from SEM review of seed layer due to carbon condensation. A void may get embedded in electroplated films, where the copper failed to adhere and nucleate. Such embedded voids can be exposed during polishing of copper. Some electroplating conditions are prone to bread-loafing, and generate a seam along the axis of trench in which copper is deposited. Such a seam shows up after CMP as a row of voids along the center of a copper line. Corrosion and material non-compatibility

The CMP process has a large chemical aspect to it. Copper CMP typically proceeds in an acidic environment. Nearing the endpoint, the acidic Figure 6f. Corrosion in copper. electrolyte is now in contact with both the barrier layer and the copper line. This leads to the formation of a galvanic cell, resulting in corrosion of copper lines along the barrier interfaces.

Corrosion attacks may also take place along the triple points in the copper microstructure, leaving distinct pitting type defects behind. Impact of annealing conditions and timing in the integration sequence

Electroplated copper films are polycrystalline. An annealing treatment is necessary to optimize the grain Figure 6g. Cross section schematic. size and stresses in copper films. However, the thermal energy available from the Grains annealing is utilized for void growth and coalescence. Such void growth may seek low free-energy sites such as grain boundaries or interfaces for condensation into large voids. Figure 6h. Triple point voids in copper. If the annealing is done prior to CMP, then these condensed large void regions give rise to defects such as rip-outs, voids along the line edges and broken lines. If the annealing is done post-CMP, sub-surface Figure 6i. Condensed voids in copper. voiding may result from condensation of voids along the bottom of the via or the side of the trench.

is not the correct metric in which to base the amount of inspection capacity needed. Instead, one should seek to maximize the profitability of the fab and employ the inspection capacity needed to reach that goal. When calculating that capacity, fabs need to pay attention to several factors that collectively are embodied in a yield management strategy. A fundamental analysis of process tool, material handling, andinspection/metrology capacity planning is required. Furthermore, the impact of inspection on yield and cycle-time needs to be understood to provide a return on investment (ROI) that is optimal. Strategies will then vary depending on the fab (development or production), device (memory, logic or mixed) and segment (captive or foundry). The transition to 300 mm has a larger impact on the economic aspect of wafer manufacture. Transferring processes with low baseline yield into the ramp phase lacks economic viability or, worse still, will become fiscal disasters. This further reinforces the value of a high yield learning rate being present early. Preliminary analysis shows orders of magnitude difference in the value of yield learning for 300 mm processing. Table 1 contains some of the parameters used and Figure 7 shows the results. It can be observed that there is a much greater return per yield learning percent increase in 300 mm processing than in 200 mm processing. Although a high yield learning rate is not only dependent on the available inspection capacity, a lack of inspection capacity can certainly be the limiting factor in the yield learning process and would most definitely be the differentiator in the long run between leading-edge companies. ASP/cm2 of silicon Wafer starts per week Die size Starting D0 Fault learning rate per month

$40 1000 1.5 cm2 0.65/cm2 4% 1

Economies of scale and yield management

The fundamental premise of the 300 mm initiative is economy of scale, i.e., to decrease the manufacturing cost per square centimeter of silicon. It is estimated that the manufacturing cost per square centimeter of silicon will be about 30 percent lower. As one would expect, the pressure on improving yield management to produce more good dies at a lower cost is increased. It is, however, simplistic to enforce the same cost performance on yield management needs without considering the whole picture. Using the guiding principle of reducing inspection cost per square centimeter of silicon by 30 percent

Table 1. Parameters in yield learning rate analysis .

After the ramp-up phase is finished, the excursion control mode of yield management takes over for the full production phase. Again the 300 mm fab is faced with the dilemma that while the initiative provides considerable economies of scale in chip production, each wafer is much more valuable and that greater amounts of material are at risk to excursions than in 200 mm production. Calculating the relative value of 300 mm yield losses relative to 200 mm yield losses in the full production phase is much simpler than for the ramp-up Winter 2002

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$35

160

Opportunity GAINED Per Year (M$) (assuming 1000 wafer starts per week)

Yield

140

Value of Materials Lost (Million/Month)

300 mm 200 mm

Learning Rate Delta

120 Time

100 80

$25

300 mm 200 mm

$20 $15 $10 $5 $ 1%

Yield Loss to Excursions

40 Figure 8. Examples of the value of yield losses to excursions for 200

mm and 300 mm processes during the full production phase.

3% 5% 7% 10% Fault Learning Rate Delta Per Month

inspection capacity will be needed for the full production phase in 300 mm processing. KLA-Tencor has a wellestablished methodology to do sample planning for both the full production and ramp up phase of the fab. This methodology has the capability to address the 300 mm defect sample planning challenges. The following paragraphs address this methodology and its application to fab planning.

Figure 7. Comparison of opportunity gained in 200 mm and 300 mm processing for a range of increased yield learning rates. The insert explains the definition of an increased yield learning rate, a traditional yield learning rate is in blue and an increased yield learning rate in purple.

phase. Utilizing the applicable inputs from Table 1, and assuming that the wafers starts per week are 4,000 in this phase, we can calculate the value of lost materials each month relative to the same in 200 mm processing (see Figure 8). Numerous results in sample planning analysis2, 3, 7 have shown that the amount of inspection capacity to be used should be based on the value of the materials that can be saved. Given the vast value difference shown in Figure 8 it is expected that greater

300 mm defect sample planning

It has become well accepted that defect inspection tools play an important role in a fabâ&#x20AC;&#x2122;s yield management strategy. While few manufacturers currently operate without some type of defect inspection, many IC manufacturers tend to view inspection as non-value-added

Inspection Method?

Inspection Tools?

Products Inspected?

% of Lots?

Wafers Per Lot?

% Area/ # of Sites

SPC Control

e.g., 8 Steps

e.g., Product Test Wafer

e.g., 2xxx AITx

e.g., Products A, B, C

e.g., 40% of Lots

e.g., 5 Wafers Per Lot

e.g., 50% of Area Per Wafer

e.g., # of Defects X-Bar Chart

Product

2xxx

Process Flow

Inspection Layers?

Test Wafer AITx/SP

In-situ eS20 Figure 9. Typical questions posed in a sample planning analysis.

$30

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and are overly conservative when planning inspection capacity. It is here that the sample planning problem arises: what types of inspections to perform; where to locate them in the process; and how frequently to perform the inspections. To answer these questions, an effective method involves the trade-off between the cost of inspection operations, both fixed and variable, and the cost and/or risk of yield loss due to undetected yield-limiting defects and process excursions. The main decision parameters are: • Placement of the inspections (which process steps/process tools) • Type of inspections (test wafer, product, or in-situ inspections) • Inspection frequency (percent lots to sample, number of wafers per lot, area per wafer) • Inspection sensitivity to use • Which parameters to track and respond to (Statistical Process Control scheme), • The fraction of defects to review • Inspection tool capacity All these parameters are inter-related, and each one gives rise to a set of variables that need to be understood. KLA-Tencor’s Sample Planner 3 (SP3) cost model provides the framework and tools to analyze critical fab parameters to develop an optimal inspection strategy with reasonable effort. By combining it with analysis performed during fab planning, the fab plan can be devised to have inherent advantages in yield management. In its simplest form, the cost model methodology is based around a recurring in- and out-of-control cycle occurring at each step in the process. A cycle starts where each step in the process is assumed to have an in-control mode of operation, which delivers a high yield. After a random length of time, an excursion takes place, causing lower yields. At this point, the inspection sampling strategy determines how quickly the excursion is caught and fixed, restarting the in- and out-ofcontrol cycle. It is sought to minimize financial loss by catching the excursions quickly, i.e., minimizing the time between excursion start and detection. It is here that accounting for yield management during fab planning is relevant. A significant portion of the delay to excursion detection is simply the time to get lots to the inspection tools. If a fab has badly placed tools and/or automated material handling systems that cannot accommodate

the extra handling loads due to yield management, detection delays can be unnecessarily long and costly. Planning to prevent this type of problems is simply a classic sample planning problem with a greater focus on material handling and cycle-time modeling to provide the data needed that characterize a fab layout. Therefore, outputs of material handling and cycle-time modeling performed during fab planning need to be made available to sample planning analysts who, in turn, can give feedback on the current fab plan strengths and weaknesses in excursion detection. The importance of having short detection delays to achieve the accelerated, and very valuable, yield learning rates should also be noted. Fab planning with sample planner 3

Involving SP3 in fab planning requires the fab to provide good models for material-handling and cycle-time estimation. Then, by combining the outputs of these models with pilot line or applicable 200 mm data to characterize process variance and defect/excursion behavior, SP3 can quantify the yield losses to excursions. Typical analysis may involve the comparison of farm and hybrid layouts. A farm layout is where all the metrology tools are kept in a separate bay, while a hybrid layout has the metrology tools in the same bay as the process tools they are monitoring. A good materials handling model will be able to provide the travel times as a function of the track layouts, number of stockers, number of automated vehicles, the load on the system, etc. Joining that with a cycle-time model that accounts for processing and queuing times, a comprehensive estimation of how long it will take lots to reach their inspections is realized for both the farm and hybrid layout. SP3 can than use these results to quantify which layout will cause greater yield loss to excursions. Assuming that the material handling system and the number of inspection tools used is the same for both layouts considered, the differentiation comes down to the losses due to excursions. The analysis can clearly involve greater complexity where the cost of different material handling options and inspection tool capacity needs to be accounted for as well. Initial 300 mm work and past experience have highlighted the following as the main drivers for inspection capacity: • Fab output (square centimeters of silicon/week) • ASP/product Winter 2002

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• Excursion frequency, types, magnitude, & yield impact • Tool capability/sensitivity • Material handling in fab/distance to inspection tools • Inspection tool throughput/queuing Conclusion

The economies of scale that are achieved with the 300 mm initiative have a flipside when it comes to yield management. The value of the material on each wafer is greater and more sensitive to excursions than ever before, calling for a much more careful planning and deployment of inspection capacity. Of concern is the possible emergence of new inspection points that are detailed in this paper. This is particularly relevant given the level of automation that is planned for 300 mm fabs that make it harder to alter layouts after the fact. Unless a fab correctly accounts for yield management during fab planning, there is risk of giving a fab an inherent handicap in yield management and losing considerable amounts of material to excursions. Those losses can significantly affect the gains foreseen from the economies of scale that drive the 300 mm initiative. References 1. Chatterjee, A. Personal Communication, Nov-Dec 2000, KLA-Tencor, San Jose, CA.

REE F IT S

2. R. Elliott, R. K. Nurani, S. Lee, L. Ortiz, M. Preil, G. Shanthikumar, T. Riley, and G. Goodwin, “Sampling plan optimization for detection of lithography and etch CD process excursions,” in proceedings of SPIE Metrology, Inspection, and Process Control for Microlithography XIV, vol. 3998, pages 527-536, 2000. 3. Nurani, R., Gudmundsson, D., Preil, M., Nasongkhla, R., Shanthikumar, G. Critical dimension sample planning for sub-0.25 micron processes. Proceedings of the 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, September 8 - 10, 1999. 4. Nurani, R.K., Gudmundsson, D., Stoller, M., Shanthikumar, G. Intelligent Sampling Strategies for Combined Optical/E-beam inspection. Yield Management Solutions, Vol 2, Issue 2, Spring 2000, p 28. 5. Wright, R. et al., “300 mm Factory Layout and Automated Material Handling”, Solid State Technology, December 1999. 6. Campbell, E. et al., “Simulation Modeling for 300 mm Semiconductor Factories”, Solid State Technology, October 2000. 7. Williams, R.R., Gudmundsson, D., Monahan, K., Nurani, R., Stoller, M., Shanthikumar, G. Optimized Sample Planning for Wafer Defect Inspection. IEEE International Symposium on Semiconductor Manufacturing, Santa Clara, California, October 11-13, 1999. 8. S. A. Kekare, et al. “Integration issues in effective removal of SiON anti reflective coating used in deep sub-micron CMOS gate layer definition.” MRS meeting-Spring 2000. Reprinted with permission from Semiconductor Fabtech. This ar ticle was originally published in Fabtech, Edition 15. http://www.semiconductorfabtech.com

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