SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner power pins.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY
CONNECTION DIAGRAM DIP (TOP VIEW) VCC
CD1
CP1
K2
CD2
CP2
J2
14
13
12
11
10
9
8
J SUFFIX CERAMIC CASE 632-08 14 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
1
2
3
4
5
6
7
J1
Q1
Q1
K1
Q2
Q2
GND
N SUFFIX PLASTIC CASE 646-06
14 1
LOGIC SYMBOL 1 1
J
14
2 Q
3
8
J
9
CP
11
K
1
Q
D SUFFIX SOIC CASE 751A-02
5
ORDERING INFORMATION 12
CP
4
K
CD
Q
2
CD
Q
SN54LSXXXJ SN74LSXXXN SN74LSXXXD
6
Ceramic Plastic SOIC
10
13 VCC = PIN 14 GND = PIN 7
GUARANTEED OPERATING RANGES Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54 74
4.5 4.75
5.0 5.0
5.5 5.25
V
TA
Operating Ambient Temperature Range
54 74
– 55 0
25 25
125 70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54 74
4.0 8.0
mA
FAST AND LS TTL DATA 5-1