SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
J SUFFIX CERAMIC CASE 620-09 16 1
Q
Q 6(7)
5(9)
CLEAR (CD) 15(14) J 3(11)
SET (SD) 4(10) K 2(12)
N SUFFIX PLASTIC CASE 648-08
16 1
1(13) CLOCK (CP)
D SUFFIX SOIC CASE 751B-03
16 1
ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD
MODE SELECT — TRUTH TABLE INPUTS
OUTPUTS
Ceramic Plastic SOIC
OPERATING MODE Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold
SD
CD
J
K
Q
Q
L H L H H H H
H L L H H H H
X X X h l h l
X X X h h l l
H L H q L H q
L H H q H L q
LOGIC SYMBOL 4
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
10
SD Q
SD Q
9
CP
13
K CD Q
6 12 K C Q D
7
3
J
1 2
5
11
VCC = PIN 16 GND = PIN 8
5-1
CP
14
15
FAST AND LS TTL DATA
J