SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
J SUFFIX CERAMIC CASE 620-09 16 1
Q
Q 6(7)
5(9)
CLEAR (CD) 15(14) J 3(11)
SET (SD) 4(10) K 2(12)
N SUFFIX PLASTIC CASE 648-08
16 1
1(13) CLOCK (CP)
D SUFFIX SOIC CASE 751B-03
16 1
ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD
MODE SELECT — TRUTH TABLE INPUTS
OUTPUTS
Ceramic Plastic SOIC
OPERATING MODE Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold
SD
CD
J
K
Q
Q
L H L H H H H
H L L H H H H
X X X h l h l
X X X h h l l
H L H q L H q
L H H q H L q
LOGIC SYMBOL 4
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
10
SD Q
SD Q
9
CP
13
K CD Q
6 12 K C Q D
7
3
J
1 2
5
11
VCC = PIN 16 GND = PIN 8
5-1
CP
14
15
FAST AND LS TTL DATA
J
SN54/74LS112A GUARANTEED OPERATING RANGES Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54 74
4.5 4.75
5.0 5.0
5.5 5.25
V
TA
Operating Ambient Temperature Range
54 74
– 55 0
25 25
125 70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54 74
4.0 8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol
P Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
O Output HIGH Voltage V l
VOL
Output LOW Voltage
IIH
IIL
Input HIGH Current
Input LOW Current
Min
Typ
Max
2.0 54
0.7
74
0.8 – 0.65
– 1.5
U i Unit
T C di i Test Conditions
V
Guaranteed Input HIGH Voltage for All Inputs
V
Guaranteed Input p LOW Voltage g for All Inputs
V
VCC = MIN, IIN = – 18 mA
54
25 2.5
35 3.5
V
74
2.7
3.5
V
MAX, VIN = VIH VCC = MIN MIN,, IOH = MAX, or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
J, K Set, Clear Clock
20 60 80
µA
VCC = MAX, VIN = 2.7 V
J, K Set, Clear Clock
0.1 0.3 0.4
mA
VCC = MAX, VIN = 7.0 V
– 0.4 – 0.8
mA
VCC = MAX, VIN = 0.4 V
– 100
mA
VCC = MAX
6.0
mA
VCC = MAX
J, K Clear, Set, Clk
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
– 20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol
P Parameter
fMAX
Maximum Clock Frequency
tPLH tPHL
Propagation Delay, p g y, Clock Clear, Set to Output
Min
Typ
30
45
Max
U i Unit
T Test C Conditions di i
MHz
15
20
ns
15
20
ns
Max
U i Unit
VCC = 5.0 50V CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol
P Parameter
Min
Typ
tW
Clock Pulse Width High
20
ns
tW
Clear, Set Pulse Width
25
ns
ts
Setup Time
20
ns
th
Hold Time
0
ns
FAST AND LS TTL DATA 5-2
T Test C Conditions di i
VCC = 5 5.0 0V