SN54/74LS173A 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organized systems. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either Output Enable line (OE1, OE2) brings the output to a high impedance state without affecting the actual register contents. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP), the Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines. • Fully Edge-Triggered • 3-State Outputs • Gated Input and Output Enables • Input Clamp Diodes Limit High-Speed Termination Effects
4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY
J SUFFIX CERAMIC CASE 620-09 16 1
CONNECTION DIAGRAM DIP (TOP VIEW) MR
VCC 16
D0 14
15
D1 13
D2 12
D3 11
IE2 10
IE1 9
N SUFFIX PLASTIC CASE 648-08
16 1
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
D SUFFIX SOIC CASE 751B-03
16
1 OE1
2 OE2
3 Q0
4 Q1
5 Q2
6 Q3
7 CP
1
8 GND
ORDERING INFORMATION
PIN NAMES
LOADING (Note a) HIGH
D0 – D3 IE1 – IE2 OE1 – OE2 CP MR Q0 – Q3
SN54LSXXXJ SN74LSXXXN SN74LSXXXD
Data Inputs Input Enable (Active LOW) Output Enable (Active LOW) Inputs Clock Pulse (Active HIGH Going Edge) Input Master Reset Input (Active HIGH) Outputs (Note b)
Ceramic Plastic SOIC
LOW
0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L.
0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L.
0.5 U.L. 65 (25) U.L.
0.25 U.L. 15 (7.5) U.L.
NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.
LOGIC SYMBOL 9 10
14 13 12 11
1 2 IE CP
7 1 2
1 2
D0 D1 D2 D3
OE MR
Q0 Q1 Q2 Q3
15
3 4 5 6
VCC = PIN 16 GND = PIN 8
FAST AND LS TTL DATA 5-1
SN54/74LS173A LOGIC DIAGRAM D0
D1 14
IE1
9
IE2
10
D2 13
D3 12
11
CP 7
CP D Q MR
15
OE1
1
OE2
2
D
D
D
Q
3
4
Q0
5
Q1
6
Q2
Q3
VCC = PIN 16 GND = PIN 8 = PIN NUMBERS
TRUTH TABLE MR
CP
IE1
IE2
Dn
Qn
H L L L L L
x L
x x H x L L
x x x H L L
x x x x L H
L Qn Qn Qn L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
When either OE1, or OE2 are HIGH, the output is in the off state (High Impedance); however this does not affect the contents or sequential operation of the register.
GUARANTEED OPERATING RANGES Min
Typ
Max
Unit
VCC
Symbol Supply Voltage
Parameter 54 74
4.5 4.75
5.0 5.0
5.5 5.25
V
TA
Operating Ambient Temperature Range
54 74
– 55 0
25 25
125 70
°C
IOH
Output Current — High
54 74
– 1.0 – 2.6
mA
IOL
Output Current — Low
54 74
12 24
mA
FAST AND LS TTL DATA 5-2
SN54/74LS173A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol
Min
P Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOZH IOZL IIH
Input HIGH Current
IIL
Input LOW Current
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Typ
Max
U i Unit
2.0 54
0.7
74
0.8 – 0.65
– 1.5
T Test C Conditions di i
V
Guaranteed Input HIGH Voltage for All Inputs
V
Guaranteed Input p LOW Voltage g for All Inputs
V
VCC = MIN, IIN = – 18 mA
54
2.4
3.4
V
74
2.4
3.1
V
VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table
54, 74
0.25
0.4
V
IOL = 12 mA
74
0.35
0.5
V
IOL = 24 mA
Output Off Current HIGH
20
µA
VCC = MAX, VO = 2.7 V
Output Off Current LOW
– 20
µA
VCC = MAX, VO = 0.4 V
20
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
– 0.4
mA
VCC = MAX, VIN = 0.4 V
– 130
mA
VCC = MAX
30
mA
VCC = MAX
– 30
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C) Limits S b l Symbol
P Parameter
Min
Typ
30
50
Max
U i Unit
T Test C Conditions di i
fMAX
Maximum Input Clock Frequency
MHz
tPLH tPHL
Propagation Delay, Clock to Output
17 22
25 30
ns
tPHL
Propagation Delay, MR to Output
26
35
ns
tPZH tPZL
Output Enable Time
15 18
23 27
ns
tPLZ tPHZ
Output Disable Time
11 11
17 17
ns
CL = 5.0 pF, RL = 667 Ω
Max
U i Unit
T Test C Conditions di i
VCC = 5.0 50V CL = 45 pF, pF RL = 667 Ω
AC SETUP REQUIREMENTS (TA = 25°C) Limits S b l Symbol
P Parameter
Min
Typ
tW
Clock or MR Pulse Width
20
ns
ts
Data Enable Setup Time
35
ns
ts
Data Setup Time
17
ns
th
Hold Time, Any Input
0
ns
trec
Recovery Time
10
ns
FAST AND LS TTL DATA 5-3
VCC = 5.0 50V
SN54/74LS173A
AC WAVEFORMS 1 / fmax
CP
tW 1.3 V ts(H)
D or E
MR 1.3 V
th(H)
ts(L)
tW th(L)
trec 1.3 V
CP
1.3 V
1.3 V
tPHL Q
1.3 V
tPLH
Q
1.3 V
1.3 V
tPHL
Figure 1
VE
Figure 2
1.3 V
VE
1.3 V tPLZ
1.3 V 0.5 V
1.3 V tPZH
tPZL
VOUT
1.3 V
VOUT
tPHZ
1.3 V
VOL
Figure 3
Figure 4
AC LOAD CIRCUIT VCC
RL
SWITCH POSITIONS SYMBOL
SW1 TO OUTPUT UNDER TEST
SW1
SW2
tPZH
Open
Closed
tPZL
Closed
Open
tPLZ
Closed
Closed
tPHZ
Closed
Closed
5 kΩ CL*
SW2
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA 5-4
≥ VOH ≈ 1.3 V 0.5 V