SN54/74LS76A DUAL JK FLIP-FLOP WITH SET AND CLEAR The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.
DUAL JK FLIP-FLOP WITH SET AND CLEAR LOW POWER SCHOTTKY
J SUFFIX CERAMIC CASE 620-09
MODE SELECT — TRUTH TABLE INPUTS
OUTPUTS
16
OPERATING MODE Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold
SD
CD
J
K
Q
Q
L H L H H H H
H L L H H H H
X X X h l h l
X X X h h l l
H L H q L H q
L H H q H L q
1
N SUFFIX PLASTIC CASE 648-08
16 1
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H,h = HIGH Voltage Level L,l = LOW Voltage Level X = Immaterial l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the HIGH-to-LOW clock transition
D SUFFIX SOIC CASE 751B-03
16 1
ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD
Ceramic Plastic SOIC
LOGIC DIAGRAM LOGIC SYMBOL Q
CLEAR (CD)
K
SD Q
16
K
1
CP
4
J C Q D
SET (SD)
J
7
2
Q
15
14
SD Q
11
6
CP
9
J C Q D
10
12
K
3
8 VCC = PIN 5 GND = PIN 13
CLOCK (CP)
FAST AND LS TTL DATA 5-1