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Reg. No. : .................................... Name : .........................................
Third Semester B.Tech. Degree Examination, November 2009 (2008 Scheme) Branch : Electronics and Communication 08.306 – DIGITAL ELECTRONICS (T) Time : 3 Hours
Max. Marks : 100 PART – A
Answer all questions. Each question carries 4 marks. 1. Represent the decimal number 258710 a) In BCD c) As a hexadecimal number
b) In excess three code d) As a binary number
2. Show that the dual of the exclusive -OR is equal to its complement. 3. Determine the complement of F = ABC + ABD using a) Demorgan’s law b) Using a Karnaugh map 4. What is an equivalence gate ? Explain. 5. Show the logic level ranges and DC noise margin for TTL. 6. Write down the characteristic equation of a T flip flop. 7. How do JK flip flops can be used as a Mod-8 counter. 8. Draw the block diagram of Mealy and Moore state machines. 9. What is meant by static hazards ? Draw the circuit with a static 1 hazard and static 1 hazard free circuit. 10. Which are the differences among a truth table, state table, characteristic table and excitation table ? P.T.O.
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PART – B Answer any two questions from each module. Each question carries 10 Marks. MODULE – I 11. Simplify the following equation using Quine -Mcluskey minimization Technique Y = f (u,w,x,y,z) = Σ (1,3,4,6,9,11,12,14,17,19,20,22,25,27,28,30) 12. a) Construct a 4 to 16 line decoder with five 2 to 4 line decoder with enable. b) Show how a full adder can be used to subtract. 13. a) Design a combinational circuit that compares two four bit numbers to check if they are equal. b) Write a note on VHDL. MODULE – II 14. a) List various TTL parameters. b) Describe a 4 bit universal shift register. 15. A sequential circuit has two flipflop (A and B), two inputs (x and y) and output (z). The flip flop input functions and the circuit output function are as follows. JA = xB + yB JB = XA KA = xyB
KB = xy + A
Z = xyA + x yB
Obtain the logic diagram, state table, state diagram and state equations. 16. Design a counter that goes through states 0,2,4,6,0. If the control line is high and goes through states 0,4,2,7,0 if the control line is low.
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MODULE – III 17. a) Construct the state diagram for a Mealy sequential circuit that will detect the serial input sequence x = 010110. When the complete sequence has been detected, then output Z = 1. b) Distinguish between fundamental and pulse mode asynchronous sequential circuits. 18. Draw the logic diagram of the product of Sums expression Y = (x1 + x ′2 )(x 2 + x 3 ). Show that there is a static 0-hazard when x1 and x3 are equal to 0 and x2 goes from 0 to 1. Find a way to remove the hazard by adding one more OR gate. 19. a) Describe the purpose and draw block diagram of a data synchronizer. b) Sketch and explain mixed operating mode asynchronous circuits.
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