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FinFET Devices for VLSI Circuits and Systems 1st Edition Samar K. Saha (Author)
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Library of Congress Cataloging‑in‑Publication
Data
Names: Kurinec, Santosh K., editor. | Walia, Sumeet, editor.
Title: Energy efficient computing & electronics : devices to systems / edited by Santosh K. Kurinec and Sumeet Walia.
Other titles: Energy efficient computing and electronics
Description: Boca Raton : CRC/Taylor & Francis, [2019] | Series: Devices, circuits, & systems | Includes bibliographical references and index.
Identifiers: LCCN 2018042978| ISBN 9781138710368 (hardback : alk. paper) | ISBN 9781315200705 (ebook)
Subjects: LCSH: Electronic apparatus and appliances--Power supply. | Computer systems--Energy conservation. | Low voltage systems. | Wireless communication systems--Energy conservation.
1. A FinFET-Based Framework for VLSI Design at the 7 nm Node 3 Vinay Vashishtha and Lawrence T. Clark
2. Molecular Phenomena in MOSFET Gate Dielectrics and Interfaces 51 S. Arash Sheikholeslam, Hegoi Manzano, Cristian Grecu, and Andre Ivanov
3. Tunneling Field Effect Transistors 67 Amir N. Hanna and Muhammad Mustafa Hussain
4. The Exploitation of the Spin-Transfer Torque Effect for CMOS Compatible Beyond Von Neumann Computing .................................................................................. 93 Thomas Windbacher, Alexander Makarov, Siegfried Selberherr, Hiwa Mahmoudi, B. Gunnar Malm, Mattias Ekström, and Mikael Östling
5. Ferroelectric Tunnel Junctions as Ultra-Low-Power Computing Devices 157 Spencer Allen Pringle and Santosh K. Kurinec
Section II Sensors, Interconnects, and Rectifiers
6. X-ray Sensors Based on Chromium Compensated Gallium Arsenide (HR GaAs:Cr) ...................................................................................................................... 167 Anton Tyazhev and Oleg Tolbanov
7. Vertical-Cavity Surface-Emitting Lasers for Interconnects ...................................... 195 Werner H. E. Hofmann
8. Low-Power Optoelectronic Interconnects on Two-Dimensional Semiconductors ................................................................................................................ 215 D. Keith Roper
9. GaN-Based Schottky Barriers for Low Turn-On Voltage Rectifiers ........................ 239 Nishant Darvekar and Santosh K. Kurinec
10. Compound Semiconductor Oscillation Device Fabricated by Stoichiometry
Controlled-Epitaxial Growth and Its Application to Terahertz and Infrared Imaging and Spectroscopy 267
Takeo Ohno, Arata Yasuda, Tadao Tanabe, and Yutaka Oyama
Section III Systems Design and Applications
11. Low Power Biosensor Design Techniques Based on Information Theoretic Principles ...........................................................................................................
Nicole McFarlane
12. Low-Power Processor Design Methodology: High-Level Estimation and Optimization via Processor Description Language 301
Zheng Wang and Anupam Chattopadhyay
13. Spatio-Temporal Multi-Application Request Scheduling in Energy-Efficient Data Centers ........................................................................................................................ 343
Haitao Yuan, Jing Bi, and MengChu Zhou
14. Ultra-Low-Voltage Implementation of Neural Networks .......................................... 379 Farooq Ahmad Khanday, Nasir Ali Kant, and Mohammad Rafiq Dar
15. Multi-Pattern Matching Based Dynamic Malware Detection in Smart Phones .....
V. S. Devi, S. Roopak, Tony Thomas, and Md. Meraj Uddin
Preface
Performance of electronic systems are limited by energy inefficiencies that result in overheating and thermal management problems. Energy efficiency is vital to improving performance at all levels. This includes transistors to devices and to large Internet Technology and electronic systems, as well from small sensors for the Internet-of-Things (IoT) to large data centers in cloud and supercomputing systems. The electronic circuits in computer chips still operate far from any fundamental limits to energy efficiency. A report issued by the Semiconductor Industry Association and Semiconductor Research Corporation bases its conclusions on system-level energy per bit operation, which are a combination of many components such as logic circuits, memory arrays, interfaces, and I/Os. Each of these contributes to the total energy budget. For the benchmark energy per bit, as shown in Figure 1, computing will not be sustainable by 2040. This is when the energy required for computing is estimated to exceed the world’s estimated energy production. The “benchmark” curve shows the growing energy demand for the system level energy per bit values of mainstream systems. The target system curve uses the practical lower limit system level energy per bit value, set by factors such as materials. The Landauer limit curve uses the minimal device energy per bit value provided by the Landauer’s Principle that relates to the Second Law of Thermodynamics to computation. As such, significant improvement in the energy efficiency of computing is needed.
There is a consensus across the many technologies touched by our ubiquitous computing infrastructure that future performance improvements across the board are now severely limited by the amount of energy it takes to manipulate, store, and critically transport data. Revolutionary device concepts, sensors, and associated circuits and architectures that will greatly extend the practical engineering limits of energy-efficient computation are being investigated. Disruptive new device architectures, semiconductor processes, and emerging
FIGURE 1
Estimated total energy expenditure for computing, directly related to the number of raw bit transitions. Source: SIA/SRC (Rebooting the IT Revolution: A Call to Action, Semiconductor Industry Association, September 2015).
new materials aimed at achieving the highest level of computational energy efficiency for general purpose computing systems need to be developed. This book will provide chapters dedicated to some of such efforts from devices to systems.
The book is divided into three sections each consisting of five chapters.
Section I is dedicated to device level research in developing energy efficient device structures.
Non-planar finFETs dominate highly scaled processes, such as sub-20 nm, CMOS processes, due to their ability to provide lower leakage and enable continued power supply scaling (VDD). Chapter 1 gives a comprehensive overview of the finFET-based predictive process design kit (PDK) that supports investigation into both the circuit as well as physical design, encompassing all aspects of digital design. Prevention of various degradation mechanisms in transistors is the key to increase the reliability and efficiency of electronic systems. Chapter 2 discusses the understanding of molecular phenomena at the MOSFET channel/dielectric interface, focussing on ZrO2 system aimed at minimizing the degrading mechanisms in transistors. Chapter 3 provides an important insight into the nanotube Tunneling field effect transistors (TFETs) device, which promise to exhibit steep slope faster than the Boltzmann limit of 60 mV/dec. TFETs address two major challenges faced by aggressively scaled conventional CMOS technology; scaling the supply voltage (VDD) and minimizing the leakage currents. Chapter 4 gives an in-depth introduction and potential of spin based devices. It gives an overview of spintronic devices, circuits, and architecture levels that include thermally assisted (TA)-MRAM, STT-MRAM, domain wall (DW)-MRAM, spin-orbit torque (SOT)-MRAM, spin-transfer torque and spin Hall oscillators, logic-in-memory, all-spin logic, buffered magnetic logic gate grid, ternary content addressable memory (TCAM), and random number generators. A large bottleneck for energy efficiency has long been the information storage units, which typically rely on charge-storage for programming and erasing. Chapter 5 describes the promise of ferroelectric tunnel junctions (FTJs) as memristors. Memristor-based logic systems for XOR, XNOR, full-adder, DAC, and ADC outperform CMOS with as low as 50% the delay and 0.1% the power consumption.
Section II deals with sensors, interconnects, and rectifiers aimed at consuming lower power.
Chapter 6 provides insight into X-ray sensors based on chromium compensated GaAs for the development of modern X-ray imaging systems. Chapters 7 and 8 deal with optical interconnects, which are actively being pursued to reduce power requirements and increase speed. Chapter 7 provides an overview of the challenges and developments of various types of Vertical-Cavity Surface-Emitting Laser (VCSEL)-based interconnects. Optoelectronic interactions at interconnective hetero-interfaces between nanoparticles and two-dimensional semiconductors, motivated by their enhancement of electronic and photonic properties are described in Chapter 8 Chapter 9 investigates AlGaN/GaN heterostructures based Schottky diodes with low turn-on voltage of Vf < 0.4V, and high breakdown voltage of V br > 400V for applications in energy efficient 230V AC-DC rectifiers. In Chapter 10, the authors have discussed the stoichiometry-controlled crystal growth technique and its application to compound semiconductor oscillation devices for extending to THz region The THz wave generators can be used in applications of non-destructive evaluation, safe for human tissues.
Section III has five chapters aimed at low power system designs.
The imminent concern of inherent physical noise with low power biosensing mixed signal CMOS technology is addressed in Chapter 11. The information rate and bit energy have been incorporated into a design methodology for detecting weak signals in the presence
of fixed system noise. Chapter 12 provides an overview of the high-level processor architecture design methodologies using Architecture Description Languages (ADLs). Chapter 13 focuses on challenging problems related to energy-efficient Cloud Data Centers (CDC). It presents how to minimize the total cost of a CDC provider in a market, and how to migrate to green cloud data centers (GCDCs). The authors propose a Temporal Request Scheduling algorithm (TRS) that can achieve higher throughput and lower grid energy cost for a GCDC. Chapter 14 presents an innovative brain inspired approach of implementing neural network in hardware implementation for ultra-low-voltage implementation of the perceptron and the inertial neuron. The final chapter (Chapter 15) addresses a large system-level problem of malware attacks to mobile devices. It presents a multi-pattern matching based dynamic malware detection mechanism in smart phones as an alternative to machine learning based methods. The proposed mechanism is more efficient and uses fewer resources.
Thus, this book brings together a wealth of information that will serve as a valuable resource for researchers, scientists, and engineers engaged in energy efficient designs of electronic devices, circuits, and systems. The editors express their sincere appreciation to the authors who have contributed their knowledge and expertise to this book. Special thanks to Nora Konopka and Erin Harris of Taylor & Francis Group/CRC Press for their publishing efforts and coordinating with the authors. The authors also express their sincere appreciation for Joanne Hakim, project manager of Lumina Datamatics, for coordinating the production of this book.
Editors
Santosh K. Kurinec is a professor of electrical and microelectronic engineering at Rochester Institute of Technology (RIT), Rochester, New York. She received a PhD in physics from University of Delhi, India and worked as a scientist at the National Physical Laboratory, New Delhi, India. She worked as a postdoctoral research associate in the Department of Materials Science and Engineering at the University of Florida, Gainesville, Florida where she researched thin metal film composites. Prior to joining RIT, she was assistant professor of electrical engineering at Florida State University/Florida A&M University College of Engineering in Tallahassee, Florida. She is a Fellow of Institute of Electrical and Electronics Engineers (IEEE), Member APS, NY State Academy of Sciences, and an IEEE EDS Distinguished Lecturer. She received the 2012 IEEE Technical Field Award. In 2016, she received the Medal of Honor from the International Association of Advanced Materials (IAAM). She was inducted into the International Women in Technology (WiTi) Hall of Fame in 2018. She has worked on a range of materials covering magnetic, ferroelectrics, semiconductors, photonic luminescent thin films, and metal composites for device applications. Her current research activities include nonvolatile memory, advanced integrated circuit materials and processes, and photovoltaics. She has over 100 publications in research journals and conference proceedings. She can be reached at Santosh.kurinec@rit.edu.
Sumeet Walia is a senior lecturer and a Vice Chancellor’s Fellow at RMIT University, Melbourne, Australia. He is an expert in materials engineering for nanoelectronics, sensing, and wearable devices. He has been recognized as one of the Top 10 Innovators under 35 in Asia-Pacific by the MIT Technology Review in 2017, was awarded the Victorian Young Achiever Award for Research Impact in 2017, and named among the most innovative Engineers in Australia in 2018 by Engineers Australia. He can be reached at waliasumeet @ gmail.com or sumeet.walia @ rmit.edu.au.
Contributors
Jing Bi
Faculty of Information Technology
Beijing University of Technology Beijing, China
Anupam Chattopadhyay
School of Computer Science and Engineering
Nanyang Technological University
Singapore
Lawrence T. Clark
School of Electrical, Computer, and Energy Engineering
Arizona State University Tempe, Arizona, USA
Mohammad Rafiq Dar
Department of Electronics and Instrumentation Technology University of Kashmir Srinagar, India
Nishant Darvekar
Electrical and Microelectronic Engineering
Rochester Institute of Technology Rochester, New York, USA
V. S. Devi
Department of Computer Science
Indian Institute of Information Technology and Management – Kerala (IIITM-K) Thiruvananthapuram, India
Mattias Ekström
Department of Electronics
KTH Royal Institute of Technology Kista, Sweden
Cristian Grecu
Department of Electrical and Computer Engineering
University of British Columbia Vancouver, British Columbia, Canada
Amir N. Hanna
Department of Electrical Engineering
King Abdullah University of Science and Technology (KAUST) Thuwal, Saudi Arabia
Werner H. E. Hofmann
Institute of Solid State Physics and Center of Nanophotonics
Technical University of Berlin Berlin, Germany
Muhammad Mustafa Hussain
Department of Electrical Engineering
King Abdullah University of Science and Technology (KAUST) Thuwal, Saudi Arabia
Andre Ivanov
Department of Electrical and Computer Engineering
University of British Columbia Vancouver, British Columbia, Canada
Nasir Ali Kant
Department of Electronics and Instrumentation Technology University of Kashmir Srinagar, India
Farooq Ahmad Khanday
Department of Electronics and Instrumentation Technology University of Kashmir Srinagar, India
Santosh K. Kurinec
Electrical and Microelectronic Engineering
Rochester Institute of Technology Rochester, New York, USA
Hiwa Mahmoudi
Institute of Electrodynamics, Microwave and Circuit Engineering
TU Wien
Vienna, Austria
Alexander Makarov Institute for Microelectronics TU Wien
Vienna, Austria
B. Gunnar Malm Department of Electronics
KTH Royal Institute of Technology Kista, Sweden
Hegoi Manzano
Department of Condensed Matter Physics University of the Basque Country UPV/ EHU
Barrio Sarriena s/n, 48330 Leioa, Bizkaia, Spain
Nicole McFarlane
Min H. Kao Department of Electrical Engineering & Computer Science
Tickle College of Engineering The University of Tennessee Knoxville, Tennessee, USA
Takeo Ohno
Department of Innovative Engineering Oita University Oita, Japan
Mikael Östling Department of Electronics
KTH Royal Institute of Technology Kista, Sweden
Yutaka Oyama Department of Materials Science and Engineering
Tohoku University Sendai, Japan
Spencer Allen Pringle Electrical & Microelectronic Engineering
Rochester Institute of Technology Rochester, New York, USA
S. Roopak
Department of Computer Science Indian Institute of Information Technology and Management – Kerala (IIITM-K) Thiruvananthapuram, India
D. Keith Roper
Ralph E. Martin Department of Chemical Engineering and Microelectronics-Photonics Graduate Program and Institute for Nanoscience and Engineering University of Arkansas Fayetteville, Arkansas, USA
Siegfried Selberherr Institute for Microelectronics TU Wien Vienna, Austria
S. Arash Sheikholeslam
Department of Electrical and Computer Engineering University of British Columbia Vancouver, British Columbia, Canada
Tadao Tanabe
Department of Materials Science and Engineering Tohoku University Sendai, Japan
Tony Thomas
Department of Computer Science
Indian Institute of Information Technology and Management – Kerala (IIITM-K)
Thiruvananthapuram, India
Oleg Tolbanov
Functional Electronics Laboratory
Tomsk State University
Tomsk, Russia
Anton Tyazhev
Functional Electronics Laboratory
Tomsk State University
Tomsk, Russia
Md. Meraj Uddin
Department of Computer Science
Indian Institute of Information Technology and Management – Kerala (IIITM-K)
Thiruvananthapuram, India
Vinay Vashishtha
School of Electrical, Computer, and Energy Engineering
Arizona State University
Tempe, Arizona, USA
Zheng Wang
Shenzhen Institute of Advanced Technology
Chinese Academy of Sciences Beijing, China
Thomas Windbacher Institute for Microelectronics TU Wien Vienna, Austria
Arata Yasuda Department of Creative Engineering
National Institute of Technology Tsuruoka College Tsuruoka, Japan
Haitao Yuan School of Software Engineering Beijing Jiaotong University Beijing, China
MengChu Zhou
Helen and John C. Hartmann Department of Electrical and Computer Engineering
New Jersey Institute of Technology Newark, New Jersey, USA
Section I
Emerging Low Power Devices
A FinFET-Based Framework for VLSI
Vinay Vashishtha and Lawrence T. Clark
1.8.1
1.1 Introduction
Recent years have seen finFETs dominate highly scaled (e.g., sub-20 nm) complementary metal-oxide-semiconductor (CMOS) processes (Wu et al. 2013; Lin et al. 2014) due to their ability to alleviate short channel effects, provide lower leakage, and enable some continued VDD scaling. However, availability of a realistic finFET-based predictive process design kit (PDK) for academic use that supports investigation into both circuit, as well as physical design, encompassing all aspects of digital design, has been lacking. While the finFET-based FreePDK15 was supplemented with a standard cell library, it lacked full physical verification, layout vs. schematic check (LVS) and parasitic extraction (Bhanushali et al. 2015; Martins et al. 2015) at the time of development of the PDK described in this chapter. Consequently, the only available sub-45 nm educational PDKs are the planar CMOS-based Synopsys 32/28 nm and FreePDK45 (45 nm PDK) (Stine et al. 2007; Goldman et al. 2013). The cell libraries available for those processes are not very realistic since they use very large cell heights, in contrast to recent industry trends. Additionally, the static random access memory (SRAM) rules and cells provided by these PDKs are not realistic. Because finFETs have a 3-D structure and result in significant density impact, using planar libraries scaled to sub-22 nm dimensions for research is likely to give poor accuracy.
Commercial libraries and PDKs, especially for advanced nodes, are often difficult to obtain for academic use and access to the actual physical layouts is even more restricted. Furthermore, the necessary
(NDAs) are unmanageable
large university classes, and the plethora of design rules can distract from the key points. NDAs also make it difficult for the publication of physical design as these may disclose proprietary design rules and structures.
This chapter focuses on the development of a realistic PDK for academic use that overcomes these limitations. The PDK, developed for the N7 node even before 7 nm processes were available in the industry, is thus predictive. The predictions have been based on publications of the continually improving lithography, as well as our estimates of what would be available at N7. The original assumptions are described in Clark et al. (2016). For the most part, these assumptions have been accurate, except for the expectation that extreme ultraviolet (EUV) lithography would be widely available, which has turned out to be optimistic. The background and impact on design technology co-optimization (DTCO) for standard cells and SRAM comprises this chapter. The treatment here includes learning from using the cells originally derived in Clark et al. (2016) in realistic designs of SRAM arrays and large digital designs using automated place and route tools.
1.1.1 Chapter Outline
The chapter first outlines the important lithography considerations in Section 1.3. Metrics for overlay, mask errors and other effects that limit are described first. Then, modern liquid immersion optical lithography and its use in multiple patterning (MP) techniques that extend it beyond the standard 80 nm feature limit are discussed. This sets the stage for a discussion of EUV lithography, which can expose features down to about 16 nm in a single exposure, but at a high capital and throughput cost. This section ends with a brief overview of DTCO. DTCO has been required on recent processes to ensure that the very limited possible structures that can be practically fabricated are usable to build real designs. Thus, a key part of a process development is not just to determine transistor and interconnect structures that are lithographically possible, but also ensuring that successful designs can be built with those structures. This discussion is carried out by separating the front end of line (FEOL), middle of line (MOL), and back end of line (BEOL) portions of the process, which fabricate the transistors, contacts and local interconnect, and global interconnect metallization, respectively. The cell library architecture and automated placement and routing (APR) aspects comprise the next section, which with the SRAM results, comprise most of the discussion. The penultimate section describes the SRAM DTCO and array development and performance in the ASAP7 predictive PDK. The final chapter section summarizes.
1.2 ASAP7 Electrical Performance
The PDK uses BSIM-CMG SPICE models and the value used are derived from publicly available sources with appropriate assumptions (Paydavosi et al. 2013). Drive current increase from 14 to 7 nm node is assumed to be 15%, which corresponds to the diminished Idsat improvement over time. In accordance with modern devices, saturation current was assumed to be 4.5× larger than that in the linear region (Clark et al. 2016). A relaxed 54 nm contacted poly pitch (CPP) allows a longer channel length and helps
with the assumption of a near ideal subthreshold slope (SS) of 60 mV/decade at room temperature, along with a drain-induced barrier lowering (DIBL) of approximately 30 mV/V. P-type metal-oxide-semiconductor (PMOS) strain seems to be easier to obtain according to the 16 and 14 nm foundry data and larger Idsat values for PMOS than those for n-type metal-oxide-semiconductor (NMOS) have been reported (Wu et al. 2013; Lin et al. 2014). Following this trend, we assume a PMOS to NMOS drive ratio of 0.9:1. This value provides good slew rates at a fan-out of six (FO6), instead of the traditional four.
Despite the same drawn gate length, the PDK and library timing abstract views support four threshold voltage flavors, viz. super low voltage threshold (SLVT), low voltage threshold (LVT), regular threshold voltage (RVT), and SRAM, to allow investigation into both high performance and low-power designs. The threshold voltage is assumed to be changed through work function engineering. For SRAM devices the very low leakage using both a work function change and lightly doped drain (LDD) implant removal. The latter results in an effective channel length (Leff) increase, GIDL reduction and, the overlap capacitance reduction. The drive strength reduces from SLVT to SRAM. The SRAM Vth transistors are convenient option for use in retention latches and designs that prioritize low-standby power. In addition to typical-typical (TT) models, fast-fast (FF) and slow-slow (SS) models are also provided for multi-corner APR optimization. Tables 1.1 and 1.2 show the electrical parameters for single fin NMOS and PMOS, respectively, for the TT corner at 25 ° C (Clark et al. 2016). The nominal operating voltage is VDD = 700 mV.
TABLE 1.1
NMOS Typical Corner Parameters (per fin) at 25°C
TABLE 1.2
PMOS Typical Corner Parameters (per fin) at 25°C
Parameter
1.3 Lithography Considerations
Photolithography, hereinafter referred to simply as lithography, in a semiconductor industry context, refers to a process whereby a desired pattern is transferred to a target layer on the wafer through use of light. Interconnect metal, via, source-drain regions, and gate layers in a CMOS process stack are a few examples of the patterns defined, or “printed,” using lithography.
A simplified pattern transfer flow is as follows. From among the pattern information that is stored in an electronic database file (GDSII) corresponding to all the layers of a given integrated circuit (IC) design, the enlarged pattern, or its photographic negative, corresponding to a single layer is inscribed onto a photomask or reticle. The shapes on the photomask, hereinafter referred to as mask, define the regions that are either opaque or transparent to light. Light from a suitable source is shone on the mask through an illuminator, which modifies the effective manner of illumination, and passes through the transparent mask regions. Thereafter, light passes through a projection lens, which shrinks the enlarged pattern geometries on the mask to their intended size, and exposes the photoresist that has been coated on the wafer atop the layer to be patterned. The photoresist is developed to either discard or retain its exposed regions corresponding to the pattern. This is followed by an etch that removes portions of the target layer not covered by the photoresist, which is then removed, leaving behind the intended pattern on the layer. Both lines and spaces can be patterned through this approach with some variations in the process steps.
Lithography plays a leading role in the scaling process, which is the industry’s primary growth driver, as it determines the extent to which feature geometries can be shrunk in successive technology nodes. Lithography is one of the most expensive and complex procedures in semiconductor manufacturing, with mask manufacturing being the most expensive processing steps within lithography (Ma et al. 2010). Both complexity and the number of masks used for manufacturing at a node affect the cost, and an increase in either of these can increase the cost to the point of becoming the limiting factor in the overall cost of the product.
As in any other manufacturing process, the various lithography steps also suffer from variability. The lithographic resolution determines the minimum feature dimension, called critical dimension (CD), for a given layer and is based on the lithography technique employed at a particular technology node. Design rules (DRs) constitute design guidelines to minimize the effects from mask manufacturability issues, the impact of variability and layer misalignment, and ensure printed pattern fidelity to guarantee circuit operation at good yield. Thus, ascertaining these DRs requires consideration of the following lithography-related metrics that can cause final printed pattern on a layer to deviate from the intent and/or result in reliability issues.
1.3.1 Lithography Metrics and Other Considerations for Design Rule Determination
1.3.1.1
Critical Dimension Uniformity (CDU)
Critical dimension uniformity (CDU) relates to the consistency in the dimensions of a feature printed in resist. CD variations arise due to a number of factors—wafer temperature and photoresist thickness, to name a few. It is defined by
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They like to run and jump and play.
Two squirrels sat upon a hickory tree.
One little squirrel said, “Run! I will catch you.
Run round and round the tree.”
The other little squirrel said, “Oh, what fun!
Catch me if you can.”
Oh, you pretty squirrel!
Come, little squirrel! Come to me. Here are some nuts for you. I like to see you eat a nut. Do not run away.
Baby Sister has some nuts for you.
Come and get the nuts.
Go away, Rover! Go away! You can not catch the squirrel.
Come and eat the nuts, little squirrel. Rover will not catch you.
Do you know how the farmer
Plants his corn in the field?
This is the way the farmer
Plants his corn in the field
Do you know how the farmer Reaps his corn in the field?
This is the way the farmer Reaps his corn in the field.
Do you know how the farmer Takes his corn to the mill?
This is the way the farmer Takes his corn to the mill
Do you know how the miller Grinds his corn in the mill? This is the way the miller Grinds his corn in the mill
This is a farmer. He is in his field.
See the farmer plant the corn. The sun makes the corn grow. The rain makes the corn grow. The wind makes it grow.
The corn will grow, and grow.
By and by the farmer will reap the corn. Then he will take it to the mill.
