Ψηφιακα ηλεκτρονικα

Boole -

-

Karnaugh -

-

- Flip Flops.

Boole (

,

,

.)

.

. . . , ,

LOW

HIGH

.

, . , on

off

LOW

HIGH

.

, ,

"1"

"0".

,

('), AND( ), OR(+) .

,

' .

, Boole

George Boole.

Boole

.

)

: ) OR ( )

)

"0",

"1",

' )

AND (

+

,

:

(

"0".

"1" ,

= ' AND AND "1", ,

.

"1".

AND

:

1

)

OR OR

"1", "1".

, AND AND

OR

: =

+

OR 1

OR

0

x 1=1 x=x x+0=0+x=x AND

OR

AND

OR

OR

AND. x (y + z) = (x y) + (x z) x + (y z) = (x + y) (x + z) (

) x

x'

:

x x' = 0 x + x' = 1 1

2

x x=x

x 0=0

x+x=x

x+1=1 De Morgan

(x y)' = x' + y'

(x y z)' = x' + y' + z'

(x + y)' = x' y'

(x + y + z)' = x' y' z'

.

(

IC)

, (

,

«chip», ,

, .

64

.

pins .

,

. chip

«pins» IC

)

14 '

IC

.

2

chip

,

,

, .

:

(Small Scale Integration SSI)

10

.

(Medium – Scale Integration MSI) 10

100

.

(Large – Scale Integration LSI)

100

.

(Very Large – Scale Integration VLSI) .

(AND, OR

.)

«

»

. .

(

)

, : TTL

.

CMOS.

: TTL (Transistor – Transistor Logic) L

,

.

L

chip . chip TTL

«

» 5400

, .

chips NAND 2-

, 7400

,

7400.

7400, 7401, 7402

7404

5V

.

,

.

L

.

TTL,

,

0,8V,

( (

5,5V.

«1»)

«0») 2,0V

0,4V

2,4V

5,5V,

.

TL

.

74

74LS. ,

standard TTL Schottky

TTL

, .

.

7400

3

.

.

7486

XOR

74LS86

. : CMOS (Complementary MOS) MOS (CMOS)

PMOS .

PMOS

NMOS

.

NMOS MOSFET

P

S ,

,

. +3V «0»,

CMOS

+15V.

70%

0

100%

«1»

5V, 3,5V

30%

0

.

1,5V,

5V.

.

5V,

,

5V 4000

,

0V.

CMOS

TTL.

TTL CMOS

TTL. A 74 C

74HCT. H

,

CMOS

74 C

,

74 CT

L. 74 CT

TTL

.

fan-out. «

»

.

10,

.

C fan-out

TTL

10

.

Schottky TTL (LS – TTL)

fan-out

fan-out 20

L 4000 CMOS

10.

fan-out

50.

4

( TTL.

)

,

'

. .

TTL

1

CMOS

LS-TTL

pull-up 2,2k

(

CMOS IC.

1k ).

5V

2

CMOS (

)

(Standard) TTL CD4050

.

3.

TTL

pull-up

CMOS,

CMOS 74HCT00

4

IC 74HCT34.

.

TTL ( (

0

IC 7404).

1)

12ns. ,

.

L

Standard TTL

IC CMOS

,

CMOS

CMOS.

HIGH TTL

LS-TTL.

CMOS

7ns.

5

. ,

,

.

AND (4081, 4073, 4082, 7408, 7411, 7421) , Boole,

,

.

.

AND ( AND (

)

)

.

AND

1,

1.

0,

0.

, AND

, :Y=A B AND

:

AND , 0 1

1.

:G=A B C D

4 2 3

,

AND

: G = (A B) (C D). :

.

6

AND CMOS CD4081, CD4073, CD4082

AND CMOS 74HC08, 74HC11, 74HC21

.

7

AND TTL compatible 74LS08, 74LS11, 74LS21, 74HCT08, 74HCT11, 74HCT21

OR (4071, 4075, 4072, 7432) OR ( ) OR ('H)

: OR ('H)

"1" (High),

=

+

"1" (High)

OR

"1" (High). :

OR ,

1 1

0

0.

: Y = (A + B) C

3 2

.

OR: G = A + B G

C

AND: Y = G C

:

.

8

OR CMOS CD4071, CD4075, CD4072

OR CMOS 74HC32

.

9

OR TTL compatible 74LS32, 74HCT32

NOT (4069, 7404, 7414) ( (

)

)

:

= '

. : (

)

,

.

2

.

,

= G' = (A')' = A

: F = A' B' C + A C' D

,

AND, NOT, OR.

F, )

:

3

, , C. ) A B C

A C D )

1

OR

2

AND 3 (+)

.

.

10

3

,

NOT CMOS CD4069, 74HC04

.

:

TTL compatible 74HCT04

11

NOT with Schimitt trigger input CMOS 74HC14 74LS14, 74HCT14

TTL compatible

NAND (4011, 4023, 4012, 4093, 7400, 7410, 7420, 74132) NAND (NOT AND) AND, OR, NOT .

NAND

AND. AND

AND

.

NAND

: Y = (A B)'

NAND

: NAND

1

0.

NAND AND, OR, NOT

NAND.

NAND

.

.

12

, AND, OR

NAND

.

NAND AND, OR, NOT. NAND

OR NAND

,

Morgan: Y = (A B)' = A' + B' OR,

NAND

De 2

:

NAND CMOS CD4011, CD4023, CD4012

.

13

NAND CMOS 74HC00, 74HC10, 74HC20

NAND TTL compatible 74LS00, 74LS10, 74LS20, 74HCT00, 74HCT10, 74HCT20

.

14

NAND with Schimitt trigger input CD4093, 74HC132, 74LS132, 74HCT132

NOR (4001, 4025, 4002, 7402, 7427) R (NOT OR) H

NOR

NOR

:

=( +

OR

.

)' OR

. :

NOR

.

1

0

15

NOR CMOS CD4001, CD4025, CD4002

NOR CMOS 74HC02, 74HC27

.

16

NOR TTL compatible 74LS02, 74LS27, 74HCT02, 74HCT27

XOR

XNOR (4070, 7486, 4077)

XOR XOR (exclusive OR)

"1",

( '

).

XOR

.

XOR

:

:

17

XOR CMOS CD4070, 74HC86

TTL compatible 74LS86, 74HCT86

XNOR XNOR (exclusive NOR)

"1", ).

XNOR

X OR

.

( ' :

:

18

XNOR CMOS CD4077

(74HC/HCT153, 74HC/HCT253, 74HC/HCT151, 74HC/HCT251) 2n

(Multiplexer - MUX) (

)

,n

.

, 2n 1

.

2n

.

4 4

(MUX 4X1)

,

0, 1, 2

S0

3

S1

: S1 0,

1,

2

S0,

3

, :

S0

S1

0,

1,

2

3

:

Y = I0 S'1 S'0 + I1 S'1 S0 + I2 S1 S'0 + I3 S1 S0

.

19

,

4 1

AND

,

OR

,

:

8 8 S1

(MUX 8X1)

S2

0, 1, 2, 3, 4, 5, 6

,

:

S0, S1 1,

2,

3,

4,

5,

6

S2,

:

, C+A

0,

7

,

A'

S0,

7

C: Y(A,B,C) = A' B' C' +

C

:

.

20

: n=3.

8 , 5,

6

,

(MUX 8X1)

.

C

.

0, 1, 2, 3, 4,

:

7

"0"

"1",

. .

74HC/HCT153 74HC/HCT153 (S0, S1).

(1 , 2 ).

(1 , 2 )

active LOW LOW

HIGH.

74HC/HCT253

.

21

74HC/HCT253 (S0, S1).

(1O , 2O )

HIGH

(OFF-state).

74HC/HCT151 74HC/HCT151

(S0, S1, S2)

( )

( ).

( ).

( )

active LOW

LOW

HIGH.

74HC/HCT251 74HC/HCT251 ( )

( ).

HIGH

.

(S0, S1, S2) (O ) (OFF-state).

22

(74HC/HCT147, 74HC/HCT148) (Encoder) (n 2m).

n

m (nxm)

n

n

m

,

.

m-bits

.

8 3 8 3

(n=8)

(m=3)

,

8 3 :

.

23

8 3

:

D3

=

I4

+I5

+I6

+I7

D2

=

I2

+I3

+I6

+I7

D1 = I1 +I3 +I5 +I7 8 3

OR

.

BCD 74HC/HCT147 74HC/HCT147

BCD. .

"

",

.

74HC/HCT147

(active LOW).

1-9

BCD

.

(

)

.

24

,

BCD

(

.

"1"),

) (

"1".

0.

74HC/HCT147

:

8x3 74HC/HCT148 74HC/HCT148

8x3. .

"

",

. (active LOW)

(octal 4-2-1)

.

.

25

74HC/HCT148

:

(CD4555/6B, 74HC/HCT139-138-238-42-154) n

(Demultiplexer - DEMUX) 1X2 2n

, n

.

n

2

,

n

.

.

1 4 1 4

,

1

bits I1

.

D0, D1, D2

0 0

D3.

.

26

1 4

:

1 4

D0, D1, D2

D3 0

1:

D0

=

E

I1'

I0'

D1

=

E

I1'

I0

D2

=

E

I1 I0'

D3 = E I1 I0 , AND

.

1 4 ,

:

27

(Decoder) (m 2n).

n

m (nXm)

n

n

2n

m "0"

"1",

. . (m=2n), (m<2n),

3 8, 4 10.

3 8 3 8

.

C, B D2, D3, D4, D5, D6

3-bits ( D7.

)

D0, D1, "1" (

)

.

3 8

"0".

28

3 8

:

3 8

:

D0

=

C'

B'

A'

D1

=

C'

B'

A

D2

=

C'

A'

D3

=

C'

A

D4

=

C

B'

A'

D5

=

C

B'

A

D6

=

C

B

A'

D7 = C B A 3 8

(3) (8)

.

AND n

,

nX2n

AND

(3)

, n

2n

.

.

29

1x4 CD4555B, CD4556B CD4555B

CD4556B

1x4.

, HIGH

(enable input) E .

CD4556B

CD4555B

LOW.

HIGH LOW

CD4556B

2-to-4 74HC/HCT139

line 74HC/HCT139

CD4555B HIGH.

2-to-4 line

. nA0

(active LOW),

nA1 nE

active

LOW. nE nA1 .

HIGH

HIGH

nA0

nE

1x4

.

.

30

2-to-8 line

74HC/HCT138 74HC/HCT138

A0, A1, A2

(enableed)

(

),

(antive LOW).

To "138"

(enable inputs): E1

active LOW 2

active HIGH.

LOW

E3

"138"

HIGH.

actine LOW LOW

2-to-8 line

HIGH.

74HC/HCT238

74HC/HCT238

74HC/HCT138 (active HIGH).

To "238"

(enable inputs): E1

.

active LOW 2

LOW

active HIGH. E3

HIGH.

31

BCD

(1-of-10)

74HC/HCT42

74HC/HCT42

(active HIGH)

(LOW)

active LOW. "42"

BCD

"9"

HIGH.

4-to-16-Line 74HC/HCT154 74HC/HCT154

4-to-16-line

(active LOW)

(enable inputs) 1 HIGH

0

2.

HIGH

3.

0

3

LOW.

.

32

BCD

(74LS47,

74LS48, CD4511) 7 (dispays)

(7)

(segments)

0-9. .

(LEDs) .

,

.

(LCDs). .

LCDs

.

BCD BCD

7

7

(BCD to 7 Segments Decoder)

(display), BCD 74(LS)48

.

7

TTL .

74(LS)47 CMOS

CD4511

.

.

33

(74LS47)

7448 (74LS48)

BCD

7447

TTL 7447A (74LS47) ,

TTL

BCD

7448 (74LS48)

,

. :

TTL 7447A (74LS47) (

BI/RBO

RBI

):

BI/RBO

RBI

):

TTL 7448 (74LS48) (

.

34

BCD D

(MSB),

(LSB)

BCD

.

LT

LOW,

BI/RBO

a - g.

.

BI

7447

D(6), C(2), B(1), A(7)

HIGH

(

LOW

LOW),

7448

,

LOW).

BI/RBO

OFF (

(

RBO

LOW)

RBI,

LOW.

LED ,

RBI.

"

" (blanking)

. ,

(

,

)

.

7447 ( 7448)

.

(ripple) ,

RBI

. , RBI .

(IC5).

RBO RBI LOW,

RBO

IC5

RBI LOW

BCD

RBO ,

IC5

LOW (

0), RBI

RBI LOW,

LOW ,

.

LOW,

0000

IC4

IC6

RBI BCD

0011.

RBO

.

IC4.

HIGH

IC3.

BCD

IC1 RBI

.

0000

. (

LOW).

35

-

BCD

CD4511

CMOS CD4511

BCD

,

. :

o

BCD

D (LSB)

D(6), C(2), B(1), A(7)

(MSB), BCD

.

LT

LOW,

,

.

LOW

LT HIGH

( LE

).

LOW, .

BCD LE

HIGH BCD

LE

LOW

HIGH.

CD4511 .

.

36

D Flip - Flops (4013, 74HC/HCT74) .

. : ---

(synchronous sequential circuits)

---

(asynchronous sequential circuits)

'

(latches). flip-flops. To flip-flop

(

1 bit

).

. (flip-flops)

SR

.

NOR

(latch)

NOR,

:

Q.

,

: (set)

Q=1

Q'=0

(reset)

(clear)

Q=0

Q'=1

NOR 1. S=0

R=0

.

,

, 2. S=0

R=1

.

.

S=0 Q=0 (

)

R=0.

Q=0

37

3. S=1

R=0

4. S=1

.

Q=1 (

R=1

)

Q=1

.

Q=0

Q'=0.

. (

Q=0

Q'=0)

S=1

R=1

.

.

NOR,

SR

.

AND,

,

SR,

:

CP S

0,

S1

R1

,

R.

CP=0.

1

CP,

S1

R1

S

R

. .

SR D.

RS S

.

R

D

S

SR.

38

Q=1.

D=0, D

0,

,

D=1

S=0

R=1,

S=1

R=0, Q=0.

Q

D CP

CP=1.

CP

1.

Flip - Flops , Q

D

CP=0,

D

CP=1.

D

.

D

,

(level sensitivity)

, . ,

"0"

,

"1"

: "1" "0"

.

(edge-triggering).

Flip-

Flops.

.

39

,

D Flip-Flop master-slave.

D. Clock=1.

master ("

,

slave ("

"1",

")

Clock=0.

master

D

.

"0", D.

,

slave

master

slave

.

")

Qm (

Qm

Clock=0,

master) slave .

D Flip - Flops D Flip-Flop

,

Q,

D

,

.

D Flip-Flop

Q(n),

,

Q(n+1) D Flip-Flop

.

Flip-Flop ,

Flip-Flop .

D Flip-Flop

D

D flip-flop flip-flops

.

:

, CP

.

40

D flip-flops RESET)

,

(SET

,

flip-flops

. flip-flop flip-flops

(

)

.

(PRESET)

flip-flop

(CLEAR)

(Q=1).

Flip-Flop

(Q=0).

D Flip - Flop

CD4013

CD4013

CMOS data

Q

flip-flop set

reset,

:

CLOCK.

Q CLOCK

RESET, .

.

clock,

Q.

D

SET

Flip - flop.

flip-flop

schmitt trigger. set

flip-flop

HIGH

reset :

41

D Flip - Flop

74HC/HCT74

74HC/HCT74 data (D), clock (CP)

flip-flop, set (SD)

reset (RD)

Q.

Q

:

set data (D)

reset

clock (CP).

HIGH

LOW D

.

Q

LOW

Schmitt-trigger .

flip-flop

:

.

42

JK

T Flip - flops (4027, 74HC/HCT73, 74HC/HCT112)

J - K Flip - flops S-R Flip-Flop (S=1 J (set) Q=0

Q=1

(reset)

J=1

=1,

Flip-Flop

(

J-K Flip-Flop

S-R Flip-Flop.

:

1.

J=0

=0,

2.

J=0

=1,

Q=0.

3.

J=1

=0,

Q=1.

J=1

J-K Flip-Flop. '

).

J-K Flip-Flop

4.

R=1)

.

=1,

Flip-Flop

,

.

J-K Flip-Flop

.

J-K Flip-Flop

:

T Flip - flops J-K Flip-Flop T Flip-Flop

,

J-K Flip-Flop, J-K Flip-Flop

J

Flip-Flop.

K,

:

.

43

Flip-Flop 1.

=0,

2.

=1,

: .

Flip-Flop

,

.

T Flip-Flop

(Toggle) Flip-Flop

.

Flip-Flop

J, K, D

.

:

flip-flops

,

flip-flops

CP

.

flip-flops ,

flip-flops

.

flip-flop flip-flops .

(PRESET) (CLEAR)

.

(

)

: flip-flop Flip-Flop

(Q=1).

(Q=0).

44

JK flip - flop CD4027 CD4027 .

J-K master-slave flip-flop

flip-flop

SET

J, K,

clock

RESET. HIGH.

preset

clear

SET

RESET

HIGH

.

flip-flop HIGH.

:

flip-flop

:

JK flip - flop 74HC/HCT73 74HC/HCT73 .

Q

J,

.

clock (CP),

reset (R)

Q. reset (R)

flip-flop

JK flip -flop

Clear

LOW. Q

LOW

J, K

clock

LOW.

45

schmitt-trigger

clock

. :

flip-flop

:

JK flip - flop 74HC/HCT112 74HC/HCT112

J-K flip-flops

.

(PRESET) S

LOW (CLEAR)

R

S

R

,

flip-flop J, K, clock.

HIGH,

J

,

K

JK flip-flop. :

.

46

flip-flop

(clocks) – binary counters),

:

.

(

(

(BCD) counters).

– Binary Coded Decimal

,

(input),

. . (counters)

: ) (synchronous counters).

(asynchronous counters) flip-flops

.

.

47

,

flip-flops,

(

), .

flip-flops

,

flip-flops,

,

flip-flop,

, flip-flops

, flop

(ripple)

flip-

.

(asynchronous) flip-flops.

(binary)

(counter)

4 J-K flip-flops .

flip-flop,

flip-flops

flip-flop. flip-flop

flip-flop.

flip-flops (ripple).

J-K flip-flops

«toggle»

J=K=1

), .

4-bits

.

Q4Q3Q2Q1 (

Q4

MSB

.

Q4, Q3, Q2, Q1 Q1

flip-flops

LSB)

48

: Q1

(

J=K=1) , .

.

flip-flop 1

«0»

,

«1»,

flip-flops

,

: Q4Q3Q2Q1=0001 ,

flip-flop 1

«0» (

.

Q1

«1»

)

flip-flop 2,

flip-flop 2

«0»

«1».

flip-flops .

,

,

: Q4Q3Q2Q1=0010 ,

flip-flop 1

. flip-flop 2)

Q1

«0»

flip-flop 2

.

«1»

flip-flops .

,

(clock),

:

Q4Q3Q2Q1=0011. flip-flops «1».

,

flip-flops

«0»

.

.

49

’

,

, .

BCD BCD

, 0.

BCD

0

9,

(

bits

) 10

4 flip-flops,

.

,

.

Q4Q3Q2Q1

flip-flops

.

bits BCD .

9 BCD

flip-flops

.

BCD bits.

.

BCD

.

50

J-K flip-flops

J=K=1.

BCD bits,

NAND.

flip-flops

,

Q4Q3Q2Q1=1001. ( flip-flops

1001,

NAND,

1010

). ,

Q4Q3Q2Q1=1010,

«0» (

Q4 flip-flops,

NAND

Q2).

NAND

flip-flops

«0»

Q4Q3Q2Q1=1001,

Q4Q3Q2Q1=0000.

NAND

flip-flops

«1»,

.

, .

CP

flip-flops

.

, flip-flops

,

.

(up-counters)

,

.

J-K flip-flops.

J-K flip-flop

(

)

J=K= «1». flip-flops

, J

flip-flops

. .

flip-flops

bits. (

) «1» bits

.

bit

.

flip-flop FF1 ,

J-K

flip-flops

.

J flip-flop

K

(

)

«1».

51

Q4Q3Q2Q1=0011 Q4Q3Q2Q1=0100.

Q1

,

Q3Q2Q1=011 (

Q2

Q1=1,

Q3

Q2Q1=11

«1»).

bits. .

J

Q4

FF1

flip-flops

«1»,

,

,

. flip-flops

,

flip-flops J

«1».

AND

flip-flops

flip-flop

AND.

AND .

bits.

(down-counter) .

.

J-K flip-flops

.

52

flip-flops

. (

Q4Q3Q2Q1=1111).

, .

modulo N modulo ( ( 16

.

(

).

0

modulo N

-1).

0

15)

bits â&#x20AC;&#x2122;

modulo

53

16. O BCD

10

(

0

9)

’

modulo 10. .

modulo. modulo 16.

0000

.

1100.

; 12 =16

+12

)

(1100=1210).

44 (

12

= 2 16 + 12) (

flip-flops

0

28 (

.

15)

modulo N

.

2 .

,

flip-flops

modulo 8, modulo 7, modulo6

modulo 5.

modulo 4

flip-flops.

modulo modulo 5 modulo 8,

,

modulo 8

.

flip-flops

(clear)

«0».

0

modulo

8

5

flip-flops

NAND Q3Q2Q1=101 (

Q3 Q2 Q1.

5

),

Q3Q2Q1=111

NAND .

5

101 ).

7.

0

«0» ,

000 ( 4

modulo 5. modulo.

.

54

bits.

bits,

.

flip-flops , 2.

,

flip-flop

, ,

.

f,

flip-flop

flip-flop f/2,

flip-flop

.

f/4 ,

f/8

.

56600 z, 28800Hz, 14400Hz,

7200Hz. .

4

,

bits ,

. 113200 z,

.

flip-flop 113200 z/2= 28800Hz,

14400Hz

flip-flop

bits

.

113200Hz/2= 56600Hz, flip-flop

113200Hz/8=

113200Hz/16= 7200Hz. (

).

55

CD4040 CMOS CD4040 CD4060

CD4060

12-stage

14-stage

CMOS

,

Q1, Q2, Q3

Q11.

RESET (CT=0),

(reset) clock. H

triger.

clock

"1"

CD4040

schmitt

8MHz (VDD=10V).

1.0V

15V. CD4040

:

, CD4040,

Q:

CD4060

.

:

56

, CD4060,

Q:

CD4060, -

.

CD4017B CD4017B

CMOS

10

.

.

57

CLOCK .

,

"1"

.

10

CLOCK.

RESET

' "1",

,

CLOCK. CD4017B,

:

CLOCK , :

CD4017B RESET,

, RESET "0".

.

58