SOLUTION MANUAL FOR Analog Fundamentals A Systems Approach 1st Edition. Thomas L. Floyd David M. Buc

PART ONE Solutions to End-of-Chapter Problems

Chapter 1 Section 1-1 1 1 1. G = R = 22kQ =45.5Il S

2. The resistance of a diode decreases as the voltage increases.

3. The ac resistance at V = 0.7 V and] = 5.0 rnA is approximately: (0.72 V - 0.675 V) = 333 Q (5.5 rnA - 4.0 rnA) 4. An W curve with decreasing ac resistance as voltage increases is shown in Figure 1-1.

/

/

/ I»(mA)

VM FIGURE 1-1 Section 1-2

5. For the sine wave given by the equation vet) = 100 sin(200 t +0.52): (a) V = 100 V V:Vg = (0.636)(100 V) = 63.6 V (0 = 200 rad/s (b) v(2.0 ms) = 100 sin(200 rad/s (200 ms) +0.52 rad) = 100 sin (40.52) = 31.5 V 6. For the voltage v(t) = 100 sin (200 t + 0.52):

f = 200 rad!s = 31.8 Hz 21t rad! cycle 1 1 T = f = 31.8 Hz = 31.4 rns

1 1 7. f = T = 27 Il s = 37.0 Hz

1

Vrms 3.5 V 8. Vpp = 0.354 = 0.354 = 9.90 V

Vrms

0.707 Vp 9. Vavg = 0.636 Vp = 1.11 10. The 5th hannonic is (5)(500Hz) = 2.5 kHz 11. Odd harmonics

Section 1-3 12. For the circuit shown in Figure 1-25 (text): Vrn= Vol = (12 V) ( 5.6 8.9 kQ) kQ = 7.55 V

Rm = 3.58 kCl

Vm=7.S5V~

Rrn= 1.5 kQ + (5.6 kQ 113.3 kQ) = 3.58 kQ The equivalent circuit is shown in Figure 1-2.

T FIGURE 1-2

13. For the circuit in Figure 1-25 (text), Rrn = 3.58 kQ and Vrn = 7.55 V (see problem 12).

For RL = 1.0 kQ: VL = (7.55 V)( 08kk~) = 1.65 V

15

For RL = 2.7 kQ:

V L = (7.55 V)(i.i8 kk~) = 3.25 V For RL = 1.0 kQ: VL = (7.55 V)(

lt8~~)

= 3.79 V

14. From problem 12, Rrn = 3.58 kQ and Vrn = 7.55 V RN =Rrn = 3.58 kQ Vrn 7.55 V IN= Rrn = 3.58 kQ = 2.11 rnA 15. The load line (for Figure 1-26 of the text) crosses the y-axis at: Vrn 15 V I SAT = R rn = 200 kQ = 75 JlA and crosses the x-axis at: Vco = Vrn= 15 V The load line drawn between these two points as shown. The IV curve for a 150 kQ resistor is shown in Figure 1-3.

2

5

10

v (V)

15

FIGURE 1·3 R.=100kn

16. The Thevenin equivalent circuit is shown in Figure 1-4.

v"r-

10mv~

FIGURE 1·4 17. For the transducer of problem 16, VOk = V,h = 10 m V and You, = 1/2 VOL when RL is 100 kn implies thatRs =R,h = 100 ku. Then: Rn = 100 kn Vth 10 mV 1 n = - = 100 kn = 100 nA Rth

The Norton equivalent circuit is as shown in Figure 1-5.

FIGURE 1·5 Section 1-4 18. For the amplifier having the transfer curve of Figure 1-17(text), the gain in the linear region is:

A = You, = 60 V = 10 000 v V. 6 mV ' In

The largest non-saturating input voltage is approximately 7.2 m V, giving Vour = 72 V

19. Av = 50,000 and Yin = 80V; Vout = AvYin = (50,000)(80 J.lV) = 4.0 V

3

Section 1-5 26. A basic test plan for the system in Figure 1-27 (text) is: 1. Check for a signal at the input of the amplifier. IT present, go to step 2; if not go to step 3.

2. Check for a signal at the output of the amplifier. IT present, problem is with the speakers; if not, go to step 4.

3. Check for a signal at the output of the microphones. IT present, switch is bad; if not, go to step 5.

4. Check for power to the amplifier. If present amplifier is bad; if not problem is with the power supply.

5 . Check for power to the microphones. IT present microphones are bad; if not batteries need to be replaced.

27. For the system of problem 26, isolating the problem of no sound from channel 2 could be done as follows: 1. The supply is common to both channels so it is not the problem. Start by reversing the channels at the input of the amplifier. IT the Channel-2 is still bad, the problem is most likely the amplifier or the Ch-2 speaker. Speakers can be tested by reversing them.

2. IT the problem changes channels when the first test is done, the problem is before the amplifier inputs and could be the A2 microphone or a problem in wiring including the battery lead at the microphone. Test by changing SI to the B microphones. If this corrects the problem, check the A2 microphone; otherwise look for continuity to the switch and check the switch itself.

28. When a square wave is applied to an oscilloscope, selective attenuation of high or low frequencies can be determined from the observed waveshape. High frequency attenuation produces a slower rise time; low frequency attenuation causes "sagging".

29. Use a static safe wrist strap (and static free work station, if possible). A static free work station includes grounded instruments, antistatic mat, and not wearing static generating clothes.

30. Two advantages of digital over analog scopes are: 1. Digital scopes can store waveforms of known good circuits for comparison of a circuit under test.

2. Displays can be pre- and post-triggered to catch intermittent signals and events leading up to or following a trigger event.

5

Chapter 2 Section 2-5 1. See Figure 2-1.

4.3 V························

OV~~----------~---------------

Voltage waveform

43 mA······················

o Current waveform

FIGURE 2-1 2. primary side: V pk = 115 12 V = 162.6 V 162.6 V secondary side: V pk = 2 = 81.3 V Peak voltage delivered to the load = V L(Pk) = 81.3V - 0.7 V = 80.6 V V2 (806 V)2 Peak power delivered to the load = R ~ = 220 Q = 29.5 W

3. (a) Full-wave rectifier (b) 28.3 V(total) (c) 14.1 V (reference is center tap) (d) See Figure 2-2 (offset approximation) (e) 13.4 rnA (offset approximation) (1) 28.3 V (ideal approximation) 13.4 V·····················_·······_-

-

~

\

OV __L -_ _ _ _ _ _ _ _ _ _ _ _ _ _

/

~L_

______________

Voltage waveform

FIGURE 2-2 4. Reverse diodes D\ and D2 as shown in Figure 2-3:

6

~_

FIGURE 2-3

5. Vp = 50 V/0.637 = 78.5 V. PIV = 78.5 V

Section 2-6 6. Peak 7. 120 pV 8. Load regulation = (VO~~

Va) 100% =e5.5i4~ ~.9 V)100% == 4%

9. 11.94 V 10. V OUT = 5.0 V = 1.25

R 2 = 5.0 V( ii~ ~

11. V OUT = 1.25 V

V(R 1;lR2) = 1.25 V (24~4~;R

2)

)-240 =720 Q

Q

(R 1;lR2) = 1.25 V (240 ~4~ ~OO Q) = 9.06 V

Section 2-7 12. See waveforms in Figure 2-4. +30 V

+12.7 Y ........... r---......

7\

+11.3 Y

OY~/_---r---~

'-------

OY - - - - - - - - - -

- 30 Y ...............-._...................._.__........................... . (b)

(a) +30Y···_·········_········

oY - 1 - . - - - - - - - - \ - - - - - - - - , . . -

OY----------------11.3 Y - - - - - - - - - ;

-12.7V ........................................................ \ ___- - - J

-30Y················h ..................... (c)

(d)

FIGURE 2-4 13. See Figure 2-5

7

7.3V --------------- ---

-7.3V------.::........<:---

OV -------~~--(b)

(a)

FIGURE 2-5

Section 2-8 14. VIN(MIN) = (2.0 mA)(560 Q) + 5.0 V = 6.12 V VIN(MAX) = (30 mA)(560 Q) + 5.0 V = 21.8 V 15. See Figure 2-6.

zz=snl f

'Vz= 7.5 V T----.:!L-

FIGURE 2-6 16. Z z = ~ ~z = 30 n UlZ

M z = 40 rnA - 30 rnA = 10 rnA

AVz =Zz M z = (30 Q)(lOmA) = 0.3 V R = VIN - V z = 18.0 V - 12.3 V = 143 Q I 40 rnA 17. 10adregulatiOn=(V NL - VFL)100%= (8.0V-7.8 V)100%=2.6% V FL 7.8 V 18. C(VR=5V) =20pF

C(VR=20V) =lOpF

AC =lOpF

19.2.0 V (Note: since the plot is logarithmic, 25 pF is 70% of the linear distance between 20 pF and 30 pF).

20. f =

1

then:

r:-;:;

21t¥ LC C= 1

C D -

L(21ifY

2

L(27ifr)2 =

_lr C -1C -"2 Dl-~ D2

2 2 =25.3 pF 2 rnH(21t1.0 MHz)

21. Approximately +2.0 V to produce a capacitance of 25.3 pF (see problem 20).

22. Reading will increase

8

23. Dark current

Section 2-9 24. PIV = VRRM = 50 V 25. PIV = VRRM = 400 V 26. The minimum surge resistor is determined assuming worst conditions - maximum current and voltage at the same time: RMJN= VOUT = 50 V =63 IFSM

800 A

mn

Section 2-10 27. DMMI is correct but DMM2 is reading the rectified average voltage rather than the peak voltage that it would show if the capacitor was in the circuit. DMM3, indicating no voltage, implies an open circuit between the bridge and the output. The most likely cause is an open path along the output line between the bridge and the filter capacitor.

28. (a) Functioning properly (b) Open diode (c) Functioning properly (d) Open diode 29. (a) Readings are correct (b) Open zener diode (c) Open switch or fuse blown (d) Open capacitor (e) Open transfonner winding (less likely: more than one diode open) 30. (a) Either an open trace before the fuse or no ac input. Check for ac across input tenninals; if present, check continuity of upper trace. (b) Either a blown fuse or open transformer. Check for ac voltage directly at transformer; if present transformer is open, otherwise fuse is open. (c) Transformer may have shorted windings or has excessive output current. Check for signs of high current; if none, replace transformer. (d) C 1 open. Check path and solder connections; if okay, replace C 1• (e) C 1 leaky or incorrect value. Replace. (t) A diode is open. Isolate with an ohmmeter and replace. (g) Bad IC. Replace.

9

Chapter 3 Section 3·1 1. le=/E-/B =5.34 mA-47.5 1lA=5.29 rnA 2. 13oc= Ie = 25 rnA = 125 IB 200 IlA

3. IB = 0.02 IE implies I e =0.98 IE Ie = 0.98 (30 rnA) = 29.4 rnA 4. VE =2.0 V -0.7 V = 1.3 V

I =1 = 1.3 V = 1.3 rnA e E 1.0 H2 2.0 V -0.7 V Q 0.276 rnA 4.7 k Ie = P/ B = (75)(0.276 rnA) = 20.7 rnA Ve = 24.0 V - (20.7 mA)(430 Q) = 15.1 V

5. IB

12 10

The load line is shown in Figure 3-1.

Ic(mA)

8 6

4 2

o

I,\-

'" "-

o 2

~

~~oadline

4

8 10 12 VeE (V)

6

I'"

FIGURE 3·1 7. 1B =

1.0V-0.7V 136 22 kQ = . IlA

Ie = PoclB = (250)(13.6 1lA) = 3.41 rnA Ve = 10 V - (3.41 mA)(1.0 kQ) = 6.59 V

Section 3·2 10 V-0.7 V Q = 13.7 IlA 650k 1e = Pocl B = (100)( 13.7 1lA) = 1.37 rnA VeE = V c = 10 V - (1.37 mA)( 2. 7 kQ) = 6.31 V

8. IB =

11

26. The circuit is shown in Figure 3-2.

FIGURE 3-2 27. V =(

R2 )V =( 22kn )18V=13.1 V Rl +R2 cc 8.22kn+22kn VB =V B - 0.7 V= 13.1 V - 0.7 V = 12.4 V B

=1 = VB = 12.4 V = 18.3 rnA B RB 680 n V CEQ = V cc - VB = 18 V - 12.4 V =5.59 V VCe(CUlo/f) = V CEQ +Iccftac = 5.59 V + (18.3 rnA) (680 Qlll.O kn) = 13.0 V

I

CQ

V CEQ 5.59 V Ic(pat) =1 CQ + Rae = 18.3 rnA + 680 0.111.0 kn =32.1 rnA 28. The input signal is connected through a coupling capacitor to the base; the output signal is connected through a coupling capacitor and is taken from the emitter. See Figure 3-3.

Vee -lSV

FIGURE 3-3 Section 3-6 29. Low input resistance

15

2)

(

R 5.6 kn ) 30. V B = ( RI+R2 Vee= lOkn+5.6kn 15V=5.38V

V E= VB - 0.7 V = 5.38 V - 0.7 V = 4.68 V VE = 4.68V =2.55rnA REI +Rm 1.84 kn Ve = Vee-IcRc = 15 V - (2.55 rnA)(2.7 kn) = 8.11 V

Ie==IE=

V CE = 8.11 V - 4.68 V = 3.43 V r:=25mV = 25rnV =9.80n IE 2.55 rnA

A -

Rc _ (2.7 kn)II(2.0 kn) _ 1.15 kn -257 v - (r: +REJII(R m) - (9.80 n+36 n)II(1.8 kn) - 44.7 n .

Note thatR m can be ignored in the gain calculation.

31. V E= 4.68 V, IE = 2.55 rnA and

r: = 9.80 n (see problem 30)

Rin(IOI) = (REI + r:JIIRm =(36 n +9.80 n)II(1.8 kn) =44.7 n

32. REI is a swamping resistor, used to reduce circuit nonlinearities due to re'o

Section 3-7 33. Assuming a 1.9 V drop across the LED and 0.1 V drop across a saturated transistor: 12V-0.IV n = 1.19 rnA R2 10k V ee - V LED- V sal (Q2) 12 V - (1.9 V + 0.1 V) I ~aI)(Q2) = Rc = 1.0 kn == 10 rnA I~al)(QI)=

Vee-Vsal(QI)

34. I ~al)(min) = I

=

Vee-VSal 15V-0.IV R = 1.2 kn = 12.4 rnA

- Ief,ral) (pUn) _ 12.4 rnA -124 IIA

B(pUn) -

RB(paax) =

~

-

100

-

I-'fl

5.0 V - V BE 5.0 V - 0.7 V 4 n. = = 3 .7 ku I B(pUn) 124 !.lA

Section 3-8 ~eiSC

35. See Figure 3-4

B

FIGURE 3-4

16

EBC ~

Chapter 4: Section 4-1 1. JFETs 2. MOSFET

Section 4-2 3. (a) Depletion-region widens (creating a narrower channel) (b) Increase (c) Less 4. To reverse bias the gate source junction.

5. +5.0 V 6. (a) +2 V (b) -6 V 7. (a) 10 rnA (/os~) 14 VI (b)RIN=1 1=4GQ 1 nA (c) RIN drops

8. zero 9. (a) Approximately +4 V (absolute value of VGS(off)) (b) Approximately 2.5 rnA (I SS) (c) V nn = Vos +/rfln =4 V +(2.5 mA)(4.7 kQ) = 15.8 V 10. (a) 6.4 rnA (b) -5 V (c) From Figure 4-60 (text), the slope ofthe curve atl n= 2.1 rnA is approximately: 1m -/Dl 2.5 rnA - 1.6 rnA g = == == 1100 !lS m V GS2 - V GSI (-1.8 V) - (- 2.4 V) These points are shown on the plot in Figure 4-1. Student answers will vary.

18

Chapter 5: Section 5-1 1. For stage 1: A y1 ¢'n.) =- g,fl D = - (2700 J.,lS)(1.5 Hl) =-4.05

R in((21) = 1.0 Mo. R 0"/((21) = 1.5 ko.

For stage 2:

V =( R + R )V cc =( 33 ko.10ko. )15V=3.49V + 10 ko.

R2

B

1

2

VE =V B -V BE =3.49V-0.7V =2.79 V VE 2.79 V I E= REI +RE2 = 1000.+ 1.0 ko. =2.53 rnA r:=25rnV = 25rnV =9.860.

IE 2.53 rnA A Y2(NL)=-

Rc =_ 2.7 ko. =-24.6 RE1+re 1000.+9.860.

I

R in ((22)=R 1 IIR211

{~(REI +r:)} =33 ko. 1110 ko. 1\ {150(100 0. +9.86 o.)}

=5.24ko.

R 0"/((22) = 2.7 ko.

The overall loaded gain is: Rin((22)

~

RL ) -R---:;;"'-R0"/((21) + in((22) 0"/((22) + L 5.24 k o . ) (-24.6) ( 2.7 ko. ) = 38.4 A = (- 4.05) ( 1.5 ko. + 5.24 ko.

2.7 ko. + 2.7 ko.

Ay =A Y1 (NL{ R

R

(

v2(NL)

y

2. See Figure 5-1 Amplifier Stage 1

Stage 2

Rout =

1.5 kn

Vin

2.7kn

=

Hn(tot)=

1.0Ma

5.26 k.Q

RiII(to\)

Rout =

FIGURE 5-1

23

Vout

RL = 2.7kn

~

Rin(2)

3. A v = A vl(NL

R oUI(I)

+ R in(2)

~ v2(NL)

24kQ ) (-15) = 812 24kQ+27 kQ

A = (- 115) (

.=20 log 812 =58.2 dB v

Av

~

R in(2)

4. Av =AvI(NL

R ou/(I)

~ v2(NL) --=--R L

(

+ R in(2)

R ou/(2)

)

+R L

) (-15) (1.0 kQ ) = 325 24 kQ 24 kQ +27 kQ 1.5 + 1.0 kQ

A = (- 115) ( v

5. (a) See Figure 5-2

~

Rin(2)

(b) A v =AvI(NL

A = (80)( v

R ou/(I)

30 kQ )(80) = 6000 2kQ+30kQ

~

R in(2)

(c) Av =AvI(NL A = (80)( v

+ R in(2)

~ v2(NL)

R oUI(I)

+ R in(2)

~ v2(NL ---=-L ) {

R

R oUI(2)

+R L

30 Hl )(80)( 3 kQ ) = 3600 2 kQ + 30 kQ 2 kQ + 3 kQ Amplifier

Stage 1

Stage 2

Rout = 2.0 k.Q

V;n

Rout = 2.0 k.Q

R;n(tot)=

R;n(tot) =

30 k.Q

30 k.Q

Vout

FIGURE 5-2 6. For the amplifier of problem 5(b), the decibel gain is: A.' = 20 log 6000 = 75.6 dB 7. Since it increases the input resistance of stage 2, gain will be larger. The input resistance of Q3 increases from 17.3 ill to 93.3 ill. As a result of the reduced loading on the first stage, the overall gain increases from 40 to -42.3. (See Example 5-1 in the text).

24

RL 100Q 25 (b)A y = RE\+r'e =8.2Q+0.37Q= 11.7

R in = ~ ac(R El + r'e) II Rill R 2 = 100 (8.2 Q + 0.37 Q) II 330 Q II 1.0 kQ = 192 Q A = A 2R in = 11 72192 Q = 263 P y R L • 100 Q

(The computed voltage and power gains are slightly higher if re' is ignored).

26. (a) If RL is removed, there is no collector current, hence the power dissipated in the transistor is zero. (b) Power is dissipated only in the bias Rm = 248 {1 ......, resistors plus a small amount in REI and RE2 • Because the load resistor Vrn = 3.72 vE,-----~-IIJII"'a!----.~ has been removed, the base voltage -=RSltooiEl = 44.2 n is altered. The base voltage can be _ found from the Thevenin equivalent FIGURE 5-6 for the bias circuit in Figure 5-6.

Applying the voltage divider rule, and including the base-emitter diode drop of 0.7 V results in a base voltage of 1.2 V. The power supply current is then computed as: Vcc-1.2 V 15 V-1.2 V Icc = = Q = 13.8 rnA R1 1.0 k Power from the supply is then computed as: PT=lccV cc =(13.8 mA)(15 V) =207 mW (c) Ay = 11.8 (see problem 25(b)). Vin = 500 mVpp = 177 mV nns' V oul =AYin = (11.8)(177 mV) = 2.09 V V 2 2 P =~ = 2.09 V =43.6 mW oul R 100 Q L

27. The changes are shown in Figure 5-7. The advantage of this arrangement is that the load resistor is referenced to ground.

+VEB

+15V

FIGURE 5-7

29

1

1

17. (a) AcINI) = B = 4.7 kD/51.7 kO = 11.0

1

1 (b) AcINI) = B = 10 kO/1.01 MO = 101 1

1

(c) AcINI) = B = 4.7 kQ/224.7 kO =47.8 1

(d) AcINI) = B =

1

1kQ/23kO

= 23.0

Rf 18. AcK/V1) = 1 +R·I

Rf =R j {A clQVl)-l) = 1 kO(50-1)=49 kO Rf R. =Acm I

Rf=-Rj{Acq)) = -10 kO(- 300)=3 MO Rf =R j{A cK/VI)-1) = 12 kOO)=84 kO Rf=-Rj{Acq)) =- 2.2 kO( -75) = 165 kO

19. (a) Ac~F) = 1 (b) A 1'1\=_(Rf)=_(100kO)=_1 coy} Rj 100 kO

(c) Acl?.T1) ~.. = (

1 Rj

Rj+Rf

) =(

1 47 kO

) =22.3

47 kO+ 1 MO

(d) A 1'1\ =_ (Rf) =_ (330 kO) =_ 10 coy} Rj 33 kO

34

20. A - sign for the output indicates a 1800 phase shift, as indicated (a) Voul == Yin = 10 rn V, in phase (b)

Vout=AcF;n =i~:)V;n=- (1)(10

~; ))Vin=(( 4/kn ))10rnV=223rnv, inphase

(c) VOUI=((

Ri+Rt (d)

mV)=- 10 mY, 180· out of phase

1047 kn

Vout =i;,)v;" C:30: )10 mV =-100 mV, 180· out ofphase =-

Yin

21. (a) lin = -

Rin

=

1V

2.2kn

= 0.455 rnA

(b) It==lin =0.455 rnA

(c) Voul=-I't=- (0.455 rnA)(22kn)= -10 V

(d) Acm=-( -Rt ) =- (22 kn) =-10 Ri 2.2 kn

Section 6-6 2.7kQ 22. (a) B = 562.7 kQ = 0.00480

Z i~ = (1 + A OI)Z in = [ 1 + (175,000)(0.00480)]10 Mn = 8.4 Gn

ZOUI 75 n Z out(Nl) = 1 + A 0f3 = 1 + (175,000)(0.00480) = 89.2 rnn 1.5kQ (b)B = 48.5 kQ = 0.0309

Z i~ = (1 + A OI)Z in = [ 1 + (200,000)(0.0309)]1 Mil = 6.2 Gn

Zout 25 n Z out(Nl) = 1 + A 0f3 = 1 + (200,000)(0.0309) = 4.04 rnn (c) B =

1.~;6~n = 0.0530

Z i~ = (1 + A ol)Z in = [ 1 + (50,000)(0.0530)]2 Mil = 5.3 Gn 50 n Z out(Nl) = 1 + A 0f3 = 1 + (50,000)(0.0530) = 19 ron

ZOUI

35

r 1+eOOHzf

Aol(mid)

80,000

5. (a) Aoz=-r======= = 1+ ( - f

1 kHz

Ic(ol)

AoZ(mid)

80,000

=

1+ ( - f

1+ - 1 kHz

r 1+(lOkHZf 80,000

(c) Aoz=-r===== =

1+ ( - f

80,000

Aol(mid)

(d) Aoz=-r===== =

( )' I

Ic(ol)

=7960

1 kHz

I c(ol)

1+

=56,600

ekHzf

)'

Ic(ol) Aol(mid)

=79,600

1+e1MHZ)' kHz

=80.0

1 1 6. (a) f. = - - = = 1.59 kHz e 211RC 2n(1O kn)(O.OI ~

q, = tan

_1(/) - = tan -1( 2 kHz ) =- 51.5 Ie

0

1.59 kHz

1 1 (b) Ie = 211RC = 2n(1 kQ)(O.OI ~ = 15.9 kHz

q, = tan

-1(/) - =tan -1( 2 kHz ) =-7.16 Ie

0

15.9 kHz

1

1 (c) Ie = 211RC = 2n(100 kn)(O.OI ~ = 159 Hz

1(/) =tan -1( 2 kHZ) =- 85.5 Ie 159 Hz

q,=tan - -

0

7. The plot of phase angle verses frequency is shown in Figure 7-1. (a) q, =- tan

_1(/) - =- tan -1( 100 HZ) =- 0.67

(b) q,=-tan

-1(/) - =-tan -1( 400 HZ) =-2.69

(c) q, =- tan

-1(/) - =- tan -1( 850 HZ) =- 5.71

Ie

Ie

Ie

0

8.5 kHz

0

8.5 kHz

8.5 kHz

38

0

7. (d) tP =- tan -1(/) - =- tan _1(8.5 kHZ) =- 45.0

Ie

r.) tP=-tan ,e

0 10

0

8.5 kHz

-15

-1(/) - =-tan -1( 25 kHZ) =-71.2 1-30 Ie 8.5 kHz :£ 0

Frequency (Hz) 100 10k 10k

r'\

\

~ 45

(t) tP =- tan

_1(/) - =- tan -1( 85 kHZ) =- 84.3 J-60 Ie 8.5 kHz

lOOk

\,

0

'\

-75

~

-90

FIGURE 7-1 Section 7-2 8. (a) A ol(mi4) = 30 dB + 40 dB + 20 dB = 90 dB (b) tPl =- tan

-1(/) - =- tan -1( 10 kHZ) =- 86.6 Ie 600 Hz

tP2 =-tan

-1(/) - =-tan -1( 10 kHZ) =-11.3 Ie 50kHz

tP3 ==- tan

0

0

-1(/) 10 kHZ) Ie =- tan -1( 200 kHz = - 2.9

tP tot =- 86.6

0 -

0

11.30 - 2.9 0 - 1800 =_ 281 0

9. (a) 0 dB/decade (b) - 20 dB/decade (c) - 40 dB/decade (d) - 60 dB/decade

Section 7-3 10. BW cl =BW o{ 1 +BA Ol(mid») = 1500 H{ 1 + (0.015)(180,000)] = 4.05 MHz

(Rf)

11. (a) A cl(l) = - R i = - (68 2.2

kQ) kQ = - 30.9; A cl(l)(dB) = 20 log 1(30.9) 1= 29.8 dB

1 1 (b) A cl(JVl) = B = 15 kQ/235 kQ = 15.7; A cl(JVl)(dB) = 20 log (15.7) = 23.9 dB

(c) A cl(VF) = 1.0; A cl(VF)(dB) = 20 log (1.0) = 0 dB These are all closed-loop gains.

39

Section '·4 16. Acl=

lOMQ

= 3704 2.7 ill AetdB) =71.37 dB At 50 kHz, the midrange gain has dropped from 100 dB at a - 20 dB/decade rate to

Aol(mid)

j I )2

100

=

(50kHZ)2

=2399

1 + 1.2 kHz

1 'Vc(ol)

AotdB) = 20l0g (2399) = 67.6 dB SinceAcl>Aol (71.37 dB> 67.6 dB), the closed-loop gain intersects the open-loop gain on the- 20 dB/decade slope. Therefore, the amplifieris stable.

AI 17 • fa) ()pm =180 0- 'I'tot =180°-30°=150° \1

(b) (}pm = 180° - lPtot = 180° - 60° = 120° AI = 180° IIfC) ()pm = 180° - 'I'tot

120° =60°

(d) (}pm = 180° - lPtot = 180° - 180° = 0° IIfe)

()pm = 180°- 'I'tot AI = 180°- 210° =- 30°

18. lP1 =- tan

-1(/) - =- tan -1( 50 kHZ) =- 89.9°

lP2 =- tan

-1(/) - =- tan _1(50 kHZ) =- 63.4°

Ie

125 kHz

kHz lP3 =- tan -1(/) =_ tan -1( 50 kHZ) =_ 15.50 Ie

25

Ie

180 kHz

lPtot=- 89.9° - 63.4° - 15.5° =- 169°

19. (a) The closed-loop gain intersects the open-loop curve in the region of - 60 dB/decade and is therefore unstable. (b) The closed-loop gain intersects the open-loop curve in the region of - 20 dB/decade and is therefore stable. (c) The closed-loop gain intersects the open-loop curve in the region of - 45 dB/decade and is therefore marginally stable.

41

7. When the zener is forward biased: ) 18 kO V out = ( 18kO+47kO V out -0.7V

V out = (0.277)Vout - 0.7 V -0.7V Vout = 1-0.277 =-0.968 V When the zener is reverse biased:

Vout = ( 18 kO18+kO47 kO )Vout + 6.2 V V out = (0.277)Vout + 6.2 V +6.2V Vout = 1- 0.277 =+ 8.57 V lOkO ) 8. Vout = ( 10 kn +47 kO Vout ± (4.7 V + 0.7 V) ~

Vout = (0.175)Vout± 5.4 V

+ 1.ISV----

o~~----~----~-I.lSV ----:...-----------I

±5.4 V Vout = 1-0.175 =±6.55 V

I

I I

V UTP =(0.175)(+6.55 V)=+ 1.15 V

¥Out +6.SS;l_-t-'_ _ _+-___

VLTP = (0.175)( - 6.55 V) =-1.15 V -6.SSV

See Figure 8-2

FIGURE 8-2 Section 8-2 Rf lOkO 9. (a) V OUT=- -(1 V + 1.5 V) = (1 V + 1.5 V) =- 2.50 V Rj lOkO Rf 22kO (b) VOUT=- -(0.1 V + 1 V +0.5 V)=(1.6 V) =-3.52 V Rj 10 kO 10. VR1 = 1 V

IV IRI = 22 kO = 45.5 J.lA

VR2 = 1.8 V 1 = 1.8 V = 81.8 J.lA R2 22kO

If=IRl +1R2 =45.5 J.lA+81.8 J.lA= 127 J.lA

VOUT= -1.f..F -(127 J.lA)(22kn)=-2.80V

12. See Figure 8-3 44

l.25W

lOW

10kQ lOkQ I I I

I I I I I

I

.~ FIGURE 8-3

13.

+

Vour=-[(:~)Vl (::)V +(:~)V3 +(:~H =- [(:~ ~)2 V +G~~)3 V+G~ ~)3 V+USOO:)6 V] 2

=- (2 V +0.91 V +0.33 V +0.33 V) = - 3.57 V If = Vour = - 3.57 V =_ 3.57 rnA Rf lOkQ 14. Rf = 100 kQ Input resistors: Rl = 100 kQ, R2 =50 kQ,

R3 =25 kQ,

R4 = 12.5 ill, Rs = 6.25 kQ, R6 = 3.125 kQ,

Section 8-3 AVout Vin 5V 15 - - = - - = =-4464 V/s=-4.46rnV/~ . At (56 kQ)(0.02 ~

R,c

v.'V2tv

AV 16• I·In =C~ At 5.0V

= 0.001 J.lF-- = 1.0 rnA 5.0~

o

: I

Vout = (lrnA)( 10 kQ) = 10 V. The output is therefore ± 10 V

+10V :

See Figure 8-4.

~ut 0

-10 V

FIGURE 8-4

45

:10 jI8 I I I

I

17. See work in problem 16. 1= 1.0 rnA

jVpp )

18. Vout=±RL\ T/2

=±(lS kO)(O.OS

"d 2 v ) =±3 V r-a',O.S ms

+UV-'

,

See Figure 8-S.

v..

0 V -I-----+----t-

-3.0V

-

FIGURE 8-5 19. This is an idealized case. For the 10 ms interval when the switch is in position 2: AVout VIN SV --=--==-SOmV/ms M RC (10 kO)(10 !iF) AVout=(-SO mV/ms)(lO ms)=-SOO mV=-O.S V For the 10 ms interval when the switch is in position 1: AVout VIN - SV --=--==+SOmV/ms RC (10 kO)(lO !iF) M AVout=(+SO mV/ms)(lO ms)=+SOO mV=+O.S V See Figure 8-6.

o

ms 10 ms 20 ms 30 ms 40 ms O-~------~---~---,~

FIGURE 8-6 Section 8-4 20. (a) VIN = V z =4.7 V 10 kO)

(b) VIN =( 20kO 12 V=6 V

VIN

4.7 V

VIN Rj

6V =60mA 1000

I =-=--=4.7mA L Rj 1kO I =-= L

46

21. See Figure 8-7 +'V

FIGURE 8-7 Section 8-5

22. VB=(

R2 )Vout ±(Vz +0.7 V) Rl +R2

±(Vz+0.7 V) VB = ---:.---:------:~

1-(R;~R)

Normally, VB should be ±(4.3 V +0.7 V) =±10V 1-0.5 Since the negative portion of VB is only -1.4 V, zener D2 must be shorted: VB =

-(OV+0.7V) =-I.4V 1-0.5 23. When the input drops below +2.0 V, the output should go high but it doesn't. Either op-amp-2 or D2 are faulty, or there is a open connection from Vjn to Vout through the opamp-2 path, or the 2 V reference voltage is too low.

VB =

24. The circuit is an inverting summing amplifier with a gain of -1. The output should be as shown in Figure 8-8. V2 has no effect on the output; therefore R2 is open.

+4V r---

-IV-

-3 V L...--':""-.

-6V '-----'

FIGURE 8-8

47

12. Answers can vary. R=R 1 =R 2 =R s =R 6 andC=C 1 =C 2 =C 3 =C 4

/.= c

1

1

=-

2,JR2C2 21fRC

LetC =0.047 ~ (for both stages), then 1 1 R=--= =17.8kn 27TfcC 2n(189.8 Hz)(0.0471JF)

ChooseR = 18 kn as nearest standard value which produces feof 188 Hz Other combinations that are scaled variations of these answers are reasonable (for example C =0.022 pF and R = 39 kn produces a cutoff of 185 Hz).

13. See Figure 9-1. Three stages are connected in series with identical frequency determining components. New DF factors need to be determined from Table 9-1. For the six-pole filter, the required damping factors are 1.932, 1.414, and 0.518 respectively. Other combinations that are scaled variations of the gain determining resistors are reasonable.

C,

Va.

0.22 J.LF

R.

R.

4.7kn

6.8kn

c.

O.l"F

C,

I

0.22 "F

R.

R.

4.7 k!l

6.8 k!l

-

R, S.6kn

RIO

4.7kn

6.8kn C.

0.1 "F

R, 10ldl

-

14. See Figure 9-2. Arrangement of blocks may differ.

(c)

(e)

(d)

FIGURE 9-2

51

RII

l.Skn RI2

10 k!l

-

-

(b)

I -

FIGURE 9-1

(a)

0.22 J.LF

R,

V_

uJI

-

Cs

Section 9·4 15. The R's and C's in the frequency determining networks need to be reversed as shown in Figure 9-3. The gain resistors remain the same. Since it is an equal value circuit, scaled vales from those shown in Figure 9-3 are reasonable. (See problem 12 for example calculation).

39kn

V.

C1

39kn C.

C2

C.

~ I--~ 1----<~__1 0.022 p.F 0.022 p.F

0.022 p.F 0.022 p.F

~

R.

39kn

39kn

R, 6.8kn

It.

S.6kn

FIGURE 9·3 16. Answers will vary. To obtain one-half the critical frequency, either the resistors or the capacitors (but not both) in the frequency determining network can be doubled. For example, in Figure 9-3, a 78 kn resistor (5% standard is 75 ill) and 0.022 pF capacitor will have one-half the critical frequency. Using 75 ill resistors and 0.022 pF capacitors produce anfc of 96 Hz. Other scaled answers are reasonable.

17. (a) The critical frequency can be increased by either reducing Rl andR2 by some factor or increasing C 1 and C2• (b) Gain can be increased by either increasing R3 or decreasing R4 • Section 9·5 18. (a) Cascaded high-pass/low-pass (Sallen-Key) filters (b) Multiple feedback (c) State-variable 19. (a) 1st stage:

1

tel =2rrRC 1

2nd stage:

1 2n(1 kn)(O.047 JlF) =3.39 kHz

1

tc2 =2;iiC =2n(1 kn)(O.022 JlF) =7.23 kHz

to =Jt cl c2 =J(3.39 kHz) (7 .23 kHz) =4.95 kHz BW=7.23 kHz- 3.39 kHz =3.85 kHz

52

Chapter 11: Section 11·1 1. Line regulation =(L1:OUT) 100% = ( 2 mV )100% = 0.0333% VIN 18V-6V 2. Line regulation = ( L1VouiVOUT)100% =(2 mV/8 V)100% =0.00417 %N L1VIN 6V 3. Load regulation =(VNL - VFL)100%=( 10 V -9.90 V)100% = 1.01 % V FL 9.90 V 4. From problem 3, the percent load regulation is 1.01 %. For a full load current of 250 rnA, this can be expressed as: 1.01 % - - - = 0.00404 %/mA 250mA

Section 11·2 5. The functional blocks are shown in Figure 11-1.

FIGURE 11·1 6.

VOUT=(1 + R2)VREF=(1 + 33kQ)2.4 V=lO.3 V R3 lOkQ

7.

VOUT=(1 + R2)VREF=(1 + 5.6kQ)2.4 V=8.51 V R3 2.2kQ

8. ForR3=2.2kQ:

Vour=(1 + R2)VREF=(1 + 5.6kQ)2.4 V=8.51 V R3 2.2kQ

ForR3 =4.7 kQ:

Vour=(1 + R2)VREF= (1 + 5.6 kQ)2.4 V =5.26 V R3 4.7 kQ

The output voltage decreases by 3.25 V whenR3 is changed from 2.2 kQ to 4.7 kQ.

59

( R2) R3

kQ) 2.7 V=9.57 V 9. VOUT= 1 +- VREP = (5.6 1+ 2.2kQ

0.7 V 10. Ir.(max) = - R4

0.7 V

0.7 V

IL(max)

250 rnA

R 4 =--= 2

=2.8Q 2

P = lu,naxp4= (250 rnA) 2.8 Q = 0.175 W, Use a 0.25 W

11. If R4 is halved, the load current is doubled as shown in the following: 2.8 Q 0.7 V 0.7 V R4 =--=1.4Q I =--=--=500 rnA 2 L(max) R4 1.4 Q Section 11-3 12. When the load current increases, Your increases causing the sense feedback voltage to increase. This higher voltage at the op-arnp's noninverting input causes the op-arnp's output to increase, thus making Q\ conduct more.

AVR1 1V 13. M =--= =10 rnA c Rl 100 Q

14. VOUT=(l + R3)VREP=(1 + 8.2kQ)5.1 V= 15.8 V R4 3.9 kQ

V OUT

III = - - = RLl

15.8 V = 15.8 rnA 1.0 kQ

V OUT 15.8 V 112 =--= = 13.2 rnA R12 1.2kQ

ML = 13.2 rnA-15.8 mA=- 2.64 rnA

Ms =- ML = +2.64 rnA VIN 25 V 15. lu,nax) = R 1 = 100 Q = 250 rnA 2

2

P R1 =/L(maxP 1 = (250 rnA) 100 Q = 6.25 W

60

Chapter 12: Section 12-1 Rl 100 kn 1. Av(l) = 1 +- = 1 + = 101 RG 1.0 kn

R2

100kn

RG

1.0kn

Al(2)= 1 +- = 1 +

2R

= 101

200kn

2. A 1= 1 + - = 1 + = 201 c RG 1.0kn

2R

4. A y =1 +RG

2R

-=A -1 R y G

R = 2R = 2(100 kn) = 200 kn = 200 n G Ay - 1 1000 - 1 999

A = 50.5 k.Q

5.

y

RG

+

1 = 50.5 kn 1 = 515 1.0 kn + .

6. From the graphic in Figure 12-6, for a gain of 10, BW::300kHz 7

•

R = 50.5 kQ = 50.5 = 2 2 k A G A y -1 23 . ~~

8 R •

G

= 50.5 k.Q = 50.5 = 2 7 k A

A y -1

19

.

~~

64

Section 12-3 lout

14. g = - = m

V in

10 JlA =1 mS lOmV

15. lout = g mVin = (5000 J.!S)(100 mV) = 500 JlA V out = Iou,RL = (500 JlA)(lO kn) = 5 V

I out 16 . gm=V in lout = g mVin = (4000 J.!S)(100 mV) = 400 JlA R = V out = 3.5 V =8.75 kn L lout 400 JlA

17.1

BIAS

=

+12 V - (-12 V)- 0.7 V +12 V - (-12 V)- 0.7 V 23.3 V = = =106"A R BIAS 220 kn 220 kl""l ~ .u

From the graph in Figure 1243, g m == 2500 J.!S V I 11 Av = out = ~ = g,fl L = (2500 J.!S)(6.8 kn) = 17.0 Vin

Vin

18. Maximum voltage gain is when the potentiometer is set to 0 n, matching the answer given in problem 17; Av(max) = 17.

The minimum voltage gain occurs when the 10 kn potentiometer is set to 10 kn: +12 V - (-12 V)- 0.7 V 23.3 V I BIAS = 220 kn + 10 ill = 230 kn = 10 1 JlA From the graph in Figure 1243, gm== 2000 J.!S Av(min) = g,fl L = (2000 J.!S)(6.8 kn) = 13.6

19. The VMOD waveform is applied to the bias input. The gain and output voltage for each value of VMOD is determined as follows using a K of 16 pS/pA (from Figure 12-16 in the text and given in the problem). The output waveform is shown in Figure 12-1. A sample calculation is given for VMOD = +8 V. The remaining results are summarized in Table 12-1.

66

ForVMOD =+8 V: I

- +8 V - (-9 V)- 0.7 V _ 16.3 V -418 J1A BIAS 39 kQ - 39 kQ -

g m = KIBIAS == 16(418 J1A) = 6.69 mS V out Iou!?L Av = = - - = g"~ L = (6.69 mS)(10 kQ) = 66.9 Vin Vin Vout=AvVin = (66.9)(100 mV) = 6.69 V

Table 12-1

~~9V-----

- - -- ---------------------------------

+5.87 v- - - - +5.04 V - - - - -

-

+422 V - - - - -

-

+3.81 V-----

o -3.BI V • - - - - -4.22 V ------ -5.04 V _ _ _ _ _ _ _

-5.B7 V - - - - --6.69 V - - - - - -

-

-

--

------- ---------------- -----------

FIGURE 12-1 20. IB1AS =

+9V-(-9V)-0.7V 17.3V = = 444 J1A 39 kQ 39.kQ

VTRIo:+) =IBlAi?-l = (444 J1A)(10 kQ) = +4.44

VTRIo:-)=-IBIASRl =(-444J1A)(lOkQ)=-4.44 V

67

-

--

21. See Figure 12-2

o~+----------------~---------------~.-

,

-".'I1V

--t----------------, :

-lOV

--~-----------------T-----

:,

:'

,,

'

'

,,

,,

+1.1 V - '

-1.'1 V

FIGURE 12-2 Section 12-4 22. (a) In 0.5 = - 0.693 (b) In 2 = 0.693 (c) In 50 = 3.912 (d) In 130 = 4.868 23. (a) log 0.5 = - 0.301 (b) log 2 = 0.301 (c) log 50 = 1.699 (d) log 130 = 2.114 24. Antilog x = lOX

INV LOG = 101.6 = 39.8

25. The output of a standard log amp is limited to 0.7 V because the output voltage is limited to the barrier potential of the transistor's pn junction.

(3 V )=-148 mV (100 nA)(82 kn)

26. Vout =- (0.025 V) In( - Vin) =- (0.025 V)ln Iflin

) =-157 mV 27. Vout = - (0.025 V) In( - Vin ) =- (0.025 V) In( 1 . 5 V Iflin (60 nA)(47 kn)

28. Vout=-RIEBoantiloge(

V. ) ( Vin ) In =-R-rlEBcY 25mV 25mV

( 0.225 V)

Vout =-(10 kn)(60 nA~ 25mV =- (10 kn)(60 nA)(8103) =- 4.86 V

68

Chapter 13: Section 13-1 1. See Figure 13-1

FIGURE 13-1 2. See Figure 13-2

FIGURE 13-2 3. fLo = 680 kHz + 455 kHz = 1135 kHz 4. fLo =97.2 MHz + 10.7 MHz= 107.9 MHz

5. fRF= 101.9 MHz-1O.7 MHz =91.2 MHz flF = 10.7 MHz (always)

70

2. See Figure 14-2

o

1

ll-----•

o

0

I I I I I

I I I I

I I

I I

I I

I I

n

I I

I I

n

I

I

I I

I I

Output

FIGURE 14·2

77

Section 14·2 3. See Figure 14-3

Analog In

s

S/H Control

H

H

I

I

Output

D

FIGURE 14·3 4. See Figure 14-4

AmlogIn

SIH Control

Output.

FIGURE 14·3

78

s

5. (a) Av = 1 The ADC585 is connected as a voltage follower.

R2 lOkn (b) A v = R lllR ext + 1 = 10 knlllO ill + 1 =2 + 1 = 3

Section 14-3 6. See Table 14-1 Table 14-1

lS~~-r~--~~-r~--~~-.-.--.--,

~~~~~~~~

7. See Figure 14-5

7

:

::

o0

l 1 ~ ~8

:::

10

12 14 lo~. 0

l ~ ~ (rna)

FIGURE 14-5 8. See Figure 14-6

000ll--l--+-+--+-+-+-+--+--+--+--+--+-----i--+-+-+-t-f--l---iI--i--i--i--t-' OOOO~~~~~~~~~~~~~~~~~~~~~~~~~~~~.

o

2

4

6

8

10

12

14

FIGURE 14-6

79

16

18

20

22

24

26 -

I

Section 14-4 9. Ro= lOkQ Ro

lOkQ

2

2

Rl =-=

=5kQ

Rl 5kQ R2 = - = - - =2.5 kQ

2

2

R2

2.5 kQ

2

2

R3 = - =

= 1.25 kQ

10. The input high level is 5.0 V and the input low level is 0 V. The binary sequences of the input numbers and corresponding output values are shown in Table 14-2. The output waveform is shown in Figure 14-7.

Table 14-2 lOkQ)

V00 =- ( 200 kQ 5.0 V =-0.25 V

10 kQ )

VDl =- (

lOOkQ

5.0 V =-0.50 V

Vm =- ( 10 kQ) 5.0V=-1.0V

50kQ

VD3 =- ( 10 kQ) 5.0 V =-2.0 V 25kQ

o

:::::: :::::: ________ ::::::::::::~::::::J::::::L::::::[:: I

-1~:::

I

_____________________________________

______ J I ______ I

~

I

I

______ IL __ I

- - - - - - - - - - - - .---"""'___________________________________________ ~

-2.0- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

~----L---------

------ -------------------------------

~.o-------------------------------------------.-----------------.----------- ------

~.o-------------------------------------------------------------

FIGURE 14-7 80

11. See Table 14-3 and Figure 14-8

Table 14-3

II1II.

Lh----.---;

.. .

•

o

I

:

---- --- '--- --~---~--- ----------____ ---~--~---~--~---- ---~----_ __ J___ _____________

~D--------

---.--~---

-------4D--------

---r--~--~

I

------------ __

~~------------

~

__ ___ ---------.

--------- ____ __ I

•

--~---

~---

I

I

-- --- ------------ --- -----------

---~--,--~ J _____

•

•

---

__________ _

---------. _________________ J ____________________ _ ---~--,---

~D---------------------------------------------------- --------

FIGURE 14-8 12. (a) (

1 )100 % = 14.3 % 2 -1 3

(b)

1 )100 % = 0.0978 % (10 2 -1

(c)

1 )100 %=0.000381 % (18 2 -1

81

Section 14-5 13. (a) 24 = 16 (b) 2 5 =32 (c) 2 8 =256 (d) 2 16 = 65,536

14. The minimum Nyquist frequency must be greater than twice the input frequency:

(a) :If =2( (b)

:If=2( ~) =2C ~s ) =2(1 kHz) =2kHZ; [N,...,., must be > 2kHz

(c) 2[= 2( (d)

~) =2C~ s) =2(0.1 Hz) =0.2 HZ; [Nyqu., must be > 0.2 Hz

~) =2( 30\.lS ) =2(33.3 kHz) =66.7 kHZ; [Nyqui" must be > 66.7 kHz

21= 2(!) = 2( 1 ) = 2(1 MHz) = 2 MHz; INyquistmust be > 2 MHz T 1000 ns

15. Quantization error = (100 m V/s)( 10 ms) = 1 m V

Section 14-6 16. See Table 14-4

Table 14-4

Table 14-5

17. See Table 14-5

82

18. 0000, initial state 1000 try 8 V , resets to 0000 (8 V > 6 V) 0100 try 4 V, keeps 0100 (4 V $ 6 V) 0110 try 6 V, keeps 0110 (6 V $ 6 V) 0111 try 7 V, resets to 0110 (8 V> 6 V) 0110, conversion complete

Section 14·7 19. The output frequency increases when the input voltage increases.

20. I¥out = 1 kHz = 500 Hz/V ~Vin 2V I¥out) fout = ~Vin( - = (4 V)(500 H7/V) = 2 kHz ~Vin

oJ6.8 x 10 sIP) + 3 x 10- s 3 10- s = C oJ 6.8 x 10 sIP) 3

21. tos = C tos-

7

7

X

3

t os - 3 x 10 -7 S

5 JlS - 3 x 10 -7 S 4.7 JlS Cos= 6.8 X 10 3 sIP = 6.8 X 10 3 sIP = 6.8 X 10 3 sIP =691 pF (select 680 pF)

22. tos = C

oJ6.8 x 10 sIP) + 3 x 10- = (470 pF)(6.8 x 10 sIP) + 3 x 10- = 3.5 JlS 3

7S

3

7S

Vin 3.5 V 1· =-= =292"A In R. 12kQ ~ In

~V=

(1 rnA-ljn)tos

=

(1 rnA- 291.7 J.1A)3.5JlS 1500 pF

C jnt 23. Vin(rnin) == 1.1 V,

1

1.1 V

= 1.65 V

Vjn(rnax) == 3.4 V

1.1 V

in(rnin) = ~ = 12 kQ =

917 A . Jl

1

3.4 V

3.4 V

in(rnax) = ~ = 12 kQ =

1 in(rnin) 91.7 JlA fout(rnin) = t os(l rnA) = (3.5 Jls)(l rnA) = 26.2 kHz 1 in(rnax) 283 JlA fout(rnax) = toil rnA) = (3.5 Jls)(l rnA) = 80.9 kHz

83

283" A I-"H

Section 14-8 24. See Figure 14-7 .wbi

0111,,,,

J i i i i .. J i ~'''''''I i i i ! i 9 ~ ~ s ~ ~ ~ ~ E o

................. Iili!!~~~i~~~~~~ FIGURE 14-7 25. The output sequence is 0001, 0001, 0011, 0011, 0001, 0001, 0011, 0011, 1001, 1001, 1011, 1001, 1001, 1011, 1011. Observing this pattern, it can be seen that Do is stuck at 1 and D2 is stuck at O. 26. See Figure 14-8. Note: a flash converter may shown the next lower value (0110) instead of 0000 assuming the failure was due to a faulty comparator.

Jw.blr

owp'UI:

FIGURE 14-8

84

Chapter 15: Section 15-1 1. The sinusoidal source must be 5 V nns.

Section 15-2 3. The angle measured is 180° + 0 + 0 + 0 + 5.62Y + 2.813° + 1.406° = 189.84° 4. The angle measured is 0 + 0 + 0 + 22.5° + 0 + 5.625° + 1.406° = 29.53° 5. The AD2S90 holds 12 bits.

6. The direction output on a AD2S90 RDC indicates the direction of rotation of the shaft being measured. The velocity is proportional to the rate of change of the input angle.

Section 15-3 7. Assuming all are of the same type, the thennocouple exposed to the highest temperature (thennocouple C) produces the highest output. Note that thennocouple voltages are significantly different for different types as indicated in Figure 15-20.

8. The letters indicate the temperature range, coefficient, and voltage characteristic.

9. V Thermocouple = 20.869 mV (from Table 15-2 in the text) V Ambientjunction = 0.25(4.277 m V) = 1.069 mV

The voltage across the op-amp inputs: VThermocouple- VAmbientjunction = 20.869 mV -

1.069 mV = 19.80 mV

For the inverting amplifier.

Rf 220kn A = - - == - 220 v R.I 1.0 kn V out = (-220)(19.80 mV) =- 4.36 V

10. When properly compensated, the input voltage to the amplifier is equal to the thennocouple voltage of 20.869 m V, so the output voltage is: Rf (220 kn) Vout=--Vin = (20.869 mV) =-4.59 V Ri 1.0 kn 11. The bridge is balanced when Rw+RRTD+Rw= 560 n R RTD = 560 n - 2R w = 560 n - 20 n = 540 n

85

PART TWO Laboratory Solutions for Experiments in DC/AC Fundamentals

David Buchla

91

Experiment 1: Signal Sources and Amplifier Characteristics Procedure 2.

Answer depends on the particular function generator. Typical function generators have a Thevenin resistance of 50  or 600  and the load resistor will be nearly the same value.

Table 1-1

Table 1-2

Resistor Listed Measured Value Value R1 10 kΩ 10.3 k R2 1.8 kΩ 1.76 k RE 1.0 kΩ 992  RC 3.9 kΩ 3.88 k

Vin 500 mVpp 1.0 Vpp 1.5 Vpp 2.0 Vpp 2.5 Vpp 3.0 Vpp 3.5 Vpp

Vout 1.90 Vpp 3.85 Vpp 5.70 Vpp 7.60 Vpp 9.50 Vpp 11.2 Vpp 11.8 Vpp

Av 3.80 3.85 3.80 3.80 3.80 3.73* 3.31

* onset of clipping

Plot 1-1

Plot 1-2 Answer for Question 4

Evaluation and Review Questions 1.

Answer depends on the Thevenin resistance of the generator. For a 600  generator that is set to 200 mV, the Norton current is 200 mV/600  = 333 A as shown.

2.

An ohmmeter cannot be used in an energized circuit. The generator’s output resistance cannot be measured with the generator off, so an indirect measurement must be done.

3.

Answer depends on the Thevenin resistance of the generator. For a 600  generator, 100  100   600   = 0.142

4.

See Plot 1-2, above. The general shape should show a linear region followed by a region where the output changes very little for a larger input. Although the gain is nonlinear, the output signal is not distorted (clipped) over a larger region with AGC.

5.

20 log 3.85 = 11.7

92

For Further Investigation The input resistance of the amplifier is measured by observing the loaded and unloaded input voltage, applying Ohm’s law and solving for Rin (amplifier) . The equation for finding Rin (amplifier) is: Rin (amplifier) RTH  Vin (amplifier) VNL  Vin (amplifier) Rin (amplifier)  Vin (amplifier) 

RTH VNL  Vin (amplifier)

The result for the tested amplifier is Rin (amplifier)  1.5 k.

93

Experiment 2: The Diode Characteristic Procedure Table 2-1 Component

Listed Value 330 

Measured Value 331 Ω

1.0 M D1 forward resistance

1.05 MΩ

D1 reverse resistance

no reading

R1 R2

Table 2-2 VF

500 Ω*

* depends on meter

6.

Table 2-3 VR2 (measured) 5.0 V

VR (measured) 454 mV

IR (computed) 0.43 µA

10.0 V

890 mV

0.85 µA

15.0 V

1.3 V

1.24 µA

0.45 V

VR1 (measured) 3.8 mV

IF (computed) 11 µA

0.50 V

16.3 mV

49 µA

0.55 V

83 mV

250 µA

0.60 V

230 mV

695 µA

0.65 V

690 mV

2.08 mA

0.70 V

1.85 V

5.59 mA

0.75 V

4.58 V

13.8 mA

The addition of heat causes the voltage across the diode to drop resulting in an increase in diode current. Cooling the diode does the opposite.

8.

Plot of the diode curve:

14 12

Current (mA)

10 8.0 6.0 4.0 2.0 -15 0

2.0

Note Scale change -10

-5.0 0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Voltage (V)

Plot 2-1 9.

Heat again causes an increase in diode current; cooling the diode does the opposite.

10.

The diode curve, shown in Plot 2-1, is plotted on the oscilloscope.

94

Evaluation and Review Questions 1.

For the forward-biased case, factors that affect the accuracy include temperature, manufacturing variations between diodes, plus resistance and voltage measurement error.

For the reverse-biased case, meter loading error is probably the most significant error plus the errors cited previously.

2.

rac (0.5 V) =

3.

Answers vary. For the diode tested, the max power dissipated in the diode was 10.4 mW.

4.

The barrier potential is decreased with the addition of heat.

5.

The meter leads must be identified for the polarity of the voltage present on the ohms function. The diode resistance is measured in both directions. The cathode is connected to the most negative lead when the resistance is lowest.

418 Ω

rac (0.6 V) =

For Further Investigation

Plot 2-2

95

55 Ω

rac (0.7 V) =

8.5 Ω

.

Experiment 3: Rectifier Circuits Procedure 20 V

20 V

Vsec

V out

-20 V

2.0 ms/div

-20 V

2.0 ms/div

Plot 3-1

Table 31 Half-wave rectifier Without Filter Capacitor Vsec(rms)

Vsec(rms)

With Filter Capacitor

Vout(p)

Vout(p)

VOUT(DC)

Vr(pp)

Ripple Frequency 60 Hz

(computed)

(measured)

(computed)

(measured)

(measured)

(measured)

12.6 V ac

14.4 V rms

20.3 Vp

20.0 Vp

19.1 V dc

1.4 Vpp

10 V

10 V

Vsec

Vout

-10 V

-10 V

2.0 ms/div

2.0 ms/div

Plot 3-2 Table 32 Full-wave rectifier circuit Without Filter Capacitor Vsec(rms)

Vsec(rms)

Vout(p)

(measured)

With Filter Capacitor Vout(p)

VOUT(DC)

Vr(pp)

Ripple Frequency 120 Hz

(computed)

(measured)

(computed)

(measured)

(measured)

(measured)

6.3 V ac

7.3 V rms

10.2 Vp

9.8 Vp

9.5 V dc

0.35 Vpp

(measured)

Step 7 observations: A second parallel load resistor increases the load current and the ripple voltage.

Table 33 Bridge rectifier circuit Without Filter Capacitor Vsec(rms)

Vsec(rms)

Vout(p)

With Filter Capacitor Vout(p)

VOUT(DC)

Vr(pp)

Ripple Frequency 120 Hz

(computed)

(measured)

(computed)

(measured)

(measured)

(measured)

12.6 V ac

14.5 V rms

20.5 Vp

19.5 Vp

19.0 V dc

0.65 Vpp

(measured)

Step 10 observations: The output voltage drops; ripple voltage is doubled; ripple frequency is 60 Hz.

96

Evaluation and Review Questions 1.

The full wave-circuit is more efficient and has less ripple than the half-wave circuit.

2.

Given a specific transformer and load, the bridge circuit has a higher output voltage and current (nearly double). For both configurations, the diode current is approximately onehalf the dc load current, but because of the bridge's higher output voltage, the diode currents will be greater.

3.

If the scope ground is the same as the center-tap of the transformer, the probes need to be connected as shown to avoid placing a direct short across the secondary.

4.

If a diode is open in a bridge circuit, the ripple frequency will be halved.

5.

(a) The bridge output voltage is the peak voltage minus two diode drops = 24 Vdc. (b) The full-wave output voltage is one-half peak voltage minus one diode drop = 12 Vdc.

For Further Investigation The test circuit output had approximately 1 mV of ripple. The ripple waveform showed only the tip of the positive waveform. Noise level was less than 1 mV.

97

Experiment 4: Diode Limiting and Clamping Circuits Procedure +3.0 V

Vs

0V

3.0 V

+0.7 V

Vout 0 V

2.5 V +2.3 V

VR2 0 V

0.5 V Vertical 2 V/div Horiz = 0.2 ms/div

Plot 4-1 3.

The positive clipping level follows changes in the power supply level. As the supply is increased, the positive clipping level moves up.

4.

Reversing the diode results in a negative clipping circuit. The negative half is fully clipped and the clipping level can be raised (made more positive) by increasing the power supply voltage.

5.

Changing the bias voltage to a negative supply causes the negative clipping level to vary.

As the power supply voltage is increased, the negative clipping level decreases.

6.

A slight decrease in clipping level occurs.

7.

The output is an ac waveform that varies from approximately -0.6 V to +5.3 V. The negative portion of the waveform is slightly distorted when the diode conducts.

8.

+5.3 V

Vout 0V

0.6 V Vertical 2 V/div Horiz = 0.2 ms/div

Plot 3-2

9.

The negative bias voltage moves the clamping level down.

98

Evaluation and Review Questions 1.

Kirchhoff's voltage law can be applied to a time varying waveform. The voltage across R2 can be predicted at each point in time by subtracting VRL from VS.

2.

The negative portion of the waveform would be clipped.

3.

Reversing the diode changes the circuit to a negative clamping circuit. The clamping level can be moved in the positive direction by the supply until the output and input waveforms are equal.

4.

A limiting circuit removes a portion of an ac waveform. A clamping circuit adds a dc voltage to the ac waveform.

5.

The positive portion of the waveform is clipped at approximately +2 V (three diode drops); the negative waveform is unaffected (reverse-biased diodes).

For Further Investigation The voltage divider (R2 and R3), cause the cathode of the diode to be biased at +5.0 V. Although limiting action begins at approximately +5.7 V, as expected, the waveform is rounded due to the ac resistance to ground. By placing the 47 µF capacitor across R2, the ac resistance to ground is brought near zero and limiting is greatly improved with a flat top at +5.7 V.

99

Experiment 5: Special-Purpose Diodes Procedure (Measured inductance = 14.2 mH) Table 5-1 Resonant VBIAS Frequency, fr 0.0 V 83 kHz 1.0 V 98 kHz 2.0 V 108 kHz 4.0 V 120 kHz 8.0 V 131 kHz 15.0 V 143 kHz 140

Table 5-2

130

Parameter Measured Value resonant frequency, fr 143.4 kHz* upper critical frequency, fcu 146.2 kHz* lower critical frequency, fcl 140.3 kHz* bandwidth, BW 5.9 kHz Q 24

fr (kHz)

120 110 100 90 80

0

2

4

6

8 10 VBIAS (V)

12

14

* frequency counter used for these measurements

16

Plot 5-1 Part 2 Step 1: The red LED drops approximately 1.65 V when forward-biased (measured at 10 mA of current) and has the smallest ac resistance (approximately 50 Ω in the region tested). The yellow LED is drops approximately 1.9 V when forward-biased. The green LED is drops approximately 2.0 V and has the highest ac resistance (approximately 100  in the region tested).

Step 2: The reverse curve drops as light is increased. (Note: The optimum value of R1 depends on the diode and lighting conditions).

100

Evaluation and Review Questions 1.

(a) Answers will vary. The capacitance of the tested varactors was inferred to be 265 pF (total) or 265 pF each. Note that the lower varactor is shorted out with zero bias so only one is active in this case. (Computed from fr = 82 kHz and a 14.2 mH inductor). (b) Answers will vary. The capacitance of the tested varactors was inferred to be 87.2 pF (total) at a bias voltage of +15 V or approximately 174 pF each. (Computed from fr = 143kHz and a 14.2 mH inductor).

2.

(a) It would not have an effect on the resonant frequency because the resonant frequency is determined by the LC circuit. (b) It will affect the Q because R1 acts as a resistive load on the resonant circuit.

3.

(a)

4.

Electrical: forward voltage drop at a specified forward current, reverse leakage current IR, and reverse breakdown voltage V(BR)R. Optical: peak emission wavelength (in nm), power output (in milliwatts or microwatts) PO, and spectral output.

5.

The photodiode is a current source; a larger resistor develops more voltage for a given current, making the circuit more sensitive to light.

I = 18.0 V – 2.0 V = 23.5 mA 680 

(b)

R = 18.0 V – 2.0 V = 533  30 mA

For Further Investigation Measured data for a green LED is shown in the table and plot.

Angle 90˚ 75˚ 60˚ 45˚ 30˚ 15˚ 0˚ +15˚ +30˚ +45˚ +60˚ +75˚ +90˚

Voltage 0.56 V 0.90 V 1.1 V 1.5 V 3.5 V 5.6 V 6.0 V 5.3 V 2.3 V 1.1 V 0.85 V 0.69 V 0.29 V

+15

o

0

o

6V

+30o

5V

o

4V

+45

3V

+60o +75

o

+90o

101

15 o 30 o 45

o

2V

60 o

1V

75 o 90 o

Experiment 6: Bipolar Junction Transistor Characteristics Procedure Values shown are for a 2N3904 transistor:

Table 6-1 Resistor R1

Listed Value 33 k

Measured Value 32.8 kΩ

R2

100 

104 Ω

Table 6-2 VCE

(measured)

Base Current = 50 µA VR2 (measured) IC (computed)

Base Current = 100 µA VR2 (measured) IC (computed)

Base Current = 150 µA VR2 (measured) IC (computed)

2.0 V

0.900 V

8.65 mA

1.91 V

18.4 mA

2.93 V

28.2 mA

4.0 V

0.931 V

8.95 mA

2.01 V

19.3 mA

3.14 V

30.2 mA

6.0 V

0.955 V

9.18 mA

2.13 V

20.5 mA

3.38 V

32.5 mA

8.0 V

0.992 V

9.54 mA

2.23 V

21.4 mA

3.58 V

34.4 mA

35

IB = 150 A

30 25

IB = 100 A

IC 20

(mA)

15 10

IB = 50 A

5 0

0

1

2

3

4

5

6

VCE (V) Plot 6-1

Table 6-3 Current Gain, ßDC VCE

IB = 50 µA

IB = 100 µA

IB = 150 µA

3.0 V

176

189

193

5.0 V

192

200

209

102

7

8

Evaluation and Review Questions 1.

For the test transistor, the ßDC was not constant at all points (see Plot 6-1). This has an effect on linearity as the gain will change as the operating point changes.

2.

It would raise all of the curves.

3.

Answers vary. For the test transistor, maximum power dissipated was 8 V x 34 mA = 272 mW.

4.

(a) β DC 

IC IB IC

α

IC IE



IC IC  I B



IB IC IB



IB



β DC β DC  1

IB

(b) Answers vary. The alpha for the test transistor was approximately 0.995.

5.

VCE would equal VCC. Without base current, there would be no collector current and the supply voltage would appear across the transistor.

For Further Investigation The transistor curve tracer confirms the result in Plot 6-1. Heating the transistor causes the beta to rise.

103

Experiment 7: Bipolar Transistor Biasing Procedure Note: The same three randomly selected 2N3904 transistors were used for the data in this experiment.

Computed values shown are based on the measured resistors.

Table 7-1 Resistor Listed Value RB 1.0 M RC 2.0 k Table 7-3 Resistor Listed Value R1 33 k R2 6.8 k RE 470  RC

2.0 k

Table 7-5 Resistor

Measured Value 1.00 MΩ 1.97 kΩ

465 Ω 1.97 kΩ

RB

Measured Value 362 kΩ

RC

2.0 k

1.97 kΩ

Measured Value Q1 Q2 Q3 11.4 V 11.3 V 11.3 V

IC

2.26 mA

VRC

4.52 V

2.40 V

7.00 V

3.73 V

VC

7.48 V

9.59 V

4.99 V

8.27 V

Table 7-4 Quantity Computed Value

Measured Value 32.6 kΩ 6.83 kΩ

Listed Value 360 k

Table 7-2 Quantity Computed Value VRB 11.3 V IB 11.3 µA

Measured Value Q1 Q2 Q3

VB

2.08 V

1.96 V

2.03 V

1.99 V

VE

1.38 V

1.26 V

1.36 V

1.30 V

IE IC VRC

2.96 mA 5.84 V

5.30 V

5.73 V

5.44 V

VC

6.16 V

6.70 V

6.28 V

6.57 V

Table 7-6 Quantity Computed Value

Measured Value Q1 Q2 Q3

IC

2.97 mA

VRC

5.95 V

4.42 V

7.14 V

5.42 V

VC

6.05 V

7.57 V

4.85 V

6.57 V

Evaluation and Review Questions 1.

The voltage divider bias (Table 7-4) showed the least variation between transistors.

2.

PNP transistors with positive supplies are shown for base bias, voltage-divider bias and collector-feedback bias with voltages calculated for  = 200.

VCC

+12 V

VCC

+12 V

1.0 M 

6.8 k 

+9.95 V

+11.3 V

RB

R2

+4.5 V

RC

2.0 k 

R1

33 k 

VCC

+12 V

RE

470  +10.65 V +5.75 V

RC

2.0 k 

104

+11.3 V

RB 360 k 

+5.95 V

RC

2.0 k 

3.

For 20 mA of collector current, the emitter voltage should be approximately 0.94 V, making the base voltage 1.64 V. Choose R2 to be 10X larger than the emitter resistor for stiff bias: 470  for a first check. The current in R2 is approximately the same in R1 giving a 6.4 k resistance. These values can be refined to give standard resistors – for example 510  and 6.8 k gives a base voltage of 1.67 V and a collector current of 20.6 mA.

4.

Rearranging the equation for collector feedback bias and using emitter voltage for the pnp transistor in place of collector voltage results in:

V  V  RB = β DC  EE BE  RC   IC   +18 V  0.7 V   200   1.2 k   5.0 mA   452 k (Choose 470 k as the nearest standard value).

5.

(a) +24 V

(Transistor is cutoff.)

(b) +24 V

(Transistor is cutoff.)

(c) +22.6 V (Collector current is 1/10 of its correct value, or 2.0 mA. The collector voltage is then 24 V  1.4 V = 22.6 V.) (d) +10.3 V (Base voltage drops by a factor of 15/24. The desired 1.64 V will be approximately = 1.03 V giving an emitter voltage of approximately 0.33 V. The collector current is therefore 7 mA and collector voltage = 10.3 V).

For Further Investigation Computed and measured parameters for the emitter-biased circuit are shown in the table.

Computed values were based on a ßDC of 200. The same three transistors used in the experiment were tested with results comparable to voltage-divider bias.

Emitter-biased circuit Quantity Computed Value

Q1

Measured Value Q2

1.31 V 1.99 V

0.52 V 1.18 V

0.92 V 1.60 V

Q3

VE

0.78 V 1.48 V

IE ≈IC

10.5 mA

VB

5.57 V

5.16 V

5.62 V

5.38 V

VC

6.43 V

6.83 V

6.37 V

6.61 V

VB

105

Experiment 8:The Common-Emitter Amplifier Procedure Table 8-1 Resistor Listed Measured Value Value R1 10 k 9.87 kΩ R2 4.7 k 4.66 kΩ RE1 100 Ω 100 

Table 8-2 DC Parameter VB

Computed Value 3.85 V

Measured Value 3.74 V

VE

3.15 V

3.04 V

RE2

330 

333 Ω

IE

7.02 mA

RC

1.0 k

1.00 kΩ

VC

4.98 V

4.87 V

RL

10 k

10.1 kΩ

VCE

1.83 V

1.93 V

Table 8-3 AC Parameter Vin = Vb Ve 

Computed Value 300 mVpp 290 mVpp

Measured Value 300 mVpp 280 mVpp

re Av

3.6 Ω 8.8

8.43

VC

2.63 Vpp

2.53 Vpp

Rin(tot)

2.9 kΩ*

2.89 kΩ

* Measured ßac of 300 used for calculation

7.

Vin and Vout are 180 degrees out of phase.

8.

The gain drops to 2.2 when C2 is opened.

9.

The gain rises (by 10%) with RL removed.

10.

Transistor is cutoff since there is no path for base current. (Note that a measurement of VCE could mislead student to thinking transistor is near saturation, however the power supply voltage is across the reverse biased base-collector junction, not across RC).

11.

Transistor is saturated. VC and VE are nearly the same and current is limited only by RC and RE. Maximum current is in the collector circuit.

Evaluation and Review Questions 1.

When C2 is open, the ac resistance of the emitter circuit is increased. Since voltage gain is the ratio of the ac collector resistance divided by the ac emitter resistance, the gain is reduced.

2.

Monitoring the output voltage insures that the amplifier is performing normally during the test. If the output is clipped or distorted, the measurement is invalid.

3.

Transistor is saturated. Since the forward drop across the base-emitter diode is normal, look in the emitter circuit for a shorted resistor (RE2) or capacitor (C2).

106

4.

See Question 3. The base voltage drops because base current rises dramatically, causing the transistor to saturate. (a) dc base voltage = +1.8 V (b) dc collector voltage = +1.1 V

5.

Measure VCE. If VCE is near zero, the transistor is saturated; if VCE is equal to VCC the transistor is cutoff. (Note that if VCE is at zero, there may be a different problem such as no power supply voltage or an open collector resistor.)

For Further Investigation The lower cutoff frequency is approximately 69 Hz (measured). The capacitors affect only the lower cutoff frequency. If C1 and C2 are switched, the new lower cutoff frequency is 1.9 kHz (due to the emitter bypass capacitor).

107

Experiment 9: The Common-Collector Amplifier Procedure Table 9-1 Resistor Listed Value R1 33 k R2 10 k

6.

Measured Value 32.5 kΩ

Table 9-3 AC Parameter Vb

9.98 kΩ

Ve 

RE

1.0 k

1.00 kΩ

RL

1.0 k

1.01 kΩ

Table 9-2 DC Parameter VB

Computed Value 2.82 V

Measured Value 3.08 V

VE

3.52 V

3.77 V

IE

8.48 mA

VCE

3.52 V

Computed Value 1.0 Vpp*

Measured Value 1.0 Vpp

298 mVpp 3.0 Ω

298 mVpp

0.99

0.99

Rin(tot)

6.63 kΩ

7.03 kΩ

Ap

6.5

6.9

re Av

* Input should be 1.0 Vpp

3.77 V

There is no phase shift between the input and output signal.

Table 9-4 Trouble

VB

DC Predictions VE VCE

DC Measurements VB VE VCE

1.39 V 1.39 V 12.0 V 12.0 V

0.66 V 1.37 V

12.0 V 12.0 V 0.0 V 0.0 V

open collector 10.2 V 10.9 V 10.9 V open emitter 2.82 V 12.0 V 12.0 V

R1 open*

0.69 V

R2 open

12.0 V

R1 shorted

12.0 V

RE open

2.82 V

Effect of Trouble on Vout See note 1.

12. 0 V 12.0 V

1.37 V 12.0 V 12.0 V

12. 0 V 0.0 V

0.0 V

No output.

10.3 V 11.0 V

11.0 V 12.0 V

See note 2.

12. 0 V 12.0 V

2.82 V 12.0 V

No output.

No output.

No output.

Note 1: Little effect. The dc conditions can be computed by assuming base bias, however, these conditions change when an ac signal is applied due to clamping action of the transistor and input coupling capacitor. The output ac signal is maintained as a result.

Note 2: Output reduced. The input impedance drops significantly when the collector is open.

Although the voltage gain drops slightly (to about 0.88), the power gain drops significantly (measured = 0.38)

8.

Cutoff clipping is observed first.

9.

As the resistance increases, the clipping level is observed to rise.

108

Evaluation and Review Questions 1.

The input and output are in phase for both types of transistors since the phase relation is a function of the common terminal of the transistor (in this case a common-collector).

2.

In the equivalent npn circuit, positive clipping occurs when the transistor has maximum conduction, hence it is saturation clipping.

3.

(a) Compared to base bias, voltage-divider bias has a more predictable and stable Q-point. (b) Voltage-divider bias requires an additional resistor.

4.

The output voltage is always smaller than the input voltage but the output current is larger than the input current, hence there is power gain.

5.

DC parameters: (VEE = +20 V) VB = +10.9 V VE = +11.6 V IE = 0.84 mA VCE = 11.6 V

AC parameters re' = 29.7  Av = 0.994 Rin(tot) = 34.3 k Ap = 6.8

For Further Investigation Parameters listed below are based on measurements. The output follows (out of phase) the input until clipping begins at approximately an input of 600 mVpp (output of 5.2 Vpp). Cutoff and saturation clipping are observed to begin approximately at the same point. RE1 controls the gain.

DC parameters: (VEE = +12 V) VB(Q1) = +3.66 V VC(Q1) = VB(Q2) = +5.54 V VE(Q1) = +2.96 V VE(Q2) = +6.24 V

AC parameters: Vin = 100 mVpp Vout = 870 mVpp

109

Experiment 10: Transistor Switches Procedure

Table 10-2 Quantity Computed Value VCE(cutoff) 12.0 V VCE(sat) 0.1 V

Table 10-1

RB

Listed Value 10 k

Measured Value 9.88 kΩ

RC

1.0 k

1.00 kΩ

R2

10 k

9.86 kΩ

VRC(sat)

9.9 V

RE

330 

327 Ω

Isat

9.9 mA

Resistor

Measured Value 10.45 V* 0.08 V 9.87 V

* The LED and transistor appear to be open; thus the measurement is affected by meter loading. Answers vary.

Table 10-3

Table 10-4

Quantity Vin(LED on)

Measured Value 0.0 V

Quantity Vin(LED on)

Measured Value 0.0 V

Vout(LED on)

0.080 V

Vout(LED on)

2.735 V

Vin(upper threshold)

3.16 V

Vin(threshold) 0.645 V Vout(threshold) 10.47 V*

Vout(upper threshold) 10.47 V Vin(lower threshold)

1.03 V

Vout(lower threshold) 2.735 V

Evaluation and Review Questions 1.

Some advantages of transistor switching circuits: (1) Very fast (2) Electrically controlled with a low voltage or current (3) Reliable (4) Low cost (5) Can be adopted to interface high current loads with low current circuits.

2.

RB limits current to the base-emitter diode of Q1. Without it, current could destroy the transistor when the potentiometer is set near maximum.

Measure the voltage drop across RB and apply Ohm’s law.

4.

5.

14 12 VOUT (V)

3.

16

The collector resistances are different for the two transistors.

When the transistor reaches saturation, the collector current is constant for any base current, hence  cannot be determined.

10 8 6 4 2 0

For Further Investigation See Plot 7-1.

0

2

4

VIN (V)

Plot 7-1

110

6

8

Experiment 11: JFET Characteristics Procedure Table 11-1 Resistor Listed Value R1 10 k R2 100 

Measured Value 10.0 kΩ 100 Ω

Table 11-2 Gate Voltage = 0.5 V VR2 ID

Gate Voltage = 0 V VR2 ID

VDS

Gate Voltage = 1.0 V VR2 ID

Gate Voltage = 1.5 V VR2 ID

1.0 V 0.304 V

3.04 mA 0.248 V

2.48 mA 0.197 V

1.97 mA 0.152 V

1.52 mA

2.0 V 0.487 V

4.87 mA 0.388 V

3.88 mA 0.291 V

2.91 mA 0.201 V

2.01 mA

3.0 V 0.560 V

5.60 mA 0.443 V

4.43 mA 0.320 V

3.20 mA 0.214 V

2.14 mA

4.0 V 0.588 V

5.88 mA 0.458 V

4.58 mA 0.328 V

3.28 mA 0.218 V

2.18 mA

6.0 V 0.605 V

6.05 mA 0.469 V

4.69 mA 0.333 V

3.33 mA 0.222 V

2.22 mA

8.0 V 0.616 V

6.16 mA 0.469 V

4.69 mA 0.333 V

3.33 mA 0.223 V

2.23 mA

7

VG = 0 V

6 5

ID

(mA)

VG = 0.5 V

4

VG = 1.0 V

3

VG = 1.5 V

2

VGS(off) = 3.22 V IDSS = 6.1 mA

1 0

Table 11-3 Measured JFET Parameters

0

1

2

3

4

5

6

7

8

VDS (V)

Plot 11-1 12.

At VDS = 3.22 V, the current for the tested transistor reached 5.46 mA, 90% of IDSS.

Evaluation and Review Questions 1.

(a) IDSS is the is read in the current source region of the characteristic curves when VGS = 0. (b) 6.1 mA (depends on transistor)

2.

(a) The transconductance is dependent on VGS. (b) Each characteristic curve was drawn with the same increase in VGS but the corresponding drain currents do not follow a linear pattern.

111

3.

Answers vary. For the transistor tested, VP = 3.22 V.

4.

Reverse bias assures that forward current is extremely small; thus the input impedance is high.

5.

The characteristic curve for a bipolar transistor is a plot of base current plotted as a function of collector current. The characteristic curve for a JFET is a plot of gate voltage as a function of drain current. The bipolar transistor is reasonably linear whereas the JFET is not.

For Further Investigation Table 11-4 VGS (measured)

ID (measured)

ID

0V

6.12 mA

(computed) 0.0782

0.5 V

4.56 mA

0.0675

1.0 V

3.32 mA

0.0576

1.5 V

2.23 mA

0.0472

2.0 V

1.33 mA

0.0364

2.5 V

0.580 mA

0.0241

3.0 V

0.119 mA

0.0109

3.5 V

0 mA

0

4.0 V

0 mA

0

4.5 V

0 mA

0

5.0 V

0 mA

0

Plot 11-2

Plot 11-3

112

Experiment 12: JFET Biasing Procedure

Load line for 510  resistor

Table 12-1 Measured JFET Parameters VGS(off) = 3.22 V IDSS = 6.1 mA 3.

RS = 510  (nearest standard R) ID (predicted) = 2.4 mA

4.

ID (measured) = 2.6 mA

1.0

0.8

0.6

0.4

0.2

0

3.22

2.58

1.93

1.29

0.64

0

1.0

6.1

0.8

4.9

0.6

3.7

0.4

2.4

0.2

1.2

0

0

ID (mA)

VGS (V)

Table 12-2 Voltage-divider biased JFET VG

Computed Value 3.00 V

Measured Value 2.95 V

VS

4.27 V

4.41 V

RS

1.78 kΩ

1.80 kΩ

ID

2.4 mA

2.44 mA

Plot 12-1

Evaluation and Review Questions 1.

Cutoff is a gradual point – the value determined by observing the drain current would be dependent on the sensitivity of the meter used.

2.

Both transistors use bias circuits to establish the proper operating point for the circuit. The bias circuits for a bipolar transistor begin to turn the transistor on – the bias circuits for a JFET begin to turn the transistor off.

3.

(a) RG establishes the gate at zero volts. (b) Yes. For the purpose of establishing VGS(OFF) and IDSS, there is no need for the resistor.

4.

The resistors can be much larger values for JFETs since the input impedance is much higher.

5.

An E-MOSFET is a normally off device and must be biased on.

For Further Investigation

The resistor determined in step 3 (510 Ω) should be connected between the source and 12 V of the lower transistor, forming a self-biased current source. With this resistor in place, the measured current in the drain resistor was 2.60 mA, the same as in the voltage-divider bias case.

113

Experiment 13: FET Amplifiers Procedure Table 13-1 Resistor Listed Value RS 1.0 k RD 3.3 k

4.

5.

Measured Value 1.02 kΩ

Table 13-2 Data for CommonSource Amplifier

DC values

Gate voltage, VG

0V

3.26 kΩ

Source voltage, VS

1.73 V

RG

1.0 M

1.01 MΩ

Drain voltage, VD

9.24 V

RL

10 k

9.9 kΩ

Drain current, ID

1.77 mA

The measured output voltage went from 2.26 Vpp to 2.44 Vpp when the 1.0 k source resistor was replaced with 510 . The transconductance, gm, increases because the bias current increases. Gain is AV = gm rd.

AC values

Input voltage, Vin

500 mVpp

Output voltage, Vout Voltage gain, Av

2.26 Vpp 4.53

Phase difference

180˚

When the load resistor was changed from 10 k to 100 k, the output voltage went from 2.44 Vpp to 3.06 Vpp due to the increase in ac drain resistance, rd. As before, AV = gm rd.

Table 13-3 Data for Common-DrainDC Self-biased Amplifier values Gate voltage, VG 0V Source voltage, VS 1.83 V

Table 13-4 Data for Common-Drain DC Current-Source Amplifier values Q1 Gate voltage, VG 0V Q1 Source voltage, VS 1.72

AC values

Drain voltage, VD

15.0 V

Q1 Drain voltage, VD

15.0 V

Drain current, ID

1.83 mA

Q2 Gate voltage, VG

AC values

Input voltage, Vin

2.0 Vpp

Q2 Source voltage, VS

15.0 V 13.3

Output voltage, Vout

Q2 Drain voltage, VD

0V

Voltage gain, Av

1.27 Vpp 0.64

Drain current, ID

1.70 mA

Phase difference

0˚

Input voltage, Vin

2.01 Vpp

Output voltage, Vout Voltage gain, Av

2.00 Vpp 0.996

Phase difference

0˚

Note that in the circuit of Figure 13-5, the signal could be taken from either side of RS1, but by taking it from the bottom as shown, there is almost no dc offset on the output.

9.

With a 10 k load, the signal level drops to 1.74 Vpp (measured). When the signal was increased, the output was observed to have a 20 Vpp signal with no clipping (the limit of the signal generator).

114

Evaluation and Review Questions 1.

(a) The input impedance is higher. (b) For comparable circuits, the gain is less with a CD amplifier than a CE amplifier.

2.

The CS amplifier has voltage gain and a phase shift between the input and output whereas the CD amplifier does not. Both have high input impedance and both provide power gain.

3.

There would be no affect on the dc parameters but the voltage gain would drop sharply.

4.

(a) No (b) Yes (c) Advantage: stable, predictable bias. Disadvantage: two transistors.

(Note that the output signal is linear unless it driven above approximately 5 Vpp. Clipping is observed at approximately 10 Vpp on the output).

5.

(a) With the resistors equal, the dc offset is approximately zero. Note that the circuit works with a wide range of resistors in place of RS1, including no resistance, but the dc offset is affected. (b) The gain is improved because the current source is a very high ac resistance. (c) The input impedance is approximately equal to the gate resistance of 1.0 M.

The output impedance is can be estimated from the loading effect observed in step 9.

From the measured values, the output impedance is approximately 1.5 k.

For Further Investigation

Initially the potentiometer is adjusted to set the output voltage to the input voltage when the input is a dc level. With matching transistors and proper setting of the potentiometer, the output will track the input within a few millivolts over the 3 V to +3 V range specified. Students can graph the transfer curve to show this relationship.

115

Experiment 14: JFET Applications Procedure

RG

Listed Value 1.0 M

Measured Value 1.0 MΩ

Table 14-2 DC Parameter VB

RS

2.7 k

2.68 kΩ

VE

4.18 V

R1

56 k

55.8 kΩ

IE

1.00 mA

R2

27 k

26.8 kΩ

VC

9.90 V

9.98 V

RE1

180 

180 Ω

VCE

5.69 V

5.85 V

RE2

3.9 k

3.88 kΩ

RC

5.1 k

5.04 kΩ

Table 14-1 Resistor

Table 14-3 AC Parameter Vb

Computed Value 225 mV

Measured Value 228 mV

re Av(Q1)

24.5 Ω 0.75

0.76

Av(Q2)

24.8

20.4

Av

18.6

15.5

Computed Value 4.88 V

Measured Value 4.74 V 4.12 V

Table 14-4 Overall Gain Av(MIN)

Measured Value 0.94

Av(MAX)

12.0

4. The current is IDSS. Measured results were 6.1 mA at VDD = +15 V; 5.74 mA at VDD = +5.0 V. 5.

6. +5 V

+5 V

Vin

Vin 5 V

5 V

+1.5 V

+4.0 V

Vout

Vout

1.5 V

0.7 V Horiz = 0.2 s/div

Horiz = 0.2 s/div

Plot 14-1

Plot 14-2

Note: The output voltage levels are dependent on the IDSS of the transistors used.

Rise time of the output in Plot 15-2 is also dependent on the internal generator resistance.

116

Evaluation and Review Questions 1.

The circuit has the high input impedance from the JFET and high gain from the BJT.

2.

The Q-point for Q3 is at the origin of the VDS verses ID curve. This means that it is operating in the ohmic region.

3.

One way is to add a self-bias resistor. (The value should be slightly smaller than VGS(off) / IDSS.)

4.

(a) The rate of change is approximately equal to 60 V/ms. (Measured = 3.0 V in 50 µs). (b) i = 0.1 µF x 60 V/ms = 6.0 ma.

5.

Q2 acts as a switch and Q2 acts as a current source. When the input signal is positive, the gate source of Q2 is forward biased, causing it to discharge the capacitor. When the input signal is negative, the gate source of Q2 is reverse-biased, causing it to be cutoff. The negative voltage on the drain-source of Q1 causes it to source IDSS, thus charging the capacitor with a constant current when Q2 is off.

For Further Investigation Parameters for the cascode amplifier are as follows: DC parameters: Calculated Measured VB 4.88 V 4.82 V VE 4.18 V 4.21 V VS 2.25 V ID 0.83 mA AC parameters: re‘ AV

Calculated 30 Ω -

Measured 6.6

117

Experiment 15: Multistage Amplifiers Procedure Table 15-1 Resistor RA

Listed Value 100 k

Measured Value 100 kΩ

RB

2.0 k

1.98 kΩ

R1

330 k

322 kΩ

R2

330 k

321 kΩ

RE1

33 k

32.5 kΩ

RE2

1.0 k

1.00 kΩ

RC1

22 k

21.8 kΩ

R3

47 k

46.7 kΩ

R4

22 k

21.6 kΩ

RE3

4.7 k

4.68 kΩ

RE4

220 

219 Ω

RC2

6.8 k

6.71 kΩ

RL

10 k

10.0 kΩ

Table 15-3 AC Parameter re’(Q1) Av(nl)(Q1) Av(nl)(Q2)

28.0*

Rout(Q1)

21.8 k

Rin(Q2)

VB(Q1) VE(Q1) IE(Q1) VC(Q1) VCE(Q1) VB(Q2) VE(Q2) IE(Q2) VC(Q2) VCE(Q2)

Computed Value 0.0 V

Measured Value 0.46 V

0.70 V

1.10 V

0.43 mA

5.69 V 6.39 V 5.43 V 6.13 V

6.02 V 7.12 V 5.83 V 6.39 V

1.80 mA 2.74 V

3.31 V

8.87 V

9.70 V

Computed Value 78*

Measured Value 82

63.8 k

68.6 kΩ 6.71 kΩ

Vin(Q1)

6.71 k 10 mV

Vout(Q2)

780 mVpp

820 mVpp

Table 15-4 AC Parameter Av Rin(Q1)

Computed Value 58.1  13.9  20.4*

re’(Q2)

Table 15-2 DC Parameter

Rout(Q2)

* calculated with 10 k load resistor.

AV= 20.4 x (9.1 k/39.9 k) x 28.0 x (10 k/16.7 k) = 78

9.1 k

Evaluation and Review Questions 1.

The input and output impedances are ac quantities. The input impedance is determined, in part, by re’, a quantity that cannot be measured directly.

2.

Capacitors can be considered “shorts” to ac for frequencies for which the reactance is small compared to the circuit impedance.

3.

Looking back from the load resistor, the circuit can be considered to be a current source (the transistor) in parallel with the collector resistor. Assuming the current source is an open, the ac and dc resistances are equivalent and are represented by the collector resistor.

118

4.

(a) Base bias is formed by removing R4 and increasing the value of R3 (the base resistor).

To find the appropriate value, divide the emitter current (1.80 mA) by ß; this is the desired base current and current in R3. Find the resistance value by dividing the desired voltage across it (20.4 V) by the base current. For ß = 100, the computed base resistor is 1.1 M. (b) The disadvantage of this is that the amplifier would be sensitive to the ß of the particular transistor that is used.

5.

Both stages are CE amplifiers; therefore they each change the phase by 180˚. The result is that there is no phase shift to the output.

For Further Investigation Table 15-5 Generator Setting 0.5 V

Vin*

Vout

Av

10 mV

2.8 V

280

1.0 V

20 mV

5.4 V

270

2.0 V

40 mV

9.1 V

220

4.0 V

80 mV

12.0 V

150

6.0 V

120 mV

12.8 V

107

8.0 V

160 mV

13.2 V

82.5

10.0 V

200 mV

13.2 V

66

20.0 V

400 mV

12.0 V

36

400

300

Av

200

100

0

*Vin should be 2% of the generator setting. All voltages shown are peak-to-peak values. Some distortion is observed on the output for Vin = 20 V.

0

100

200

Vin (mV pp)

Plot 15-1

119

300

400

Experiment 16: Class A Power Amplifiers Procedure Table 16-1 Resistor Listed Value R1 56 k R2 10 k

Table 16-2 Parameters for CE Amp(Q1)

Computed Value

VB

Measured Value 55.7 kΩ 9.9 kΩ

RE1

100 

99 Ω

RE2

560 

548 Ω

RC

4.7 k

4.7 kΩ

R3

10 k

9.9 kΩ

R4

22 k

21.9 kΩ

RE3

22 

23 Ω

Measured Value

Table 16-3 Parameters for CC Amp(Q2,3)

Computed Value

Measured Value

1.82 V

1.70 V

VB

8.25 V

8.05 V

VE

1.12 V

1.05 V

VE

6.85 V

6.75 V

IE

1.73 mA

IE

311 mA

VC

3.96 V

4.52 V

VC

12.0 V

12.0 V

VCE

2.84 V

3.45 V

VCE

5.15 V

5.25 V



0.08 Ω 0.99

0.98

0.98

0.96



re Av(NL)

14.5 Ω 41

39

re Av(NL)

Av(L)

25

24

Av(L)

Table 16-4 Quantity

Value

Load impedance, RL

8Ω

Input impedance, Rin

8.5 kΩ

Output rms voltage, Vout

1.24 Vrms

Input rms voltage, Vin

0.071 Vrms

Load power, PL

192 mW

Input power, Pin

0.593 µW

Power gain, Ap

323,000

120

Table 16-5 Trouble

Effect on Circuit

RE1 switched with RE2

reduced voltage gain by approximately a factor of 5.

RC open

Q1 cutoff. No output signal.

C3 = 10 µF

no effect

VCC = 6 V

output clips at a lower point; dc conditions change.

R4 open

Q3 dc base voltage rises; output ac signal clips earlier.

C4 = 10 µF

no effect at 1.0 kHz;(affects lower cutoff frequency).

Q2 has open collector

much less power gain.

Evaluation and Review Questions 1.

The Darlington arrangement provides an extremely high ß; hence the loading on the first stage is minimal, allowing the voltage gain of the first stage to be unaffected by the power amplifier.

2.

The loaded gain is lower because ac collector resistance is much lower with load connected.

3.

(a) From Table 16-2 and 16-3, the quiescent emitter current (for all transistors) is approximately 313 mA (Bias resistors can be ignored). The quiescent power for the amplifier is the product of this current and the supply voltage (12 V) for a quiescent power dissipation of 3.75 W. (b) Power dissipated in Q3 is ICQ3 x VCEQ3. This is 311 mA x 5.25 V = 1.6 W.

4.

(a) As given in Table 16-3, the VCEQ of Q3 is approximately 5.25 V (b) ICQ is 311 mA.

5.

Reverse R1 and R2. Install the PNP transistor with the emitter toward the positive supply and the collector toward ground. Resistors and capacitors from the original emitter and collector circuits are put in the new emitter and collector circuits respectively. Take the output from the collector.

For Further Investigation Answers vary. A CB amplifier, with its low input impedance, offers no advantage (here) over a CE amplifier but should give the student practice in solving a design problem. To keep re’ large, a small emitter current was selected for the test circuit. The test circuit worked well with a low impedance microphone input. Bypass capacitors on the protoboard help avoid noise. Also, note polarity of C7.

121

Experiment 17: Class B Push-Pull Amplifiers Procedure Table 17-1 Resistor Listed Value RL 330  R1 10 k

Measured Value 351 Ω

Vin Vout

9.92 kΩ

R2

10 k

9.90 kΩ

R3

68 k

67.4 kΩ

R4

2.7 k

2.68 kΩ

Horiz = 0.1 ms/div Vertical = 5 V/div

Plot 17-1

Table 17-2 DC Parameter VE

Computed Value 0V

Measured Value 0V

VB1

0.7 V

0.60 V

VB2

0.7 V

0.63 V

IR1 = ICQ

830 µA

Table 17-3 AC Parameter Vp(out) Ip(out) P(out)

Computed Value 7.5 Vp*

Measured Value 7.2 V

23.1 mAp 86.5 mW

* allowing 1.5 V for bias current in R1

Table 17-4 DC Computed Measured Parameter Value Value VB3 6.11 V 6.15 V VE3 6.81 V 6.78 V ICQ3

Table 17-5 AC Parameter Av

Computed Value 3.21

Measured Value 3.14

811 µA

Evaluation and Review Questions 1.

I = 0.83 mA + 0.83 mA = 1.66 mA.

2.

Open D2, bad Q2, no 9 V voltage.

3.

(a) Crossover distortion.

4.

Bypass R4.

5.

Range is from -5.75 to 6.70 V.

V = 18 V. P = IV = 30 mW.

(b) Half the signal will be missing.

For Further Investigation For best results, the transistors should to be matched and at the same temperature. For the circuit in Figure 17-5(a), the current in RB is approximately 953 µA (measured = 954 µA). Ideally, this current is mirrored into Q1, producing a 9.53 V drop across RC. Because it is not easy to thermally match separate transistors, the voltage across RC depends on temperature differences between the two transistors – if Q1 is warmed (touching it will do it!), the voltage across RC drops and viceversa.

122

Experiment 18 The Differential Amplifier Procedure:

RB1

Listed Value 100 k

Measured Value 102 k

Table 18-2 DC Parameter VA

Computed Value –1 V

RB2

100 k

102 k

IT

1.4 mA

RE1

100 

99 

IE1 = IE2

0.7 mA

RE2

100 

100 

VC(Q1)

+15.0 V

+15.0 V

RT

10 k

10.2 k

VC(Q2)

+8.0 V

+8.35 V

RC2

10 k

10.3 k

Table 18-1 Resistor

Table 18-3 AC Parameter Vb(Q1)

Computed Value 100 mVpp

Measured Value 100 mVpp

VA

50 mVpp

50 mVpp

re(Q1) = re(Q2)

35.7 

Av(d)

36.8

35.5

Vc(Q2)

3.68 Vpp

3.55 Vpp

Rin(tot)

35.1 k

36.5 k

Av(cm)

0.5

0.44

CMRR

37.3

38.1

Measured Value 1.1 V

Evaluation and Review Questions 1.

IC is controled by IB, which is unaffected by the collector resistor.

2.

It assures that the measurement is made when the amplifier is operating in its linear region.

3.

(a) C2 affects the gain; if it is open, the gain drops significantly. (b) RE1 has a small effect on the dc. A short will increase the gain but decrease stability. (c) Collector currents will be imbalanced, resulting in lower CMRR. (d) Reduced emitter current in both transistors, Q2’s collector voltage will rise and cutoff clipping occurs at a lower voltage. (e) The dc collector current in Q2 rises, the Q2 collector voltage drops and saturation clipping occurs with a smaller input signal.

4.

The input and output signals are in phase.

5.

Balance the transistors (same betas and bias resistors) ass current source biasing.

For Further Investigation The CMRR rises significantly – the observed CM output was 5 mVpp for a 7.7 Vpp commonmode input, which implies a CMRR of 95 dB. This result is better than expected based on previous tests. Student results will likely be less.

123

Experiment 19: Op-Amp Characteristics Procedure Resistors: Rf = 1.01 M, Ri = 10.2 k, RC(1) = 10.2 k, R1 = 102 k, R2 = 102 k, RA = 102 , RB = 101 , RC(2) = 102 k, RD = 102 k.

Table 19-1 Specified Value Measured Minimum Typical Maximum Value

Step

Parameter

2d

Input Offset Voltage, VOS

2.0 mV

6.0 mV

0.66 mV

3d

Input Bias Current, IBIAS

80 nA

500 nA

98 nA

3e

Input Offset Current, IOS

20 nA

200 nA

1 nA

4b

Differential Gain, Av(d)

1000

4c

Common-Mode Gain, Acm

0.032

4d

CMRR

5

Slew Rate

70 dB

90 dB

89.9 dB

0.5 V/µs

0.8 V/µs

Evaluation and Review Questions 1.

(+) means non-inverting input. () means inverting input.

2.

The dc voltage that is applied between the op-amp's inputs to produce zero volts output.

3.

The input bias current is the average of the input currents; the input offset current is the difference between the input currents when the output voltage is 0 V.

4.

(a) Differential gain is the amplification of the voltage between the inputs of the op-amp.

Common-mode gain is the amplification of the voltage present at both inputs of the op-amp. (b) The 741C was connected as a high-gain differential amplifier. One at a time, differential and common-mode input signals were applied to the inputs and the gain measured for each.

The ratio of the differential gain to the common-mode gain was calculated and then converted to dB. (c) The advantage is the rejection of common-mode signals; these are undesired and frequently represent cross-talk, or other form of interference.

5.

A fast slew rate means the output can change rapidly; it is related to the frequency response of the op-amp.

For Further Investigation A 10 Vpp signal was applied to the input. A 9.9  load resistor causes the output voltage to drop to 450 mVpp (225 mV for positive and negative excursions). The current in this case is 225 mV/9.9  = 22.7 mA (measured result). The specified current limit is 25 mA (typical). The smallest resistor that could be used with the observed current is 5 Vp/22.7 mA = 220 . A test with this value shows no discernible difference between the input and output signals. Resistors smaller than 220  show the effect of current limiting.

124

Experiment 20: Linear Op-Amp Circuits Procedure Table 20-1 Rf

Ri

Vin

Measured

Measured

Measured

10.2 kΩ

1.02 kΩ 500 mVpp

Vout

Acl(NI)

Computed

11

5.5 Vpp

Acl(I)

Computed

10

5.0 Vpp

Measured

(pin 6)

Computed

V(-)

Measured (pin 2)

Rin

Measured

5.5 Vpp

500mVpp 5 MΩ

Measured

Measured

Table 20-2 Rf

Ri

Vin

Measured

Measured

10.2 kΩ

1.02 kΩ 500 mVpp

3.

Measured

Computed

V(-)

Rin

(pin 6)

(pin 2)

Measured

4.95 Vpp

0 Vpp

1.0 kΩ

The circuit is shown below. The measured closed-loop gain was 47 with a 100 mVpp input.

Rf 470 k  +15 V

Ri 10 k 

2 3

+

 7 1.0 µF 6

741C

+

Vout

The output becomes slew rate limited when the input frequency is above 10 kHz. With 100 mVpp input, fMAX was approximately 40 kHz. With 500 mVpp input, fMAX was approximately 10 kHz. For a slew rate, S, at a frequency, f, the output is limited to Vout(pp) ≤ S/πf.

+

Vin

Vout

4

1.0 µF

15 V

Evaluation and Review Questions 1.

Amplifier 1 gain = 20 log (11) = 20.8 dB Amplifier 2 gain = 20 log (10) = 20.0 dB

2.

The voltage on the inverting terminal is not close to ground; it is nearly the same as the input voltage.

3.

(a) Acl(NI) = 2 (b) Acl(I) = 1

4.

(a) Unity gain (b) Voltage-follower

5.

A square wave due to the amplifier operating with open-loop gain

For Further Investigation The ohmmeter accuracy depends on the standard resistor, meter used and the op-amp. The test circuit readings were within 3% of a lab DMM.

125

Experiment 21: Op-Amp Frequency Response Procedure Table 21-1 Step Resistor 4

Ri-1

Listed Value 2.0 k

Measured Value 1.98 kΩ

4

Rf-1

18 k

17.76 kΩ

5

Ri-2

1.0 k

1.003 kΩ

5

Rf-2

100 k

100.9 kΩ

Table 21-2 Data for Noninverting Amplifiers Computed Measured Closed-loop Bandwidth Step Gain Gain Computed Measured 3 1.0 1.0 1.31 MHz 4 10 9.95 131 kHz 138 kHz 5

101

100

13.1 kHz

12.9 kHz

Table 21-3

Ri-3

Listed Value 1.0 k

Measured Value 1.003 kΩ

7

Rf-3

1.0 k

1.007 kΩ

8

Rf-4

10 k

10.00 kΩ

9

Rf-5

100 k

101.2 kΩ

Step

Resistor

7

Table 21-4 Data for Inverting Amplifiers Computed Measured Closed-loop Bandwidth Step Gain Gain Computed* Measured 7 655 kHz 568 kHz 1.0 1.0 8 9

10 100

9.95 100

119 kHz

89 kHz

13 kHz

9.7 kHz

*computed values are based on the measured unity-gain frequency of 1.31 MHz.

Evaluation and Review Questions 1.

(a) The gain-bandwidth product was constant to within 5%. (b) Yes.

2.

(a) The gain-bandwidth product is not constant, especially for low gain amplifiers. (b) No. (Note: Noise gain is defined as 1/ß. It is the gain that results if the non-inverting terminal is driven. Using the noise gain, the gain-bandwidth product is a constant.)

3.

The response should be observed at a frequency at least a factor of ten below the predicted cutoff frequency.

126

4.

(a) The rise time is inversely proportional to the bandwidth. The relationship is TCL = 0.35 B CL

(b) Slew rate.

5.

Since the bandwidth drops off at higher gain, the overall frequency response can be increased by using two lower gain (but equivalent) amplifiers. The disadvantage is more hardware and added noise.

For Further Investigation Signal should be applied to the inverting input of the amplifier. The gain is determined by only Rf and Ri, so is 100. However, the feedback fraction is smaller due to the presence of RC, therefore the bandwidth is smaller also (as given in Equation 21-1). The measured bandwidth for the amplifier is 1.02 kHz. A low bandwidth is desirable if the bandwidth of the signal is low (such as from a temperature transducer). This reduces the noise and increases the signal-to-noise ratio.

127

Experiment 22: Comparators and the Schmitt Trigger Procedure +15 V

Vin

7 1.0 µF

+

6

741C

Vs =

3.0 V pp 50 Hz

3

2 

+15 V

Vout

4 1.0 µF

VREF

10 k 

Vin

0V 3.0 Vpp

Vout

15 V

0V 28 Vpp

15 V

Horiz =5.0 ms/div

Plot 22-1 Comparator waveform 2.

Varying the potentiometer changes the duty cycle of the output from 0 to 100%.

0V

0V

X = 1 V/div Y = 10 V/div

X = 1 V/div Y = 10 V/div

0V

0V

The vertical line moves along the x-axis as the potentiometer is varied.

Plot 22-2 Comparator transfer curve

Plot 22-3 Comparator transfer curve (inputs reversed)

4.

Varying the potentiometer causes the vertical line along the x-axis.

6/7. When the potentiometer is set to maximum, the output is in positive saturation. As the potentiometer is varied (less resistance), the output waveform suddenly becomes a 50% duty cycle. Reducing the resistance more causes the output waveform to shift to the left.

Note that the positive threshold is different than the negative threshold. +15 V

Vin Vs

3.0 V pp 50 Hz

10 k 

2 3



Vin

7 1.0 µF

741C

6

0V 3.0 Vpp

Vout

+ 4

1.0 µF

Vout

15 V

0V 28 Vpp

R1 100 k 

Horiz =5.0 ms/div

Plot 22-4 Schmitt trigger waveform

128

8.

The potentiometer varies the hysteresis; the upper and lower thresholds move apart as resistance is increased.

0V

X = 1 V/div Y = 10 V/div 0V

Plot 26-5 Schmitt trigger transfer curve

Evaluation and Review Questions 1.

The threshold voltage is a dc quantity that adds to or subtracts from the input plotted along the x-axis of the transfer curve. Varying the threshold shifts the vertical line along the x-axis.

2.

The offset control on the generator does not affect the threshold for the circuit but it adds a dc component to the input voltage. As a result, the duty cycle of the output waveform can be changed by the offset control. (Note: it is useful to show this with the transfer curve – it varies only the endpoints of the transfer curve, not the vertical line).

3.

The transfer curve is a characteristic that is independent of the input, however, the plot of the transfer curve on an oscilloscope will have various intensities that depend on the input because the waveform determines the time the beam spends in graphing any given point on the curve.

4.

A comparator has the same threshold for rising or falling signals; a Schmitt trigger has a different threshold for each.

5.

Setting up a voltage divider: Rx Rx  100 k

 26 V  100 mV

Rx = 383 

For Further Investigation When the potentiometer = maximum resistance, the output is a 28 Vpp square wave at a frequency of 270 Hz. Pin 2 shows a rising and falling exponential waveform, 2.5 Vpp. As R is reduced, the output frequency increases and slew rate limiting is observed. With very careful adjustment, the output waveform reaches a maximum frequency of approximately 4.5 kHz and can be adjusted to appear sinusoidal (the waveform on pin 2 also appears to be a sine wave). At this point, the measured resistance is about 47  – a fixed resistor can be substituted to give a more stable view.

129

Experiment 23: Summing Amplifiers Procedure Table 23-1 Listed Resistor Value RA 20 k RB 10 k

Measured Value 20.0 kΩ 10.1 kΩ

RC

5.1 k

5.08 kΩ

Rf

3.9 k

3.93 kΩ

QA

0V

QB

QC 4.4 V Horiz = 1 ms/div Vertical = 1.0 V/div

Horiz = 1 ms/div Vertical = 5.0 V/div

Plot 23-1

Plot 23-2

4.

The output waveform is the positive portion of the input waveform with no offset. The small jump on the output is due to slew rate limitation as the output moves from negative saturation.

5.

Observations: The output is a negative half-wave rectified signal. With D1 removed, the output appears to be a full-wave rectified signal with overshoot on the back side of every other pulse. This overshoot is frequency dependent, and disappears at a few hundred hertz.

6.

The output is a positive full-wave rectified signal. The signals are shown in Plot 23-3.

Input R i2 Input R i3

Horiz = 2 ms/div Vertical = 5.0 V/div

Vout

Plot 23-3

130

Evaluation and Review Questions 1.

(a) To approximate the column values in the binary system (1, 2, 4, etc.), the three inputs are amplified in proportion to the column values they represent. (This is in effect a three-bit D/A converter). (b) Add an inverting amplifier to the output.

2.

Gains are 0.195, 0.39, and 0.76. The output is 4.5 V x (0.195 0.39 0.76) = 6.05 V

3.

One of the inputs to the summing amplifier is a variable dc as shown: Rf

R1 Vs

R2

+15 V

 +

VREF

10 k 

Vout

15 V

4.

The inverted half-wave rectified signal is amplified twice as much as the sine wave input in order to cancel the negative excursion of the sine-wave and add a positive going signal to it.

5.

The resistors shown are representative and can have other values; the ratios are important.

R1

Rf

10 k 

30 k 

R2 15 k



Vout

+

For Further Investigation The generator was set to a frequency of 100 Hz with an amplitude of 300 mVpp. The measured notch frequency was 1.15 kHz at 50 mVpp.

131

Experiment 24: The Integrator and Differentiator Procedure Table 24-1 VOUT Red ON Green ON +2.1 V 2.0 V

VREF Threshold 0.001 V

VA

0V

VB

0V

Horiz = 0.5 ms/div Vertical = 2.0 V/div

Plot 24-1 3. Duty cycle changes as R3 is varied. Output B slope changes to follow Table 24-2 Trouble

Symptoms

No Negative Power Supply

Red LED on; B goes to positive saturation

Red LED open

A = -2 V to + sat; B = - sat w/small deviation

C1 open

B goes to a square wave (+ and - saturation)

R4 open

No change in A; B goes toward - saturation.

VB

VB

Vout

Vout

0V

0V

0V

0V

Horiz = 0.5 ms/div Vertical = 2.0 V/div

Horiz = 0.5 ms/div Vertical = 2.0 V/div

Plot 24-2

Plot 24-3

Evaluation and Review Questions 1.

Vref(min) = 714 mV

2.

The LEDs drop a maximum of about 2.0 V at the op-amp's current limit.

Vref(max) = +714 mV

132

3.

(a) R4 establishes a virtual ground at the inverting input through negative feedback and stabilizes the operating point. Without it, the output will saturate. (b) The output went to negative saturation.

4.

Differentiator circuit

5.

Higher amplitude due to longer charging of the capacitor until clipping occurs on both the positive and negative peaks.

For Further Investigation The first op-amp is a relaxation oscillator with a measured frequency of 233 Hz. It has a square wave that goes between + and  saturation at its output (pin 6). The waveform on the capacitor is a fairly good triangle (no inversion) that goes from 1.5 V to +1.5 V. The output of the second comparator is a pulse waveform (peaks of pulses are centered on peak of triangle). The duty cycle of the pulse is adjustable with R4 and can be adjusted from not quite 0% to 100%.

133

Experiment 25: Low-Pass and High-Pass Active Filters Procedure Table 25-2 Measured Values A1 B1 A2 B2 8.17 kΩ 8.37 kΩ 8.00 kΩ 8.22 kΩ

CA1 to CB2

Listed Value 8.2 k 0.01 µF

Ri1

10 k

10.1 kΩ

Rf1

1.5 k

1.5 kΩ

Ri2

22 k

21.9 kΩ

Rf2

27 k

26.8 kΩ

Table 25-3 Frequency

VRL

500 Hz

2.55 V

1000 Hz

2.52 V

1500 Hz

2.45 V

2000 Hz

1.72 V

3000 Hz

0.45 V

4000 Hz

0.14 V

8000 Hz

0.009 V

RA1 to RB2

0.01 µF

0.01 µF

0.01 µF

0.01 µF

3.0

VRL (V)

Component

2.0 1.0 0.0 0

1.0

2.0

3.0

4.0

Frequency (kHz)

Plot 25-1 10

VRL (V)

1.0

0.1

0.01

10

5.0

100

1.0 k

10 k

Frequency (Hz)

Plot 25-2

134

6.0

7.0

8.0

Evaluation and Review Questions 1.

(a) The cutoff frequency is approximately 2.0 kHz. (b) Answers vary; for the tested circuit, the average R is 8.19 k, the average C is 0.010 µF. The computed cutoff frequency from these values is 1.94 kHz.

2.

(a) The measured voltage gain in the band pass is 2.55. (b) The desired value for a four-pole filter (from Table 25-1) is 2.574 (This is the product of the two gains: 1.152 x 2.235 = 2.574).

3.

The output is reduced by a factor of 104 (80 dB for this filter), which is approximately 250 µV.

4.

The constructed filter is very close to the theoretical roll-off.

5.

(a) The gain computed from the actual resistors in the first stage is 1.149. (b) The gain computed from the actual resistors in the second stage is 2.227. The product of these gains results in an overall gain of 2.559 (compare to question 2).

For Further Investigation The filter response is a high-pass filter with a cutoff frequency of 2.0 kHz and a roll-off of 80 dB/decade).

135

Experiment 26: State-Variable Band-Pass Filter Procedure Table 26-1 Component R1

Listed Value 10 k

Measured Value 10.0 kΩ

R2

10 k

10.1 kΩ

R3

10 k

9.91 kΩ

R4

1.0 k

1.01 kΩ

R5

100 k

101 kΩ

R6

1.0 k

1.00 kΩ

R7

1.0 k

1.02 kΩ

C1

0.1 F

0.0979 µF

C2

0.1 F

0.1006 µF

Table 26-2 Quantity

Computed

Measured

Center frequency, f0 =

1.59 kHz

1.62 kHz

Vpp(center) = Upper cutoff, fcu =

13.3 Vpp 1.649 kHz

Lower cutoff, fcl =

1.60 kHz

Bandwidth, BW =

0.047 kHz 0.049 kHz

Q=

33.7

32.4

Table 26-3 Frequency 100 Hz

Output voltage, Vpp 40 mVpp

200 Hz

75 mVpp

500 Hz

200 mVpp

1.0 kHz

0.48 Vpp

1.5 kHz*

3.0 Vpp

2.0 kHz

1.14 Vpp

*peak is at 1.6 kHz; 13.3 Vpp.

Table 26-3 (continued) Output Frequency voltage, Vpp 2.5 kHz 0.54 Vpp 3.0 kHz

0.37 Vpp

4.0 kHz

0.24 Vpp

5.0 kHz

180 mVpp

10 kHz

82 mVpp

20 kHz

41 mVpp Plot 26-1

6.

Gain is 1 for the high- and low-pass outputs although the response “peaks” at 1.6 kHz (13.3 Vpp). To eliminate the peaking, change R6 to 100 k.

136

Evaluation and Review Questions 1.

If the Q of the circuit is made smaller, the output can be increased.

2.

(a) Advantages: high Q, easily tuned, and both high- and low-pass outputs are available. (b) The change of R6 to 100 k, as noted in step 6, will eliminate the peaking, but greatly decreases the Q of the circuit so it affects the response of the band-pass filter.

3.

(a) To double the frequency, reduce R4 and R7 or reduce C1 and C2 by half. (b) To lower the Q, increase the value of R6.

4.

(a) A band reject or notch filter. b) Rejection of an interfering noise frequency.

5.

(a) Provide the x-axis signal that becomes the frequency base for the oscilloscope. (c) Change the internal voltage controlled oscillator of the swept frequency generator.

For Further Investigation The output of the band pass filter can be observed as a “bipolar” frequency based signal on the scope.

137

Experiment 27: The Wien-Bridge Oscillator Procedure 2.

The output saturates on both positive and negative peaks. Freeze spray causes circuit to change and even stop oscillating. Circuit is temperature sensitive.

Table 27-1 Table 27-2 Listed Measured fr Component Value Value Computed Measured (pin 6) R1 10.0 kΩ 10 k 1.59 kHz 1.46 kHz R2 10.0 kΩ 10 k C1

0.01 F

0.01 µF

C2

0.01 F

0.01 µF

Table 27-3 Vout(pp) (pin 6)

|

4.0 Vpp

Measured Voltages V(+)(pp) V(-)(pp) (pin 3)

|

1.5 Vpp

(pin 2)

|

VG

1.0 Vdc

1.5 Vpp

Table 27-4 Vout(pp) (pin 6)

4.6 Vpp

|

Measured Voltages V(+)(pp) V(-)(pp) (pin 3)

|

1.56 Vpp

(pin 2)

1.56 Vpp

|

VG

1.29 Vdc

5.

The phase shift between the output voltage and the feedback voltage is 0 degrees.

6.

Very little effect with freeze-spray. The output is much more stable.

Evaluation and Review Questions 1.

(a) Feedback fraction is very close to 1/3. (b) The measured result agrees with theory.

2.

The extra diode causes C3 to charge for a smaller part of the cycle decreasing VG. . This causes the FET resistance to drop (temporarily). The op-amp's gain (and output voltage) increase until the charge on C3 is returned to the proper level for a stable output.

3.

The diode causes the negative half-cycle of the output to charge the capacitor and bias the FET with a negative bias voltage.

4.

The frequency is halved to 790 Hz.

5.

Use a ganged resistor for R1 and R2 or a ganged capacitor for C1 and C2.

For Further Investigation The bulb will help stabilize the output. Some instability remains as can be demonstrated by touching the non-inverting input.

138

Experiment 28: The Colpitts and Hartley Oscillator Procedure Table 28-1 (continued) Listed Measured Resistor Value Value RE2 1.01 kΩ 1.0 k

Table 28-1

R1

Listed Value 10 k

Measured Value 9.98 kΩ

R2

3.3 k

3.31 kΩ

RE1

50  *

50 Ω

Resistor

Table 28-2 DC Parameter VB

Computed Value 3.01 V

Measured Value 2.97 V

VE

2.31 V

2.32 V

IE

2.18 mA

VC

6.11 V

6.07 V

Table 28-4 Colpitts Oscillator frequency

Computed Value 1.06 MHz

amplitude

RC Table 28-3 AC Parameter Vb

2.7 k

2.69 kΩ

Computed Value

Measured Value

100 mVpp 61.5 Ω

100 mVpp

43.9

39.0

Vc

4.39 Vpp

3.9 Vpp

Measured Value 1.04 MHz

Table 28-5 Hartley Oscillator frequency

Computed Value 969 kHz

Measured Value 961 kHz

7.4 Vpp

amplitude

re Av

5.

The measured frequency decreased to 781 kHz.

6.

Both the amplitude and the frequency of the oscillator decreased.

5.5 Vpp

Evaluation and Review Questions 1.

The amount of feedback decreased.

2.

The two conditions are positive feedback and a loop gain equal or greater than 1.

3.

Temperature change can cause a frequency drift in an oscillator.

4.

In the Hartley oscillator, an inductor is used to provide positive feedback from the tank circuit. In a Colpitts oscillator, a capacitor is used to supply positive feedback.

5.

(a) Gain will increase, so the output will increase and clip. (b) Feedback voltage will increase, output will increase and clip. (c) Gain will decrease, so oscillation may cease. (d) Output will decrease.

For Further Investigation The oscillator frequency measured for the test circuit was 990 kHz, with a varying amplitude. Freeze spray caused oscillations to cease. As the temperature rose, the circuit resumed oscillating.

139

Experiment 29: The 555 Timer Procedure Table 29-2

Table 29-1 Component R1

Measured Value 9.12 k

Listed Value 9.1 k

R2

10 k

Cext

0.01 F

10.0 k 9.6 nF

Quantity frequency

Computed Value 5.16 kHz

Measured Value 4.69 kHz

duty cycle

0.66

0.66

Step 4:

Plot 29-1 5.

The frequency increases (observed = 6.74 kHz) and the duty cycle changes to 0.52 to 12.5kHz, with only negative triggers on the output. There is a small dependency of frequency on the power supply voltage; with +5 V, the frequency drops to 6.25 kHz.

6.

Higher light intensity causes the resistance of the CdS to decrease, resulting in a higher frequency. With no diode, the frequency observed ion room light was 1.29 kHz. Covering the CdS cell resulted in a frequency of 49 Hz. With a bright flashlight shining on the cell, the frequency increased to 3.7 kHz.

Table 29-3 Quantity pulse width

Computed Value 10.6 ms

Measured Value 10.1 ms

V C(ext) 0V

Horiz =2.0 ms/div Vertical = 5 V/div

Vout 0V

Plot 29-2

140

Evaluation and Review Questions 1.

The value of R1 needs to be larger and R2 smaller. R1 will need to be increased by twice the amount of reduction to R2. For example if R2 is reduced to 5.1 k, then R1 should be a resistor that is near 2 x 4.9 k larger than 8.2 k, which is 18 k.

2.

The shape will remain the same, but the waveform will go between 5 V and 10 V (1/3 and 2/3 of VCC.)

3.

For any real value of R1, the fraction (R1+R2)/(R1+2R2) > 0.5.

4.

(a) The trigger points are 1/3 and 2/3 of VCC. The capacitor charges and discharges between these two levels. (b) It has no effect on the frequency because the frequency is determined solely by the time constants.

5.

a) The maximum output source or sink current is 200 mA but depends on the acceptable output voltage levels for high and low. (b) The high output voltage drops and the low output voltage rises.

For Further Investigation:

With R1A set to 0 , the output is as shown below. The measured frequency was 6.33 kHz.

The front side of the triangle waveform is controlled by R1A. As the resistance is increased, the front side of the triangle is longer; the back side is approximately the same (60 µs long) and the dc level increases. At a resistance setting of 50 k, the measured frequency was 1.82 kHz and the output appeared as shown below:

141

Experiment 30: The ZenerRegulator Procedure Table 30-1 Resistor

+10 mA

R1

Listed Value 220 Ω

Measured Value 219 Ω

R2

1.0 kΩ

1.00 kΩ

RL

2.2 kΩ

2.22 kΩ

0 mA

10 mA 10 V

Table 30-2 Vs Vout

(measured)

2.0 V 4.0 V 6.0 V 8.0 V 10.0 V 4.

IL

(computed)

VR1

(computed)

0V

Plot 30-1

+10 V

Is (computed)

IZ (computed)

1.82 V

0.82 mA

0.18 V

0.82 mA

0.0 mA

3.60 V

1.62 mA

0.40 V

1.81 mA

0.19 mA

4.70 V

2.12 mA

1.30 V

5.90 mA

3.78 mA

5.07 V

2.28 mA

2.93 V

13.3 mA

11.0 mA

5.24 V

2.26 mA

4.76 V

21.6 mA

19.3 mA

As shown in Table 30-2, zener current increases for increasing source voltage.

Table 30-3

RL

Vout

(measured)

1.0 kΩ 750 Ω 500 Ω 250 Ω 100 Ω *

IL

(computed)

VR1

(computed)

5.32 mA

6.68 V

30.4 mA

28.0 mA

5.31 V

7.08 mA

6.69 V

30.4 mA

28.0 mA

5.26 V

10.5 mA

6.72 V

30.5 mA

28.1 mA

5.08 V

20.3 mA

6.92 V

31.5 mA

29.2 mA

3.75 V

37.5 mA

8.25 V

37.5 mA

0.0 mA*

10

Voltage (V)

8 6 4 2 0

200

IZ (computed)

5.32 V

out of regulation with this load.

0

Is (computed)

400

600

800

1000

Resistance ( )

142

Experiment 31: Voltage Regulators Procedure Table 31-2 Parameter

Table 31-1

R1

Listed Value 2.7 k

Measured Value 2.69 kΩ

R2

330 

329 Ω

R3

1.0 k

1.00 kΩ

R4*

1.0 k

1.00 kΩ

R5

1.2 k

1.19 kΩ

RL

330 

328 Ω

Resistor

VOUT(min)

Computed Value 8.30 V

Measured Value 8.54 V

VOUT(max)

15.3 V

15.09 V

*potentiometer; record maximum resistance

Table 31-3

Table 31-4

VIN +18.0 V

VOUT (measured) +10.0 V

+17.0 V

9.94 V

+16.0 V

9.88 V

+15.0 V

9.82 V

Load regulation

0.4%

+14.0 V

9.75 V

Vripple(in)

700 mVpp

Vripple(out)

45 mVpp

Step 6

VNL

Measured Value 0.63% +10.0 V

VFL

9.96 V

Quantity Line regulation

7

8

Evaluation and Review Questions 1.

(a) 18 V  10 V  90 mA  720 mW c) I 2 =

18 V – 10.7 V = 22.1 mA. 330 

(b)

90 mA 100

 0.9 mA

I C = 22.1 mA – 0.9 mA = 21.2 mA

2.

(a) Bipolar transistors in parallel can have thermal runaway when one transistor conducts more causing it to heat up. The heat reduces VBE causing additional current and heating. (b) MOSFETS have a negative temperature characteristic; as temperature increases, channel transconductance decreases.

3.

Increase the size of C1. (A second 1000 µF capacitor in parallel with C1 halved the ripple).

4.

The power delivered to the load is 0.91 W. The efficiency is 45%.

5.

R6 needs to drop 0.7 V with a current of 200 mA. From Ohm’s law R6 = 3.5 

For Further Investigation Measured data for the regulator circuit is shown. The current that is programmed is 5.0 V/220  = 22.7 mA. It can be changed by changing the value of R1.

Data for Current Source Voltage I out 7.0 V 16.5 mA 8.0 V 21.5 mA 9.0 V 25.0 mA 10 V to 18 V 26.0 mA

144

Experiment 32: The Instrumentation Amplifier Procedure Table 32-1

R1

Listed Value 10 k

Measured Value 9.87 kΩ

R2

10 k

9.87 kΩ

RG

470 

463 Ω

R3

10 k

9.91 kΩ

R4

10 k

9.87 kΩ

R5

10 k

9.88 kΩ

R6

8.2 k

8.10 kΩ

R8

100 k

101 kΩ

R9

100 k

100 kΩ

Resistor

Table 32-2 Step 3

Parameter Differential Input Voltage, Vin(d)

Computed Value 300 mVpp

Differential Gain, Av(d)

43.5

Differential Output Voltage, Vout(d)

13.1 Vpp 10 Vpp

Common-mode Input Voltage, Vin(cm) 4

Common-mode Gain, Av(cm) Common-mode Output Voltage, Vout(cm)

5

CMRR

Measured Value 300 mVpp 43.0 13.0 Vpp 10.0 Vpp 0.008 80 mVpp 74.6 dB

Table 32-3 Measured Parameter Value Oscillator frequency 682 Hz Vout(pp) from oscillator 7.6 Vpp Vout(pp) from IA 170 mVpp 8.

The measured differential signal was a 170 mV, 682 Hz square wave (from the 555 timer). It was amplified by the IA but the 10 Vpp common-mode signal was almost completely eliminated from the output as viewed on an oscilloscope.

Evaluation and Review Questions 1.

Any noise that comes into the IA in differential-mode form cannot be eliminated from the output. This includes thermal noise, shot noise, or other noise from the source. It can also include any common-mode signal that has been converted to a differential signal.

145

2.

A CMRR of 130 dB means the ratio of the differential- to common-mode gain is 3.16 x 106.

This implies that the common-mode gain for the experiment is 43/3.16 x 106 = 13.6 x 10-6.

The expected output signal is 10 Vpp x 13.6 x 10-6 = 136 µVpp.

3.

The oscillator signal was differential mode signal but the signal generator was a commonmode signal.

4.

The reference ground for the 555 timer needs to be isolated from the reference ground for the IA. The simplest way to do this is power it from an independent source.

5.

Both inputs to the IA are balanced and have relatively high input impedance. (In the experiment, the input impedance was 100 kΩ, but it can be much higher).

For Further Investigation When RB was replaced with a CdS cell, the frequency varied from 520 Hz (dark) to 7.9 kHz (bright room light). An application is a digital light meter (or any other case where the intensity of light needs to be assigned a numeric value).

146

Experiment 33: Log and Antilog Amplifiers Procedure Table 33-1

R1

Listed Value 100 k

Measured Value 100 kΩ

R2

100 k

100 kΩ

Resistor

12

12

Vin

10 8

Vin(V)

Vin

10 8

Vin(V)

6

6

4

4

2

2

0

0

Vout is from 0.58 V to 0.51 V (both plots)

Horiz = 0.2 ms/div

Horiz = 0.2 ms/div

Plot 33-1

Plot 33-2

5.

Output from antilog amp matches input to log amp.

6.

When the log amp is warmed (by touch), the output goes down; when the antilog amp is warmed (by touch), the output increases. 0.4

Table 30-2 Data for Log Amp VIN VOUT -0.513 V

+2.0 V

-0.532 V

+4.0 V

-0.548 V

+6.0 V

-0.559 V

+8.0 V

-0.566 V

+10.0 V

-0.572 V

+12.0 V

-0.577 V

0.5

VOUT (V)

+1.0 V

0.45

0.55 0.6 0.65 0.7 1

2

147

3

4

VIN (V)

6

8

10 12

Evaluation and Review Questions 1.

Reasons given in the Summary of Theory include (a) less temperature sensitivity. (b) greater dynamic range (5 or 6 decades) (c) gain control.

Additional advantages to IC log amps are: (d) single package design (e) high accuracy and linearity and (f) very low bias current (typical = 5 pA in the LOG104).

2.

The antilog amp transfer curve is also a straight line plotted on semilog paper; however the input voltage should be plotted on the linear scale and the output voltage is plotted on the log scale.

3.

With the same resistor in the log and antilog circuit, the original signal applied to the log amp is restored by the antilog amp. If the antilog amp has a larger resistor, its transfer curve is shifted up, resulting in more gain.

4.

(a) Multiplication of the inputs (and multiplying by 1 because of the three inversions).

(Note the summing amplifier added the logs; the antilog amplifier returns the product of the original numbers but with opposite sign). (b) 6.0 V

5.

Remove one of the log amps and change the summing amplifier to one with a gain of 2.0

For Further Investigation The circuit returns the square root of the input voltage. The tested circuit was calibrated at an input voltage of 3.997 V and adjusted for an output of 1.990 V (reasonably close to the square root of 4.0 V). The measured data is shown in the Table. All measured values are within 1% of the expected square root.

Data for Further Investigation VIN VOUT Measured Expected +0.994 V 0.994 V 0.997 V +1.995 V

1.399 V

1.412 V

+3.997 V

1.990 V*

1.999 V*

+5.01 V

2.23 V

2.24 V

+9.05 V

3.004 V

3.008 V

+12.04 V

3.49 V

3.47 V

*calibration point

148

Experiment 34: IF Amplifiers Procedure Listed Value 56 k

Measured Value 56.1 kΩ

Table 34-2 DC Parameter VB

Computed Value 0.697 V

Measured Value 0.697 V

4.7 k 10 k 220  470  10 k

4.62 kΩ

VE

0.0 V*

0.0999 V

10.1 kΩ

IE

0 mA

222 Ω

VC

9.00 V

Table 34-1 Resistor R1 R2 R3 RE1 RE2 RL

VCE 9.00 V 8.99 V *assuming VE cannot be negative

467 Ω 10.1 kΩ

Measured Value 300 mVpp*

Table 34-4 AC Parameter fc

Measured Value* 455.8 kHz

Vc

8.0 mVpp**

fcu

461.4 kHz

Av

26.7

fcl

444.6 kHz

Vout(tot)

1.2 mVpp

BW

16.8 kHz

Q

27.1

Table 34-3 AC Parameter Vb

8.99 V

* Signal gen set to approx 500 mVpp ** Different transformers were tested. Results varied more than usual. Typical results shown.

*frequency counter suggested for frequency measurements

Evaluation and Review Questions 1.

Adding a second probe doubles the loading effect. If probe loading is not a problem, no effect will be observed when the second probe is connected to the circuit.

2.

In experiment 8, the frequencies bypassed were audio, requiring a large C to keep reactance low. With the higher frequencies in the IF amp, a small capacitor can achieve the same result.

3.

The resonant circuit has highest reactance at resonance; thus, amplifier gain is also highest here.

4.

The voltage across Rin is 3X larger than that dropped across R3, hence Rin = 3 X 10 k = 30 k.

5.

Answers (a) and (e) could account for 0 V on the collector.

For Further Investigation Representative data for various loads is shown. Notice that BW, and Q are affected by different loads.

AC Parameter fc

2.0 kload 1.0 kload 270 load

100 load

456 kHz

457 kHz

456 kHz

455 kHz

fcu

473 kHz

478 kHz

496 kHz

554 kHz

fcl

441 kHz

436 kHz

415 kHz

371 kHz

BW

32 kHz

42 kHz

81 kHz

183 kHz

Q

14.3

10.9

5.63

2.70

149

Experiment 35: The ADC0804 Analog-to-Digital Converter Procedure: Table 35 -1 Digital number 0000 0001 0000 0010 0000 0011 0000 0100

Ideal threshold 10 mV 30 mV 50 mV 70 mV

Measured threshold 15.1 mV* 35.1 mV 54.6 mV* 75.6 mV*

*These readings are sensitive to the position of ground on the protoboard. All are about 5 mV higher than ideal.

Table 35 -2 Input voltage 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V

Plot 35 -1

Binary output 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0001*

*Ideally, this should be 1000 0000

8. Set the ADJ leg on the LM335 for 25o C (approximately room temperature). VADJ = 1.30 V to set output.

Holding the LM335 between the fingers, the temperature increased to 29o C as read by the digital thermometer. Freeze spray quickly lowered the temperature to 0oC.

Evaluation and Review Questions 1. 0010 1000 (This represents 640 mV + 160 mV = 800 mV).

2. The binary output 1010 0000 represents 3.20 V (2.56 V + 0.64 V) at the input.

3. The Vref/2 input is the reference voltage for the span and represents ½ the span. With 1.28 V applied, the steps are (2 X 1.28 V)/256 steps = 10 mV/step.

4. An output of 1111 1111 represents 2.55 V at the input. (255 steps X 10 mV/step = 2.55 V). This represents 255o C. 5. The

line is the input that controls the start of the conversion process.

For Further Investigation To convert the LM335 to read Fahrenheit temperatures, the following adjustments are needed: Keep R5 set as it was since it was set to room temperature in step 8. The LM335 produces 10 mV/oC, which is 5.55mV/oF (5/9 X 10 mV). At 0o F. the Kelvin temperature is 255 K. Since this produces 2550 mV, set R2 for 2.55 V. R4 is set for 1.422 V, which represents 256 steps X 5.55 mV/step. The output will be a binary number that represents the temperature in oF.

150

Experiment 36: Transducers Procedure: Table 36 -1 Quantity PC board size

Measured Value 7” X 8”

Note: Plate size is not critical but smaller plates will have a nonlinear response and will produce a higher frequency.

Table 36-2 Number of pages none

Measured Frequency 1524 Hz

20

3166 Hz

40

4508 Hz

60

5609 Hz

80

6580 Hz

100

7400 Hz

Plot 36-1 6.

Answers will vary; typically students can estimate to within 2 or 3 pages.

Evaluation and Review Questions 1. This would increase the capacitance and make the sensor more sensitive to changes in spacing.

2. (a) Variation of plate placement and spacing, frequency measurement, and interpolation of data. (b) Resolution is a measure of the ability to detect differences. A smaller plate area (or misaligned plates) implies a smaller capacitance. It is more difficult to detect a change when the capacitance is small.

3. Noise problems and added capacitance of cables.

4. A frequency counter (operated in frequency mode) needs many cycles to determine the frequency with a given resolution. (For example, 100 cycles need to be counted to measure the frequency to within 1%.)

During the counting time, the frequency should not change. This limits the speed at which the transducer can operate.

5. Answers will vary. One possibility is to use a look-up table in a computer and use the table to interpolate the given frequency and convert it to a number of pages.

For Further Investigation Results from this investigation indicated that the pc boards with paper dielectric do not make a good scale. As weight is added to the plates, the paper initially compresses and the frequency lowers slightly, but the paper responds to the pressure and the frequency moves back toward the initial value. There was less than a 1% change with a 5 kg load. Experimenting with different dielectrics produced similar results, however student results may vary.

151

Experiment 37: Measuring Rotational Speed Procedure: A Singer 12 V motor was tested: Table 37-1 Motor Measured Motor Voltage Frequency rpm 20% 33 Hz 1980 40%

71.5 Hz

4290

60%

109.6 Hz

6576

80%

147.5 Hz

8850

100%

184.5 Hz

11,070

Plot 37-1

Evaluation and Review Questions 1. An optical system will not “load” the motor and change its speed.

2. The light output of an LED is not uniform. The sensor should be placed to receive maximum light from the LED. 3. Although bias is sometimes used, it is not required for a phototransistor because the light itself creates electron-hole pairs at the junction, providing base current.

4. 4000 rpm = 66.7 rpm. Because there is one slot, the frequency will be 66.7 Hz. 5. The tachometer is basically a small generator mechanically linked to the device to be measured. A voltage is induced in a coil as it rotates in a constant magnetic field, producing a voltage or frequency that is proportional to the speed of rotation. Unlike a traditional tachometer, the light detector in this experiment has no mechanical linkage to the device being measured. It can be configured as a tachometer by connecting the output to a frequency counter.

For Further Investigation A square wave from 0 to 4 V was connected through a series 10 k resistor to the base of the MRD300 in place of the LED light source (see Figure 37-4). The collector resistor was 68 k and the supply was set to +15 V. The transistor alternately cutoff (HIGH) and saturated (LOW) with this input with a very slight reduction of the cutoff peaks when a bright LED was shined on the phototransistor. Interestingly, if the function generator is reduced to about 3 V, the positive (cutoff) peaks of the output were reduce when light is added; a red LED can be used to control the amplitude of the output by saturating the transistor.

152

Experiment 38: The SCR Procedure: Table 38-2

Table 38-1

R1

Listed Value 1.0 k

Measured Value 993 Ω

Parameter VAK(off state)

Transistor Latch 13.5 V

SCR 13.5 V

R3

160 

161 Ω

VAK(on state)

0.803 V

0.769 V

R4

1.0 k

1.001 kΩ

VGate trigger

0.768 V

0.736 V

R5

10 k

9.94 kΩ

VR4

3.42 V

3.83 V

IH(min)

3.42 mA

3.83 mA

Resistor

7.

S1 turns on the SCR. S2 turns it off.

Plot 38-1

Evaluation and Review Questions 1.

Lower anode voltage so that the current drops below the holding current.

2.

Commutation refers to the process of interrupting anode current or "opening" a solid-state switch.

3.

A short to the anode removes the load resistance for the power supply. The power supply's short-circuit current may be higher than the SCR's peak current.

4.

The LED is on all the time and S2 would not be able to turn it off.

5.

The voltage across R4 is proportional to the conduction current. The SCR is on for a shorter time and the back of the SCR waveform will drop earlier.

For Further Investigation Waveforms are similar to those in Plot 38-1 but the photocell will cause the SCR trigger point to vary according to the light level. Applications include alarms, automatic night lighting control, or light control of a process.

153