ad converter

D/A AND A/D CONVERSION  D/A and A/D conversion is very important in digital data processing.  Digital to Analog conversion involves translation of digital information, into equivalent analog information i.e., needed to  Drive a motor,  Pen recorder, and Control of a control system

 in ADC is needed to convert the analog signal to digital signal to incorporate the digital system.

It is also called encoder SYSTEM EXAMPLE:

Analog-to-Digital  The usual method of bringing analog inputs into a microprocessor is to use an analog-to-digital converter (ADC).  Here are some tips for selecting such a part to fit our needs.

Analog-to-Digital Converters  In analog-to-digital converter (ADC) accepts an analog input A voltage or  A current-and  Converts it to a digital value that can be read by a microprocessor.

Analog-to-Digital Converters  Fig. shows a simple voltage-input ADC.  This hypothetical part has two inputs:  A reference and  The signal to be measured.  It has one output, an 8-bit digital word that represents the input value.

Analog-to-Digital Converters  The reference voltage is the maximum value that the ADC can convert.  Example 8-bit ADC can convert values from 0V to the reference voltage.  This voltage range is divided into 256 values, or steps. The size of the step is given by:  Vref/256

where Vref is the reference voltage.

Analog-to-Digital Converters  The step size of the converter defines the converter's resolution. For a 5V reference, the step size is:  5V/256 = 0.0195V or 19.5mV  The most significant bit of this word indicates whether the input voltage is greater than half the reference (2.5V, with a 5V reference).

Each succeeding bit represents half the range of the previous bit.

Analog-to-Digital Converters

      

Adding the voltages corresponding to each set bit in 0010 1100, we get: .625 + .156 + .078 = .859 volts The resolution of an ADC is determined by the reference input.

The resolution defines the smallest voltage change that can be measured by the ADC. The only way to increase resolution without reducing the range is to use an ADC with more bits.

A 10-bit ADC has 210, or 1,024 possible output codes.

So the resolution is 5V/1,024, or 4.88mV; a 12-bit ADC has a 1.22mV resolution for this same reference.  ADCs come in various speeds, use different interfaces, and provide differing degrees of accuracy.  The most common types of ADCs are  Flash,  Successive approximation, and Sigma-delta Flash ADC  The flash ADC is the fastest type available.  A flash ADC uses comparators, one per voltage step, and a string of resistors.  A 4-bit ADC will have 16 comparators, an  8-bit ADC will have 256 comparators.



All of the comparator outputs connect to a block of logic that determines the output based on The conversion speed of the flash ADC is the sum of the comparator delays and the logic delay (the logic delay is usually negligible).

 

Flash ADCs are very fast, but consume enormous amounts of IC real estate.

Also, because of the number of comparators required, they tend to be power hogs, drawing significant current.

A 10-bit flash ADC may consume half an amp. which comparators are low and which are high.



Successive approximation converter  A successive approximation converter uses a comparator and counting logic to perform a conversion.  The first step in the conversion is to see if the input is greater than half the reference voltage.  If it is, the most significant bit (MSB) of the output is set.  This value is then subtracted from the input, and the result is checked for one quarter of the reference voltage.  This process continues until all the output bits have been set or reset.  A successive approximation ADC takes as many clock cycles as there are output bits to perform a conversion.

Sigma-delta  A sigma-delta ADC uses a 1-bit DAC, filtering, and over sampling to achieve very accurate conversions.  The conversion accuracy is controlled by the input reference and the input clock rate.   

The primary advantage of a sigma-delta converter is high resolution.

The flash and successive approximation ADCs use a resistor ladder or resistor string.

The problem with these is that the accuracy of the resistors directly affects the accuracy of the conversion result.  Although modern ADCs use very precise, laser-trimmed resistor networks, some inaccuracies still persist in the resistor ladders.  The sigma-delta converter does not have a resistor ladder but instead takes a number of samples to converge on a result.  The primary disadvantage of the sigma-delta converter is speed.  Because the converter works by over sampling the input, the conversion takes many clock cycles.  For a given clock rate, the sigma-delta converter is slower than other converter types.  Another disadvantage of the sigma-delta converter is the complexity of the digital filter  That converts the duty cycle information to a digital output word.

ADC comparison  Fig shows the range of resolutions, maximum conversion speed available for sigma-delta, successive approximation, and flash converters.



The speed of sigma-delta ADCs reaches into the range of the successive approximation ADCs, but is not as fast as even the slowest flash ADCs.

ADC comparison  For instance, successive approximation ADCs that range from 8 to 16 bits,  you won't find the 16-bit version to be the fastest in a given family of parts.  The fastest flash ADC won't be the 12-bit part, it will be a 6- or 8-bit part.  For instance, successive approximation ADCs that range from 8 to 16 bits,  you won't find the 16-bit version to be the fastest in a given family of parts.  The fastest flash ADC won't be the 12-bit part, it will be a 6- or 8-bit part.

Sample and hold  ADC operation is straightforward when a DC signal is being converted.  But if the input signal varies by more than one least significant bit (LSB) during the conversion time, the ADC will produce an incorrect result.  One way to reduce these errors is to place a low-pass filter ahead of the ADC. Sample and hold  Another way to handle changing inputs is to add a sample-and-hold (S/H) circuit ahead of the ADC.  The S/H circuit has an analog (solid state) switch with a control input.

Sample and hold  The figure shows slowly rising signal is connected to the S/H input.  While the control signal is low (sample), the output follows the input.  When the control signal goes high (hold), disconnecting the hold capacitor from the input.

 Typically, the S/H will be switched to  Hold mode just before the ADC conversion starts, and Switched back to sample mode after the conversion is complete.

 

In the real world, though, the hold capacitor will leak and the buffer amplifier input impedance is finite, So the output level will slowly drift down toward ground as the capacitor discharges.



   

Figure shows various ways of converting three analog input signals to digital signals for acquisition by a single digital n-bit bus.

In some systems, the software directly controls the S/H control input with a port.

In sample mode, and the software must ensure that the acquisition time requirement is met.

In some systems, simply by leaving the S/H in sample mode until a conversion is needed.

After the S/H is placed into hold mode, another bit starts the ADC. After the conversion is complete, the software reads the result.  The process of converting are analog voltage into an equivalent digital signal is known as A to D conversion.  It is some what complicated compare to DAC. There are different methods of conversion. Simple method is simultaneous conversion Simultaneous Conversion  It is based on the use of no of comparator circuits.  Analog to 3 bit digital converter CKT is shown below. For every bit you need one comparator

  

 

Analog signal will be connected with one input of all the comparators. The second input is the ref. voltage.

The ref. voltage used are +V/4, V/2, 3V/4 If the analog input signal exceeds the ref. voltage to any comparator that comparator turns on means output of comparator is high.

If all the comparators are off then analog input signal between 0 – V/4.

If C1 is high then between V/4 – V/2, when all C1C2C3 = 111, then voltage between 3V/4 to V.

Simultaneous Conversion (flash ADC) ď ˇ To convert the analog signal into 3 bit digital signal we need 23-1 = 7 comparators. ď ˇ The encoding matrix must accept such input levels and encode them into a 3 bit binary no (eight possible states).

Comparator Level

COUNTER METHOD ď ˇ

Higher resolutions A/D converter using only one comparator can be constructed if a variable reference voltage are available.

This voltage then can be applied to the comparator and when it becomes equal to the input analog voltage the conversion will complete.

ď ˇ ď ˇ

First counter is reset to all zeros.

When start signal is high immediately the clk will be allowed to the counter.

 

The counter advances through normally binary count sequences and stair case waveform will be generated.

When the ref. voltage is equal to the analog input voltage the gate is closed and counter stops and conversion is complete.

1. Successive approximation Method 2. Single Slope Converter Double Slope Converter Single Slope Converter (ADC)  The heart of this AD converter having a ramp generator.

Its CKT is shown in the fig

Single Slope Converter (ADC)  Manual reset make all counters to O’s and reset the ramp voltage to zero.  Since Vx is +ve. Ramp begins at zero, and output of comparator is Vc must be high which allow the clk into decade counters.  Counter begin counting upward and the RAMP continues upward until the ramp voltage = Vx.



At point t1 the comparator output goes low and disables the clk gate and counter cease to advance.

Simultaneously the –ve transition of Vc generates the STROBE signal in the control box that shifts the contents of the three decade counters into three 4FF latch Ckts

 

Shortly a reset signal resets the RAMP and clears the decade counters to O’s and next conversion cycle will short.

At the same time the contents of the conversion are displayed on the seven segment LED



EXAMPLEA



generalized hybrid and digital circuit by which input analog data can be transmitted, stored, delayed, or otherwise processed as a digital number before re-conversion back to an analog output.

Parallel-Encoding ADC (flash ADC)  The parallel-encoding or flash ADC design provides the fastest operation at the expense of high cost  The resistor network sets discrete thresholds for a number of comparators.  All comparators with thresholds above the input signal go false while those below go true.  Then digital encoding logic converts the result to a digital number.

Successive-Approximation ADC  The successive-approximation ADC is the most commonly used design. This design requires only a single comparator and will be only as good as the DAC used in the circuit.  The analog output of a high-speed DAC is compared against the analog input signal.  The digital result of the comparison is used to control the contents of a digital buffer that both drives the DAC and provides the digital output word.

Successive-Approximation ADC The successive-approximation ADC uses fast control logic which requires only n comparisons for an nbit binary The bit-testing sequence used in the successive approximation method.

Digital-to-Analog Conversion  When data is in binary form, the 0's and 1's may be of several forms such as the TTL form where the logic zero may be a value up to 0.8 volts and the 1 may be a voltage from 2 to 5 volts.  Data in clean binary digital form can be converted to an analog form by using a summing amplifier.  For example, a simple 4-bit D/A converter can be made with a four-input summing amplifier.

More practical is the R-2R Network DAC.  The output of a DAC can only assume discrete values.

DAC Limitations  The relationship between the input binary number and the analog output of a perfect DAC is shown in figure.



Output signals from DACs showing a) the ideal result, and b) a differential nonlinearity or c) nonmonotonic behavior, both caused by imperfectly matched resistors.

 Variable Resistor Network Binary Ladder Variable Resistor Network  DA conversion can easily be done by the resistive network. Consider the truth table of 3 bit binary signal.  we want to change the 8 possible digital signal into equivalent analog signal. 

See 000 – 111 having of discrete levels so the analog signal also will be decided into seven levels.

 

Smallest incremental change in digital signal is represented by 2 0 This will cause the change of analog signal equal to 1/7 of the full scale output voltage = 1/7 X7 = 1 V. Since 21 = 2 and 20 = 1 so we can write 21 = 2 x 20 = 2 x 1/7 x7=2



  

Similarly 22 = 4 = 4 x 20 = 4/7 x7 = 4 volts.

Now the sum of the weight = 1/7 + 2/7 + 4/7 =1.

In general the binary equivalent weight assigned to LSB 1/ [ 2 n – 1 ] = 1/7, where n = 3,

 A resistive divider that performs these function is shown in the fig.

RL is called load where divider CKT is connected its value is very high, not loading the network

Variable Resistor Network  Say digital signal is 001 is applied, note that 0 means 0 volt and 1 means +7 volt.  Now the equivalent analog output voltage can be measured by Millman’s Theorem.  Millman’s Theorem states that the voltage at any node is equal to the summation of currents entering the nodes divided by the summation of conductance.

R0 R V/ 0 2 4 2 / R0 4 / R0

V / R0 V / VA

V / R0 7 / R0

1 / R0

1 / 7Volt .

7 / R0 7 / R0

1Volt.

Four-Bit D/A Converter  One way to achieve D/A conversion is to use a summing amplifier  This approach is not satisfactory for a large number of bits because it requires too much precision in the summing resistors. This problem is overcome in the R-2R network DAC.

Binary Ladder  A 4 bit ladder CKT is shown.  It is constructed by two types of resistors R and 2R which is overcoming the draw back of resistor divider network.  Right end is the output and left end is connected to ground though 2R.

Binary Ladder  Say all the digital inputs are ground = 0000.  At node ‘A’ the equivalent resistance is 2Rx2R/4R = R  At node ‘B’ ‘C’ ‘D’ the equivalent resistance is = R  The total resistance looking from any node to the terminating resistor and outward to the digital input is always 2R.



Say the digital input signal is 1000 then the binary ladder will be

 

As the there is no voltage source connected to the nodes ABC except D so the network will be converted to the The VA = [V/4R] X 2R = V/2

 

Say input 0100, C is connected VA = V/2 x ½ = V/4



Thevenin’s equivalent.

R-2R Ladder DAC  The summing amplifier with the R-2R ladder of resistances shown produces the output  where the D's take the value 0 or 1.  The digital inputs could be TTL voltages which close the switches on a logical 1 and leave it grounded for a logical 0.  This is illustrated for 4 bits, but can be extended to any number with just the resistance values R and 2R.

R-2R Ladder DAC