15 Reasons Cyient Outshines Other Semiconductor Design Service Providers
Contents
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Executive Summary
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Outsourced Services
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Demonstrated Success
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RTL to GDSII
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SoC Verification
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Design Verification
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Physical Design
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DFT
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Analog Mixed Signal Design and Verification
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Custom IC Layout
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Design Services
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Project Scope That Meets Your Needs
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What to expect when working with Cyient
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References
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15 Reasons Cyient Outshines Other Semiconductor Design Service Providers
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Next Steps
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About Cyient
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By choosing an outsourced services provider, semiconductor companies and IDMs can quickly get access to engineers with prior experience to exactly the new skills that they need, like FinFET design, AMS or Formal Verification, and DFT techniques.
Executive Summary
Demonstrated Success
IC engineering teams at both fabless semiconductor companies and integrated device manufacturers (IDMs) face the same business challenges of getting their next chip design to market on time, with the staff at hand, while working within the budget. Finding out that your existing design and verification team is already stretched too thin, or that your engineers don’t have the right experience for the challenge creates a real dilemma to success. Hiring and training new engineers will simply take too long, so the option of adding a flexible workforce by using an outsourcing services provider becomes appealing to consider.
Cyient is an outsourced design services provider with over 350 semiconductor engineers. It has helped a wide range of clients over the past 15 years, including tier-one semiconductor companies in North America, Europe, Taiwan, Japan and APAC. In total Cyient has over 14,000 associates, located in 38 countries, serving industries like Semiconductor, Transportation, Medical, Consumer, Energy, Oil & Gas, Aerospace and Defense. The semiconductor teams at Cyient are actively involved in leading-edge IP development using 10 nm and 14 nm Bulk/SOI FinFET technology and collaborate closely with the fabs.
Outsourced Services By choosing an outsourced service company, you can quickly get access to engineers with prior experience to exactly the new skills that you need, like FinFET design, AMS or formal verification, and DFT techniques. These engineers have already gone through the learning curve, saving you valuable time and will complement your existing team for the duration of the project. Perhaps your project looks like it will run over budget or that the complexity has increased to meet new market requirements. Adding an outsourced team will help meet your budget, and build your team to the proper size to meet the market window of opportunity. Moving from a 28 nm planar CMOS node to 16 nm FinFET process requires about a 3X increase in circuit simulation time due to process variation effects1. So, it’s recommended to be prepared with more computing and engineering resources.
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You will find a complete set of engineering skills ranging from RTL design and verification through IC implementation, using each of the major EDA tool flows (Synopsys, Cadence, Mentor Graphics). Since Cyient owns EDA Licenses, your team doesn’t incur added costs to the services team. Modern SoCs can have hundreds of IP blocks, and Cyient will help you find just the right IP and VIP to meet your requirements, integrate the IP, and verify it in the context of the complete system.
RTL to GDSII Examples of IC design services that included RTL creation, functional verification, logic synthesis, formal analysis, floorplanning, place and route, DFT, timing closure, and GDSII output are listed in the following table: Project Type
Business Need
Results
802.11n Router • 65 nm, 8M gates, 500MHz
• Derivative SoC development • 18% die reduction • Timing closure with 13 modes across 6 corners
• First-pass silicon success • 22.6% die reduction • 70% manufacturing yield
HD Image Processor • 90 nm, 6M gates, 237 MHz
• All engineering RTL to GDSII • System-level verification • Timing closure, DFT, physical design
• Cost savings with team across US and India • Design and verification of complex DSNU, MJPEG, ARM cache subsystem, SPI, DMA, Gigabit Ethernet
• LVDS at 1 GHz
SoC Verification Design service projects in this category were focused on the logical verification process of a SoC to create high coverage stimulus using a metric-driven verification methodology.
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Project Type
Business Need
Results
Cache Coherent Interconnect Subsystem IP • 1 Manager, 10 Engineers • 12-month project
• Mobile platform development • OVM verification environment
• Integrated 4 OCP master OVCs, 4 AXI4ACE master OVCs, 1 AXI4 master OVC • Integrated 5 OCP slave OVCs and 1 AXI4 slave OVC
AMS UVM Verification • 3 Engineers • 1-month project
• AMS verification environment • Metric-driven verification • Executable verification plan
• UVM-SV based verification environment • Reusable I2C master UVC to generate I2C transactions
ARM Cortex based SoC • 12 Engineers • 12-month project
• Mobile platform with Cortex-M3 • ARM DSM setup • Low-power verification • Environment components • USB and PCIE integration developed with SystemVerilog verification and OVM • USB, PCIE VIP integration
Design Verification IP blocks and subsystems have been verified across a wide range of domains. Project Type
Business Need
Results
Memory Subsystem • 8 Engineers • 10-month project
• Functional verification of cache coherent multiprotocol interconnect IP • Memory subsystem IP verification
• Used coverage-driven random verification with UVM • Verified AXI4.0, ACE, and OCP 3.0 protocols • Regressions achieved 100% pass rate
DDR-3 • 3 Engineers • 6-month project
• Verify DDR3 PHY, DDR3 controller, RLD2/RLD3 PHY • Augment verification team
• Cost savings with team across US and India • Design and verification of complex DSNU, MJPEG, ARM cache subsystem, SPI, DMA, Gigabit Ethernet
Power Management IC
• Develop verification environment using Verilog • Augment verification team
• Verification environment created using Verilog • Developed verification test plan • Reached 100% regression pass, 100% code coverage
Ethernet
• Verify Ethernet 100M/1G PHY with Specman/E • Functional coverage
• Verification plan developed • Wrote checkers using eRM • Achieved functional coverage goal
Physical Design IC design is often divided between front-end and back-end work, and the following projects are in the back-end where the physical layout is completed at the cell and transistor levels.
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Project Type
Business Need
Results
Video Processor Chip • 17 million placeable instances
• Implement a video processor from netlist to GDSII • Physical design and timing closure • Physical verification
• Used Cadence SoC Encounter for place and route, Conformal for equivalence checking • Mentor Graphics Calibre used for physical verification
Graphics Chip • 9 Engineers • 12-month project
• Physical design of 9 blocks • Full-chip timing closure • Physical verification
• Completed 9 blocks through floor planning, place and route, timing, IR drop analysis, physical verification • Timing met
Project Type
Business Need
Processor • TSMC 65 nm • 11 M gates • 275 MHz
• Use libraries from TSMC and Virage • Fault coverage of 97%
Handheld Device • TSMC 90 nm • 2 M gates • 100 MHz
• Use libraries from ARM and Virage • Achieve 99% fault coverage
Results
DFT Design For Test (DFT) is a design service on the front-end of design where the goal is to reach a high fault coverage goal by using design techniques like scan chains and built-in test (BIST).
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Project Type
Business Need
Results
Digital Video Processor • 3 Engineers • 4-month project
• Cost savings • Time-to-market
• Used JTAG, scan insertion, and scan compression • Lowered ATE test times • Transition and stuck-at fault test ATPG with Mentor TestKompress
Multimedia Chip • 2 Engineers • 6-month project
• Cost savings • Memory testing with repair features • JTAG standards, 1149.1 and 1149.6
• Used memory BIST on 320 memories with 66 controllers • Scan compression with Mentor TestKompress
Mixed-Signal Chip • 4 Engineers • 5-month project
• Cost savings • Memory test with repair features • Analog IP testing • Full-chip scan
• Hierarchical scan and test compression used • Memory BIST used • IEEE P1500 test architecture for analog IP • Tested SerDes, PLL, and DDR
Analog Mixed Signal Design and Verification Combining both digital and analog IP on a single device is another specialty service offered by Cyient as shown in the following client examples. Project Type
Business Need
Results
Analog Design • DC-DC Buck Converter • PMIC
• High efficiency • Programmable
• 96% max efficiency • Programmable using metal3 mask option
Analog Design • CAN PHY Transceiver • LVCS Transceiver
• Wide temperature range • High ESD tolerance • Japanese CAN standards
• Operation over -40 to 150C • ESD tolerance to +/- 20KV • Designed with 0.35um BCDMOS SOI
PMIC • 4 Engineers • 6-month project
• AMS verification • eRM environment
• Analog blocks modeled • Full-chip transistor-level simulation with NanoSim • Digital simulations with VCS and e
Custom IC Layout Analog and digital IP can be created at the transistor-level to help your team achieve the exact specifications required when off-the-shelf IP isn’t a good fit. Project Type
Business Need
Results
IFPLL • Layout of analog blocks, custom • Layout of analog blocks: PFD, Regulators, VCO • 2 Engineers digital blocks, and chip level • Layout of custom digital cells • 6-month project • Use 32 nm SOI technology • Physical verification of blocks • Chip-level integration and physical verification SERDES • 4 Engineers
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• Layout of analog blocks and custom digital blocks • Use 32 nm SOI technology
• IC layout of analog blocks: OpAmp, DAC, RX Rotator, TX rotator • Layout of custom digital blocks: standard cells, level shifters • Physical verification of blocks
• Cost savings Low-power RF chip • Layout of analog blocks and full • 2 Engineers chip • 6-month project • Use of Cadence tools • TSMC 65 nm LP technology
• Layout of analog blocks: ADC, PLL, VGA, LDOs • 6 GHz nets required shielding • Full chip layout integration and physical verification
PMIC • 12 Engineers
• Layout of analog blocks: Clock generators, buck converter, battery charger • Use of Cadence and Mentor tools for layout and physical verification
• Layout of analog blocks and custom digital blocks • Use of 180 nm DNWELL process • Physical verification with EM checks
Design Services There are three major service areas offered by Cyient - semiconductor design, programmable device design and system and software design. As you can see through the project examples above, Cyient has extensive experience delivering services in every phase of the design and implementation. • Semiconductor Design - RTL design and verification - Logic synthesis and DFT - Physical design and STA - Library cell development and characterization - Mixed-signal design and verification - Analog layout - Post-silicon validation - Yield enhancement - Silicon bring-up • Programmable Device Design - High-density FPGA-based design - Soft processor integration - IP development and integration - Reference design development - Firmware development and integration - RTL design, verification, and validation - Turnkey designs • System and Software Design - OS enablement, porting - Board support package (BSP) - Device drivers – core, peripherals - Audio, video and speech codecs - Middleware, multimedia components - 3rd party IP, application integration - System integration and validation - Benchmark, compliance testing - Derivative product development - Sustenance of platform software
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Project Scope That Meets Your Needs For ASIC and SoC designs a typical design flow includes multiple steps, and Cyient can perform some or all of these steps. It really depends on how you want your existing team to be assisted in meeting the schedule. The experienced teams from Cyient have delivered over 300 ASIC tape-outs with a first-pass silicon rate of greater than 95%, while meeting schedule commitments over 95% of the time, all while providing a 50% cost benefit to clients. What makes Cyient unique among service providers is that they provide an on-site resource for your local team, and that person manages all of the offshore resources for you. The outsourced engineers are trained on each of the EDA vendor tools, flows, and methodologies, so they start producing quickly
Design Flow Product Definition and Design
RTL Design
Functional Verification
Planning/Partitioning
Synthesis
DFT Physical Design with Timing Closure Physical Verification and Tape out Productization and Implementation
What to expect when working with Cyient
Services - Ownership
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DFT Net list
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and without draining your EDA licenses, saving you both time and expense. The result is a flexible business model that is created for each customer engagement to optimize how services are delivered to meet their needs. Founded in 1991, Cyient is publicly traded on the NYSE as CYIENT. With the necessary corporate governance a public company requires, financial transparency provides much-needed peace of mind when selecting an outsourcing partner. There are processes and procedures in place within Cyient to ensure that all of your IP and design data are secure and protected. This lets you concentrate on getting to market, knowing that only your team has access to proprietary information.
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Program management ensures that your team and Cyient discuss the technical objectives, identify the capabilities that you already have, define the role that Cyient will provide, how to meet your project timeline, and how team members will connect throughout the design, verification and validation process. A member from Cyient will available to be on-site with your team to coordinate with a program management role. Through daily communication, any issue is quickly raised and dealt with, eliminating the possibility of any last-minute surprises. This approach allows Cyient to modify their design flow or EDA tool usage to meet your schedule commitment. Employees at Cyient have a set of core values that fit the acronym FIRST – Fairness, Integrity, Respect, Sincerity, and Transparency. This is part of their corporate culture, and it helps build a winning relationship with your design team. Managers at Cyient are PMP certified, so you’ll be able to follow the progress of this outsourcing approach and know the schedule status. A Project Management Professional (PMP®) credential means that you have a person with the experience, education and competency to lead and direct successful semiconductor design projects.
References 1
Design Automation Conference 2015. Moving from 28 nm to 16 nm. ARM, Freescale, Broadcom, HiSilicon, TSMC, Cadence.
15 Reasons Cyient Outshines Other Semiconductor Design Service Providers 1.
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Global services provider with more than 14,000 associates in 38 countries, where there are more than 350 experienced semiconductor designers Engineering expertise spanning concept design engineering through manufacturing including aftermarket services – they can provide full product services beyond semiconductor 15 years of design expertise in every semiconductor engineering design discipline Many Tier-1 semiconductor clients Extensive resources include complete design flows from RTL through GDSII using all three major EDA vendors, helps control your costs Design verification specialists; analog mixed-signal (AMS), embedded processor (ARM), Interface IP, software – using the latest verification methodologies (UVM, SystemC and others) Physical design experts who can minimize die size, ensuring timing closure, achieving power budget and ensure testability (DFT)
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Semiconductor process experience with the latest process geometries, providing custom library migration and characterization for each new semiconductor node including FinFET devices Embedded software development for popular platforms like ARM, MIPS System level software development to enable operation within Linux, Windows, Android, MAC OS, iOS, etc. Partnerships with semiconductor ecosystem companies to provide complete turn-key semiconductor design and development services Alliances with IP and semiconductor foundry partners Extensive design expertise in virtually all of the vertical markets that the semiconductor industry serves Turnkey services through trusted partners eliminate the difficulty of dealing with multiple vendors for packaging, assembly, manufacturing, design, etc. Circuit board design through manufacturing and mass production addresses go-tomarket needs
Next Steps Now that you’ve learned a bit about how outsourcing with Cyient can complement your existing design team, please take the next step and request a semiconductor design services overview. During this meeting, we will provide a detailed overview of our success working with the top semiconductor companies and understand the ways these experiences can be applied to your business needs.
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If you have an immediate need, why not request a semiconductor design project assessment where we will work with you to map your requirements with Cyient services capabilities and staff. We will review the methods we use to ensure project communication flows fluidly between your project team and the Cyient project resources.
About Cyient Cyient is a global provider of engineering, manufacturing, data analytics, networks and operations solutions. We collaborate with our clients to achieve more and shape a better tomorrow. With decades of experience, Cyient is well positioned to solve problems. Our solutions include product development and life cycle support, process and network engineering, and data transformation and analytics. We provide expertise in the aerospace, consumer, energy, medical, oil and gas, mining, heavy equipment, semiconductor, rail transportation, telecom and utilities industries. Strong capabilities combined with a network of more than 13,100 associates across 38 global locations enable us to deliver measurable and substantial benefits to major organizations worldwide. For more information about Cyient, visit our website.
NAM Headquarters Cyient, Inc. 330 Roberts Street, Suite 400 East Hartford, CT 06108 USA T: +1 860 528 5430 F: +1 860 528 5873 EMEA Headquarters Cyient Europe Ltd. High Holborn House 52-54 High Holborn London WC1V 6RL UK T: +44 20 7404 0640 F: +44 20 7404 0664 APAC Headquarters Cyient Limited Level 1, 350 Collins Street Melbourne, Victoria, 3000 Australia T: +61 3 8605 4815 F: +61 3 8601 1180 Global Headquarters Cyient Limited Plot No. 11 Software Units Layout Infocity, Madhapur Hyderabad - 500081 India T: +91 40 6764 1000 F: +91 40 2311 0352
www.cyient.com connect@cyient.com
Š 2016 Cyient. Cyient believes the information in this publication is accurate as of its publication date; such information is subject to change without notice. Cyient acknowledges the proprietary rights of the trademarks and product names of other companies mentioned in this document. Updated June 2016
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