Manual de servço tvs lg 37lc2r 42lc2r 32lb1r 37lb1r 42lb1r chassis hurricane3 high by Portal da Eletrônica

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Hurricane3 High chassis guide

Table of contents 1. Specification 2. Block Diagram 3. Trouble Shooting 4. Debugging Method 5. Adjustment UI Specification 6. Document

2006.05.03 Great Company Great People

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Blue Ocean P続 Innovation

Model Concept

Design 37LC2R

H&C

2 Tone

• New XD Engine • 10 Bit • HDMI • 3D Surround (Royalty Free) • 1Tuner(EU), 2Tuner(Non-EU) • AV Input Navigation • Stand-by Power consumption 1W • On Screen Equalizer

Feature

Module

42PC1R

• Clear Filter • Brightness : 1,200 ㏅/㎡ • Contrast : 10,000 : 1 • ASIC : 4025적용

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• Brightness : 500 ㏅/㎡ • Contrast : 1600 : 1 • View Angle : 178 ˚

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Model Concept Tool line up

PB2

PC1/PC3

Type

42X

50X

H&C

●

▶ PB2 Tool(Better High) All H&C

구분

26”

32”

37”

42”

H&C

LB2

LC2

2 Tone

▶ LB2 Tool(Better High) All H&C

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Blue Ocean P³ Innovation

Model Specification Model

37LC2R-ZH

37LC2R-TH

42LC2R-ZH

42LC2R-TH

32LB1R-TH

37LB1R-TH

42LB1R-TH

16:9

0.2 × 0.6

0.227 × 0.681

0.227 ×0.681

0.17 × 0.51

0.2 × 0.6

0.227 ×0.681

940.3

1067.3

800.4

940.3

1067.3

1366X768 (WXGA)

500

Contrast Ratio

1200:1

View Angle

178˚Min

Color(R,G,B)

16.7 Mil

Input Signal

PAL

Multi

PAL

Multi

E/F/G/S/I/ SW/N/D

E/C/F/G/S /Arab/Parsi

E/F/G/S/I/SW/ N/D

E/C/F/G/S /Arab/Parsi

N-EU

1-Tuner

2-Tuner

1-Tuner

2-Tuner

Aspect Ratio Cell Pitch(mm) Screen size(mm) Resoultion

V I D E O

Luminance (cd/㎡)

OSD Language Market place Remark

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Model Specification Model

J A C K

37LC2R-ZH

37LC2R-TH

42LC2R-ZH

42LC2R-TH

32LB1R-TH

37LB1R-TH

42LB1R-TH

RF In

AV in

Monitor out

S-Video in

Component Input(Y,Pb,Pr)

Variable Audio out

PC Audio In

RGB Input

RS-232C

Remote control

110-240V 50/60Hz

190

230

140

190

230

944×729 ×286

1054×813×2 86

1054×813 ×286

911.4×599 ×259

1045.8×693.8 ×260.4

1175×768×3 00

35.5

42.3

22.6

31.6

41.4

AC Input Power Consumption SIZE (W x H x D) (mm) :with stand Weight with Packing(kg)

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Blue Ocean P³ Innovation

Model Specification Model

42PC1R-ZH

42PC1R-TH

42PC1R-CH

42PC3R-ZH

50PC1R-ZH

50PC1R-TH

50PC1R-CH

16:9

Cell Pitch

300(um) × 676(um)

270(um) × 810(um)

Resolution

1024X768 (XGA)

1366X768 (WXGA)

Peak White /special (cd/㎡)

340 /540

340 / 540

340/ 540)

340(540)

280(400)

Contrast Ratio

10000:1 (1% full white window in dark room)

10000:1 (1% full white window in darkroom)

10000:1 (1% full white window in dark room)

N-EU

China

N-EU

China

1-Tuner

2-Tuner

1-Tuner

Aspect Ratio

V I D E O

Market place Remark

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Blue Ocean P³ Innovation

Model Specification Model

J A C K

42PC1R-ZH

42PC1R-TH

42PC1R-CH

42PC3R-ZH

50PC1R-ZH

50PC1R-TH

50PC1R-CH

RF In

AV in

Monitor out

S-Video in

Component Input(Y,Pb,Pr)

Variable Audio out

PC Audio In

RGB Input

RS-232C

Remote control

110-240V 50/60Hz

330

430

1129×748.5 ×380

1129×748.5 ×336.6

1302.6×872 ×355.8

29.3

31.3

51.5

AC Input Power Consumption SIZE (W x H x D) (mm) :with stand Weight with Packing(kg)

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Blue Ocean P³ Innovation

Main Feature Compare with H2

Platform Version Up (H2→H3) • LCD Board & PDP Board is different à Same PCB Board (With option) • Main/Sub IC is separate à Main/Sub Picture IC were merging (Only One Main IC : XD8662)

Added features in circuit • New XD Engine -. Adaptive NR -. No noise boosting Sharpness -. Sub Picture Y/C Separate Sharpness Control • Blue-tone stretch (Only White region)

New Feature of PDP Module

Improved Function from H2

• Decrease the reflection of eternal light -> increase the clarity and contrast (XGA Grade extended) • 10 Bit Input and Processing • Adopt Low Contour noise Algorithm

• Sub Picture 3D Comb Filter • 8Bit à10 Bit Signal Processing (Decoder, ADC, de-interlacer, Output)

Productivity • Support DMS Full process (Productivity will be very higher then previous model)

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Blue Ocean P³ Innovation

H3 High Whole Block Diagram 유선IR

TX Tx/Rx : ±15Vpp

RS232

ST3232C

DSUB_SCL / DSBU_SDA

RGB_PC RGB_DTV

DS_VS / DS_HS

PC_Audio

74HC14 SCART1_FB

Comp_L/R : 500mVrms Comp_SW

COMP

COMP2

CN_IIS

OUTPUT 31P_LVDS

MC_IIS

I2C

MAIN_V or Y/C OUT : 2Vpp SUB_V : 2Vpp

SCART1_LIN/RIN : 500mVrms SCART1_ID

(TV_out)

Tx0/1/2/3/4/C± DISP_EN SCL/SDA_Part

MAIN SCALER XD8662

Comp_SW Comp2_SW

Comp2_L/R : 500mVrms Comp2_SW

Scart1

AT49BV160C F-ROM(2MB)

TXD /RXD : 5V Digital VGA_RGB : 0.7Vpp AIP_RAW_VS / AIP_RAW_HS_CS : 5V High/Low COMP_Y/Pb/Pr : 1/0.7Vpp COMP2_Y/Pb/Pr : 1/0.7Vpp SCART1_RGB : 0.7Vpp

24C02

PC_Audio_L/R : 700mVrms

K4D261638F-LC50X2 DDRRAM(128MB X2)

HDMI_DATA HDMI_CLK/DE HDMI_VS/HS

Variable_audio_out L/R

SCART1_VIN : 1Vpp SCART1_ID SCART2_ID SCART2_LIN/RIN : 500mVrms SCART2_VIN/YIN/CIN : 1/0.285Vpp SCART2_ID MNT_LOUT/ROUT MNT_OUT TU_MAIN : 1Vpp I2C AV SWITCH TUNER SIF (MAIN) CXA2069Q AM_Audio SCART1,2_LIN/RIN TUNER TU_SUB : 1Vpp (SUB) LIN3/RIN3 : 500mVrms

Scart2 (MNT_OUT)

RF Rear AV (AV3)

PC_Audio_L/R AM_Audio / S I F COMP1,2_RIN/LIN AV_LOUT/ROUT

Audio S/W & CONTROL MSP4450K

HDMI_IIS TV_L/R OUT : 500mVrms

I2 C

I2S (SCK/WCK/DATA)

VIN3/YIN3/CIN3 : 1/0.285Vpp AV3_SW/S3_SW MNT_OUT

MNT_OUT : 1Vpp MNT_LOUT/ROUT : 500mVrms I2C

HDMI1/2

HDMI Rx ANX9021

HDMI_DATA : 3.3V HDMI_CLK/DE : 3.3V HDMI_IIS : 3.3V HDMI_VS/HS : 3.3V

24C02

Variable Audio_out

SCL/SDA Variable_audio_out L/R : 500mVrms

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I2 C

PWM NTP2000H I2 C

L_CH R_CH

AMP TAS5122

L_SPK_OUT R_SPK_OUT

I2 C

AV4_SW/S4_SW VIN4/YIN4/CIN4 : 1/0.285Vpp LIN4/RIN4 : 500mVrms

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Video Signal Audio Signal

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Main Scaler(XD8668) Features

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Main Scaler(XD8668) Block Diagram

• The FLI8668 chip has a flexible Analog Front End (AFE) with 13 configurable inputs through an analog multiplexer before the Analog to Digital Converters (ADCs). • It also contains an embedded Multi-Standard Video Decoder. This decoder contains a digital comb filter for optimum Y/C separation. A 3D comb filter is a vailable for optimum Y/C separation, that reduces or eliminates any artifacts due to poor Y/C separation seen on standard 2D video decoders on composite inputs, most commonly found on TV tuners. • The FLI8668 microprocessor can process a wide range of Vertical Blanking Interval (VBI) data and display this data with the bitmap OSD processor. The microprocessor can support VBI data processing in the Main or PIP channels as well as in the background when the corresponding video stream is not pre sent on the output stream. The VBI dataslicer can extract data encoded into the VBI of the input video stream. Decoded data bytes from the VBI dataslicer are stored in a memory buffer for subsequent processing by the microprocessor. The microprocessor decodes the different formats of the VBI data and pas ses the information to the OSD controller for output to the display controller. The VBI decoding process can run continuously in the background for inputs th at contain VBI data.

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Main Scaler(FLI8668) Block Diagram Explanation

• The Digital Input Port is a 48-bit data input with flexible configuration to support a wide range of digital sources. It consists of two 24-bit ports (PORT A and PORTB),two sets of control signals (VS,HS,ODD,etc.), and 4 input clocks. Up to 4 different inputs are supported as long as at least 2 of these in puts are 8-bit CCIR656. The digital input port can also be configured to support one 30-bit input with a second 16-bit input port. Bit 7 to 0 of PORTA ca n be configured as a bidirectional interface for media card applications. • DCDi (Directional Correlation De-Interlacing) is an algorithm from Genesis Microchip’s Faroudja division, that is used to deinterlace video content (co nvert from interlaced to progressive scan). DCDi is known for its smooth interpolation of video content as it fills in the missing lines. Its purpose is to eli minate jagged edges (jaggies) along diagonal lines caused by interpolation, resulting in the projection of cinema-like images with exceptional picture q uality. • The FLI8668 allows a very flexible PIP display configuration whereby either the graphics or video channel may act as the PIP source to overlay over the other channel. Any one of the inputs (analog RBG, 24-bit digital, 8-bit digital, YPbPr, composite video, etc) may be multiplexed to either channel. T he PIP can be from any of the AIP (Analog Input Port) 1 or 2 or DIP (Digital Input Port) 1 or 2. Single PIP allows the PIP display to be placed arbitrarily in the display window. It can be placed within the Main display, partially overlapped with Main display, or fully detached from Main display. Multiple PIP s display allows a number of PIP windows to be displayed at the same time depending on display pixel resolution. The Main and one PIP window will be running in real time. There are up to 16 PIP windows available at the same time, however only one might be active. All of them should be aligned to the 4x4 grid. Default S/W application uses multiple PIP windows to display different RF channels. • Two LVDS channels (A and B) are available on the output of the FLI8668 to transmit data and timing information to the display device. FLI8668 direct ly drives the standard LVDS interface panels, supporting all standard data formats—single and dual bus, 18- or 24-bit data output. The 24-bit data may be mapped as either standard receiver formats. • The FLI8668 has a fully programmable, true color bitmapped OSD controller capable of displaying up to 16 “tiles” or bitmap windows on the display. The individual tiles are programmable for location, size and bits per pixel, and have a precedence determining which tiles appear when overlapping oc curs on the display. Tile data is stored in the external frame store memory by the OCM in either : 1, 2, 4, or 8-bit per pixel format. On-chip table registe rs point to the start of tiles in external memory. A programmable on-chip 256x24-bit color lookup table is provided to map the OSD pixels onto a true 2 4-bit color space. • The FLI8668 on-chip microcontroller (OCM) serves as the system microcontroller. It programs the FLI8668 and manages other devices in the system such as the keypad and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can address a 22-bit address space to utilize 4 MB external ROM.

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H3 High Power A

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H3 High Power - A

3 2

Power Sequence :

AC_DET RL_ON +5VST

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Power Cord connect to set. Power b/d supplies 5VST CON from wafer P1000 pin 3 and 8. This is also distri buted as +5VST_CORTEZ, that connect to Regulator IC1001, IC1004, and IC1005, which regulate 1.8, 2.5, and 3.3V for Cortez (turns ON). Also distributed as + 5VST, that connect to Transistors Q1000,1001,1004, and 1005. AC_DET signal are sent by Power b/d from pin 1 waf er P1000 to pin N23 of IC800(Cortez). Then Cortez s end 3.3V_ON from pin M2 to Power b/d via pin 13 P1 000. IC800 send RL_ON from pin U24, this switches the tr ansistor Q1004 ON so +5VST grounded, this makes t he transistor Q1000 OFF, so other +5VST supplies R L_ON on pin 2 wafer P1000. So Relay on Power b/d t urns on to supplies 3.4, 6, 12, and 19V.(section 2) 5VDet is sent by Power b/d to Cortez. Then Cortez s end command to turn on VaVs from pin U25 that swit ches ON transistor Q1005, so +5VST grounded, this makes transistor Q1001 OFF, and this make another +5VST supplies to pin 5 wafer P1000. The Power b/ d supplies X b/d and Y b/d.

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H3 High Power - B 3Và1.8V 5Và3.3V

Power Sequence : 1.

12Và9V 2.

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The +5VST_Cortez as an input on pin 1 of IC1001(B A033T), a LOW SATURATION VOLTAGE REGULATO R, is being step-down to 3.3V. Then this output act as input and enable for IC1003 pin 2 and pin 1 (SC15 65-1.8TR), a VERY LOW DROP OUT 1.5 Amp REGU LATOR WITH ENABLE, the output 1.8V is in pin 4, that is regulated to +1.8V_ADC_CTZ,+1.8V_CORE _CTZ, +1.8V_DLL_CTZ, and +1.8V_PLL_CTZ. The P_12 (from section 2), as an input on pin 1 of IC1 002 (KA7809R), a 3-TERMINAL 1A POSITIVE VOL TAGE REGULATOR, regulated to be 9V output on pin 3, distributed as +9V_CXA2069, +9V_MSP4450, +9 V, and +9V_TK1184. The VAVS_ON from Cortez switches ON transistor Q 1006, and makes +12V_panel grounded and supply pi n1-4 IC1006(SI925DY), a DUAL P-CHANNEL LOGIC LEVEL POWER TRENCH MOSFET, minimized ON s tate resistance, and the output is on pin 5-8 a 12V_L CD. The VAVS_ON also enable IC1007 pin 7, to s tep-down an input +12V_PANEL on pin 2 into 5V_LC D on pin 1 and 3.

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H3 High Power - C 5Và3.3V 5Và3.3V

Power Sequence : 1.

The+5V_CORTEZ acts as input on pin 1 of IC1005( BA033T) a LOW SATURATION VOLTAGE REGUL ATOR, which step-down into 3.3V output on pin 3. This outputs then is distributed as +3.3V_PLL_C TZ, +3.3V_LBADC_CTZ, +3.3V_LVDS_CTZ, + 3.3V_LVDS_PLL_CTZ, and +3.3V_IO_CTZ. The 3.3V output from IC1005 also acts as input on p in 1 of IC1000 (MIC39100-2.5WS), a 2.5V/1A REGU LATOR, step down the 3.3V into 2.5V output on pi n 3 as a +2.5V_DDR_CTZ.

The+5V_CORTEZ also acts as input on pin 1 of IC1 004(BA033T, a LOW SATURATION VOLTAGE REG ULATOR, which step-down into 3.3V output on pin 3. This outputs then is distributed as +3.3V_ADDC1 _CTZ, and +3.3V_ADDC2_CTZ

3.3Và2.5V

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Trouble Shooting Guide 1. No power ◈ Symptom 1) Minute discharge doesn’t occur at module. 2) Front LED doesn’t come into action.

Start check

Is inserted a plug in power cord?

Plug in a power cord

YES NO

Is connected the Line Filter and PSU?

Connect a cable. Plasma (EL11), LCD(SC100)

YES NO

Is normal the fuse of PSU? Plasma(F101), LCD(F111)

Replace the fuse

YES Is it connected that PSU and 13pin cable in VSC board?

Connect the 13pin cable.

YES After remove all cables connected to PSU(except the CN101), authorizes the AC voltage marking on manual. When ST-by 5V doesn’t operate, replace PSU

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Trouble Shooting Guide 2. Protection mode ◈ Symptom 1) After once shining, it doesn’t discharge minutely from module. 2) The relay falls.( The sound is audible “ Click”) 3) It is converted with the color where the front LED is red from white.

Start check

Is the PSU normal?

Is output the normality Low/High Voltage except Stand-by 5V?

Replace the power board

After connecting well each connector the normality it operates?

Replace the power board

Is normal the fuse (FS2,FS3) on Y-B/D?

YES Is the each connector normal? YES Is the Y- Board normal ? YES Is the Z- Board normal ?

YES NO

Is normal the fuse (FS1,FS2) on Z-B/D? YES

YES Is the X- Board normal ?

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Is normal the output voltage after remove P100,110,200, 210 connector of X-B/D?

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Is normal the output voltage after remove P1connector of Y-B/D?

Replace Y-B/D

Replace the fuse NO

Is normal the output voltage after remove P1 connector of Z-B/D?

Replace Z-B/D

Replace the fuse After remove P100,110 output voltage normality: Replace Right X-B/D After remove P200,210 output voltage normality: Replace Left X-B/D

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Trouble Shooting Guide 3. No Raster ◈ Symptom 1) No OSD and image occur at screen. 2) It maintains the condition where the front LED is white

Start check

Does minute discharge at Module?

Is the inverter/VaVs on?

Is output the normality Low/High Voltage except Stand-by 5V?

Replace the power board

YES YES

Is the link cable normal?

Check the PDP/LCD Module

Reconnect the link cable in P803(Plasma)/P804(LCD)

Replace the VSC

YES Is the IC800’s output normal?

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Trouble Shooting Guide 4. In case of becomes unusual display from RF mode(Main) Is normal video output of the Tuner? (Check TU201_Pin14)

YES

Is the Tuner Cable connected well?

YES

Check the power ( L1103)

Cable inserts well.

Is normal video output NO of CXA2069Q? (Check R324, In case of S-Video check R324, R328)

Is normal the Input voltage ? (Check L308)

Is the LVDS Cable connected well?

Is normal the I2C communication ? (Check Pin5, Pin4)

NO Change the Tuner

(Check R309, R310)

Check the power ( Check L1004)

YES

YES Is normal the I2C communication ?

NO YES

Is normal the Input voltage ? (Check Pin8, Pin6)

Change the IC(IC300)

Cable inserts well

YES

Change the IC(IC800)

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Trouble Shooting Guide 5. In the case of becomes unusual display from rear AV mode(main) Is normal video input of the A/V jack? (Check R2101)

Check the input source)

YES Same as Block A

6. In the case of becomes unusual display from rear S-Video mode(main) Is normal video input of the A/V jack? (Check R198, R199, R2100)

Check the input source)

YES Same as Block A

7. In the case of becomes unusual display from side AV mode(main) Is normal video input of the A/V jack? (Check R343)

Check the input source)

YES Same as Block A

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Trouble Shooting Guide 8. In the case of becomes unusual display from side S-Video mode(main) Is normal video input of the A/V jack? (Check R339, R341, L310)

Check the input source

YES Same as Block A

9. In the case of becomes unusual display from SCART 1 mode(main) Is normal video input of the A/V jack? (Check R102)

Check the input source

YES Same as Block A

10. In the case of becomes unusual display from SCART 1_RGB mode(main) Is normal video input of the A/V jack? (Check L111, L112, L106)

Check the input source

YES Same as Block A

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Trouble Shooting Guide 11. In the case of becomes unusual display from SCART 2 mode(main) Is normal video input of the A/V jack? (Check R115)

Check the input source

YES Same as Block A

12. In the case of becomes unusual display from SCART 2_YC mode(main)

Is normal video input of the A/V jack? (Check R115, R149)

Check the input source

YES Same as Block A

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Trouble Shooting Guide 13. In case of becomes unusual display from RF mode(Sub) Is normal video output of the Tuner? (Check TU200_Pin14)

YES

Is the Tuner Cable connected well?

NO YES

Is normal video output of CXA2069Q? YES (Check R312, In case of S-Video check R312, R314)

Check the power ( L1103)

Is normal the Input voltage ? (Check L308)

YES

Is the LVDS Cable connected well?

(Check Pin5, Pin4)

NO Change the Tuner

Is normal the I2C communication ? (Check R309, R310)

Check the power ( Check L1004)

YES

YES Is normal the I2C communication ?

Cable inserts well.

Is normal the Input voltage ? (Check Pin8, Pin6)

Change the IC(IC300)

Cable inserts well

YES Change the IC(IC800)

14. In case PIP doesn’t display from other modes(Sub) ▷ Same as the case of main except block A should be change to B

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Trouble Shooting Guide 15. In case of becomes unusual display from component1 mode(main/sub) Is normal video input of the JK102? (Check L126, L127, L128)

Check the input source

YES Change IC(IC800)

16. In case of becomes unusual display from component 2 mode(main/sub) Is normal video input of the JK103? (Check L129, L130, L131)

Check the input source

YES Change IC(IC800)

17. In case of becomes unusual display from RGB mode(main/sub) Is normal R, G, B input and H,V sync of the JK500? (Check R509, R511, R512 R513, R515)

Check the input source

YES Change IC(IC800)

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Trouble Shooting Guide 18. No Sound ◈ Symptom LED is White Screen is existent, but sound isn’t

◈ Check follow All input (mode) is no sound?

Is the speaker on in menu?

YES

YES Only HDMI is no Sound?

Is the speaker cable normal?

Download the EDID data NO

YES Only AV input is no Sound?

Set on speaker in menu

Check the Speaker cable

YES

Is the output of IC300(pin52,53) normal?

Replace IC300 NO

YES

Replace IC400 NO

YES

Check the signal after IC300 refer to circuit diagram

YES

IC400 operate normally?

IC401 operate normally?

Replace IC401 NO

YES Only RF is no Sound?

IC402 operate normally?

Check the Tuner In/Out NO

Replace IC402 NO

YES

Replace VSC B/D

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Trouble Shooting Guide 19. HDMI mode

Is normal only video ?

Yes

Download EDID data each port. 1. Check TV input mode. (HDMI1 port support HDMI and DVI. So if you input DVI signal and PC audio from phone jack, You can hear PC audio. ) 2. Unplug and plug HDMI cable. (sometimes ESD surge occurred at HDMI port.) 3. Check HDMI Mute register. (0x68, offset 0x37) 4. Check Audio-out channel mute register (0x68, offset 0x32) is appropriately enabled.

No Is normal only audio?

Yes

No Check TMDS line wave. (R1215 ~ R1222/ R1226 ~ R1233)

Is wave continuous?

Check HDMI source. Change another source or cable.

Yes 1. Check HDMI receiver’s status register. (0x60, offset 0x06) If the value is 0xf or 0x8, it is normal. 2. Check HDCP register. (0x60, offset 0x32) Enable bit 6: HDCP key loaded Enable bit 5: HDCP decryption active Enable bit 4: HDCP authen. attempted

Reset TMDS power down/on register. - 0x60, offset 0x3f : 0xf7 => 0xff

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Normal video, Normal audio?

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Replace IC1200

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Gprobe5 Install & Download Guide

GProbe 5.2.0.2.exe

Install the GProbe Software from the Desktop using the GProbe 5.2.0.2.exe file.

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Gprobe5 Install & Download Guide

CGProbe Redistributable 5.2.0.4

After installing GProbe 5.2.0.2 install the CGProbe from CGProbe Redistributable 5.2.0.4.exe as shown in the figure.

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Gprobe5 Install & Download Guide

GProbe 5

Select the Icon named GProbe 5 Tool for downloading the software in T.V. from the desktop.

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Gprobe5 Install & Download Guide

Help Menu

Verify the GProbe UI Version: 5.2.02 and CGProbe Version: 5.2.0.4 from the Help menu under About GProbe.. .

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Gprobe5 Install & Download Guide

Connection Settings

Select Chip:

Choose the appropriate chip from Select Chip: FLI8638 Check Connection settings.

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Gprobe5 Install & Download Guide

Set the Connections as shown in figure: Device: Serial Protocols: SERIAL1 Scheme: Serial connection for all Genesis Chips Great Company Great People

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Gprobe5 Install & Download Guide

Set the Connections as shown in figure: Port: COM1 Data Bits: 8 Baud Rate: 115200 Parity: None Stop Bits: 1 Great Company Great People

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Gprobe5 Install & Download Guide

Set the Connections as shown in figure: Port: 0x378 Clock Frequency: 60000 Hz Scheme: Standard Speed LPT1(0x378) Great Company Great People

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Gprobe5 Install & Download Guide

Set the Connections as shown in figure: I/p Pin: 15(active high) SDA Signal I/p Pin: 11(active high) Scheme: Default Pin Assignments Great Company Great People

O/p Pin: 17(active high) SDA Signal O/p Pin: 9 (active high)

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Gprobe5 Install & Download Guide

Set the Connections as shown in figure: Scheme: Default USB Setting Great Company Great People

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Gprobe5 Install & Download Guide

Set the Connections as shown in figure: Short Timeout: 1000 ms Address: 4096 Scheme: Default Setting Great Company Great People

Long Timeout: 15000 ms Size: 4096

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Gprobe5 Install & Download Guide

Select the “Commands” Option and then select the “Batch” option to locate the Path from where the “.text file” has to be downloaded which contains the information regarding the location of final “.hex file”.

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Gprobe5 Install & Download Guide

browse

Browse the .txt file from its specified location in the directory such as: C:\clearcase_rohit\rohit_view2\CC_HURRICANE3_H\10_Source\FLI8668\Isp\b atch\CORTEZ_A.txt Great Company Great People

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Gprobe5 Install & Download Guide

After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for downloading the software other wise it generate an Error. RS232 Host: Gprobe. Baud Rate: 115200bps(T.V in Power on state)/9600bps (T.V in stand by Power off).

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Gprobe5 Install & Download Guide

After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for downloading the software other wise it generate an Error. Error: Timeout while waiting for Response.

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Gprobe5 Install & Download Guide

If the connections between T.V Board and C.P.U are not proper or T.V is not in the GProbe mode it will give “Error Message” as shown in figure. Error Message: Timeout while waiting for Response. So Check the connection properly and GProbe condition & again Start Downloading.

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Gprobe5 Install & Download Guide

After Downloading complete its shows : Execution time: XXX.XX second (~~Approx) Batch: Command Successful.

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Gprobe5 Install & Download Guide

After Downloading complete its shows : Execution time: XXX.XX second (~~Approx) Batch: Command Successful.

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Gprobe5 Debugging GPIO port debugging

appstest 0 input appstest funtion help

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Gprobe5 Debugging Register Bit Types

After value change, Input 0xe000 = 0xff in command window è Execute (Real value change)

After value change, è Directly Real value change

PAA,CRW,CRO,RO,WO type è We could not change the register value using the Gprobe5

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Gprobe5 Debugging IC control Example EEPROM initialization (Except adjustment Data)

appstest 1 0

EEPROM initialization (Include adjustment Data)

appstest 1 99

EEPROM Specific address value : Byte read

appstest 22 Addr

EEPROM Specific address

appstest 21 Addr Data

EEPROM

HDMI

MSP

: Byte write

EEPROM Specific address value : Word read

appstest 24 Addr

EEPROM Specific address

appstest 23 Addr Data

: Word write

HDMI initialization

appstest 4

HDMI Specific register : value read

appstest 75 SubAddr Addr

HDMI Specific register : value write

appstest 76 SubAddr Addr Data

MSP initialization

appstest 33

MSP Specific register : value read

appstest 32 Addr1 Addr2

MSP Specific register : value write

appstest 31 Addr1 Addr2 Data

CXA2069 register : write

appstest 60 Main Pip MonitorOut

CXA2069 Status : read

appstest 61

CXA2069

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EDID data Download Guide. 1.

Required Test Equipment

1) Adjusting PC with S/W for writing EDID Data.(S/W : EDID TESTER Ver.2.5) 2) A Jig for EDID Download 3) Cable : Serial(9Pin or USB) to D-sub 15Pin cable, D-sub 15Pin cable, DVI to HDMI cable. 2. Setting of the device

Connection Diagram of DDC download

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EDID data Download Guide. 3. Preparation for Adjustment 1) As above Fig. 5, Connect the Set, EDID Download Jig,, PC & Cable 2) Turn on the PC & EDID Download Jig. And Execute the S/W : EDID TESTER Ver.2.5 3) Set up the S/W option .

Repeat Number : 5 Device Address : A0 PageByte : 8

4) Power on the Set

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EDID data Download Guide. 4. Example Data of EDID(42PC1R-ZH) 1) 42PC1R-ZH DDC data of Analog-RGB (Check Sum : CE )

[BLOCK0]

2) 42PC1R-ZH DDC data of Digital_HDMI (Check Sum : 0B2B)

[BLOCK0]

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[BLOCK1]

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EDID data Download Guide. 5. Sequence of Adjustment 1) Init the data 2) Load the EDID data.( Open File : Analog ,Digital) 3) Push the “Write Data & Verify” button. And confirm “Yes”. 4) If the writing is finished, you will see the “ OK” message 5) It is important that PP62A/C has two HDMI so digital DDC downloading must be performed two times(HDMI 1 , HDMI 2)

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Document

Owner’s Manual Module CAS

Owner's manual _ EU

42X3_PDP

Circuit Diagram Adjustment UI Specification Area Option Table

Gprobe5

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Owner's manual _ Non EU

50X3_PDP

Circuit Diagram_VSC

32LCD_LPL

Circuit Diagram _ Local key

37LCD_LPL

Circuit Diagram _ PreAMP

42LCD_LPL

37LCD_AUO

Circuit Diagram _ Side AV

Adj_UI Specification

LCD H3 High Option Table

GProbe5.2.0.2

PDP H3 High Option Table

CGProbe5.2.0.4

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