Manual de serviço televisores philips modelos 32pfl3606d e 40pfl3606d chassis l11m1 1l by Portal da Eletrônica

Published by ER/JY 1164 BU TV Consumer Care

Printed in the Netherlands

ÂŠ Copyright 2011 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.

66 67

42 43 45 46 50 52 56 57 59 65

35 36 37 38 39 40 41

Page 2 2 4 8 12 18 20 26

1. 2. 3. 4. 5. 6. 7. 8. 9.

Revision List Technical Specifications and Connections Precautions, Notes, and Abbreviation List Mechanical Instructions Service Modes, Error Codes, and Fault Finding Alignments Circuit Descriptions IC Data Sheets Block Diagrams Wiring Diagram 32" (Thriller) Wiring Diagram 40" (Thriller) Block Diagram Video Block Diagram Audio Block Diagram Control & Clock Signals Block Diagram I2C Supply Lines Overview 10. Circuit Diagrams and PWB Layouts B01 393912365052 B02 393912365052 B03 393912365052 B04 393912365052 B05 393912365052 B06 393912365052 B07 393912365052 313912365052 SSB Layout T01 393912365071 313912365071 TCON Layout 11. Styling Sheets Styling Sheet Thriller 32" Styling Sheet Thriller 40"

Contents

Colour Television

Subject to modification

2011-Apr-29

EN 3122 785 19130

19130_000_110421.eps 110421

L11M1.1L

Chassis

L11M1.1L LA

Revision List

DIGITAL AUDIO OUT

SERV.U

Pr CVI 2

ANTENNA

AUDIO IN DVI/VGA

2.2

2.3.1

Styling

3122 785 19130

Published in:

VGA

1 - USB2.0 2

4 10000_022_090121.eps 090121

Figure 2-2 USB (type A)

Side Connections

19130_001_110421.eps 110421

SIDE CONNECTORS

You can download this information from the following websites: http://www.philips.com/support http://www.p4c.philips.com

Directions for Use

40PFL3606D/78

32PFL3606D/78 Thriller

CTN

Table 2-1 Described Model numbers

Figure 2-1 Connection overview

HDMI 1 (ARC)

Note: The following connector colour abbreviations are used (according to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow.

BOTTOM REAR CONNECTORS

CVI 1

REAR CONNECTORS

Connections

For on-line product support please use the links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.

Technical Specifications

2011-Apr-29

2.3

2.1

Notes: • Figures can deviate due to the different set executions. • Specifications are indicative (subject to change).

Index of this chapter: 2.1 Technical Specifications 2.2 Directions for Use 2.3 Connections

2. Technical Specifications and Connections

Manual xxxx xxx xxxx.0 • First release.

1. Revision List

EN 2

2.3.3

2.3.2

- +5V - Data (-) - Data (+) - Ground Gnd

- D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink - n.c. - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground j jk H j j H DDC clock DDC data Gnd

8 - CVI-2: Cinch: Video YPbPr - In, Audio - In Wh - Audio - L 0.5 VRMS / 10 kΩ Rd - Audio - R 0.5 VRMS / 10 kΩ Rd - Video Pr 0.7 VPP / 75 Ω Bu - Video Pb 0.7 VPP / 75 Ω Gn - Video Y 1 VPP / 75 Ω

Bottom Connections

7 - Mini Jack: Audio - In DVI/VGA Bk - Audio 0.5 VRMS / 10 kΩ

jq jq jq jq jq

H k j

5 - Cinch: Digital Audio - Out Bk - Coaxial 0.4 - 0.6VPP / 75 ohm 6 - Service Connector (UART) 1 - Ground Gnd 2 - UART_TX Transmit 3 - UART_RX Receive

jq jq jq jq jq

4 - CVI-1: Cinch: Video YPbPr - In, Audio - In Wh - Audio - L 0.5 VRMS / 10 kΩ Rd - Audio - R 0.5 VRMS / 10 kΩ Rd - Video Pr 0.7 VPP / 75 Ω Bu - Video Pb 0.7 VPP / 75 Ω Gn - Video Y 1 VPP / 75 Ω

Hot Plug Detect Gnd

j H j j H j j H j j H j jk

jq jq jq

k jk jk H

Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel/CEC

Figure 2-3 HDMI (type A) connector

Rear Connections

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

1 2

10000_017_090121.eps 090428

19 18

3 - HDMI: Digital Video, Digital Audio - In

2 - AV IN: Cinch: Video CVBS - In, Audio - In Ye - Video CVBS 1 VPP / 75 ohm Wh - Audio L 0.5 VRMS / 10 kohm Rd - Audio R 0.5 VRMS / 10 kohm

1 2 3 4

L11M1.1L LA

- D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink - ARC - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

5 10 15

- Video Red - Video Green - Video Blue - n.c. - Ground - Ground Red - Ground Green - Ground Blue - +5VDC - Ground Sync - n.c. - DDC_SDA - H-sync - V-sync - DDC_SCL

H H H H j H j j j j

Gnd Gnd Gnd Gnd +5 V Gnd DDC data 0-5V 0-5V DDC clock

2011-Apr-29

j j j

j H j j H j j H j j H j jk j j jk H j j H

EN 3

0.7 VPP / 75 Ω 0.7 VPP / 75 Ω 0.7 VPP / 75 Ω

Figure 2-5 VGA Connector

10000_002_090121.eps 090127

11 - VGA: Video RGB - In

Coax, 75 Ω

Hot Plug Detect Gnd

Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel/CEC Audio Return Channel DDC clock DDC data Gnd

Figure 2-4 HDMI (type A) connector

10 - Aerial - In - - F-type

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

1 2

10000_017_090121.eps 090428

19 18

9 - HDMI1: Digital Video, Digital Audio - In

Technical Specifications and Connections

L11M1.1L LA

Precautions, Notes, and Abbreviation List

2011-Apr-29

•

Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).

General

3.3.1

All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential. Be careful during measurements in the high voltage section. Never replace modules or other components while the unit is switched “on”. When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.

Notes

•

Warnings

Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points: • Route the wire trees correctly and fix them with the mounted cable clamps. • Check the insulation of the Mains/AC Power lead for external damage. • Check the strain relief of the Mains/AC Power cord for proper function. • Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply): 1. Unplug the Mains/AC Power cord and connect a wire between the two pins of the Mains/AC Power plug. 2. Set the Mains/AC Power switch to the “on” position (keep the Mains/AC Power cord unplugged!). 3. Measure the resistance value between the pins of the Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 MΩ and 12 MΩ. 4. Switch “off” the set, and remove the wire between the two pins of the Mains/AC Power plug. • Check the cabinet for defects, to prevent touching of any inner parts by the customer.

Safety regulations require the following during a repair: • Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA). • Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard.

Safety Instructions

3.3

3.2

3.1

Index of this chapter: 3.1 Safety Instructions 3.2 Warnings 3.3 Notes 3.4 Abbreviation List

3.3.6

3.3.5

3.3.4

3.3.3

3.3.2

Where necessary, measure the waveforms and voltages with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 kΩ). Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω). All capacitor values are given in micro-farads (μ = × 10-6), nano-farads (n = × 10-9), or pico-farads (p = × 10-12). Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF). An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values. The correct component values are listed on the Philips Spare Parts Web Portal.

It should be noted that on the European Service website, “Alternative BOM” is referred to as “Design variant”.

Alternative BOM identification

Due to lead-free technology some rules have to be respected by the workshop during a repair: • Use only lead-free soldering tin. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle. • Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: – To reach a solder-tip temperature of at least 400°C. – To stabilize the adjusted temperature at the solder-tip. – To exchange solder-tips for different applications. • Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat. • Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.

Lead-free Soldering

BGA Temperature Profiles For BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.

Introduction For more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com. Select “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs.

BGA (Ball Grid Array) ICs

For the latest spare part overview, consult your Philips Spare Part web portal.

Spare Parts

•

Schematic Notes

•

3. Precautions, Notes, and Abbreviation List

EN 4

3.3.8

3.3.7

•

It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard. Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a

Practical Service Precautions

If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging!

Board Level Repair (BLR) or Component Level Repair (CLR)

Figure 3-1 Serial number (example)

10000_053_110228.eps 110228

Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2010 week 10 / 2010 week 17). The 6 last digits contain the serial number.

The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts! For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.

3.4

L11M1.1L LA

AARA

0/6/12

Abbreviation List

DDC

DCM

DAC DBE

CVBS

CLR ComPair CP CSM CTI

B-TXT C CEC

BDS BLR BTSC

AV AVC AVIP B/G

ATV Auto TV

ATSC

AM AP AR ASF

AGC

ADC AFC

ACI

EN 5

2011-Apr-29

SCART switch control signal on A/V board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format Automatic Aspect Ratio Adaptation: algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio Automatic Channel Installation: algorithm that installs TV channels directly from a cable network by means of a predefined TXT page Analogue to Digital Converter Automatic Frequency Control: control signal used to tune to the correct frequency Automatic Gain Control: algorithm that controls the video input of the feature box Amplitude Modulation Asia Pacific Aspect Ratio: 4 by 3 or 16 by 9 Auto Screen Fit: algorithm that adapts aspect ratio to remove horizontal black bars without discarding video information Advanced Television Systems Committee, the digital TV standard in the USA See Auto TV A hardware and software control system that measures picture content, and adapts image parameters in a dynamic way External Audio Video Audio Video Controller Audio Video Input Processor Monochrome TV system. Sound carrier distance is 5.5 MHz Business Display Solutions (iTV) Board-Level Repair Broadcast Television Standard Committee. Multiplex FM stereo sound system, originating from the USA and used e.g. in LATAM and AP-NTSC countries Blue TeleteXT Centre channel (audio) Consumer Electronics Control bus: remote control bus on HDMI connections Constant Level: audio output to connect with an external amplifier Component Level Repair Computer aided rePair Connected Planet / Copy Protection Customer Service Mode Color Transient Improvement: manipulates steepness of chroma transients Composite Video Blanking and Synchronization Digital to Analogue Converter Dynamic Bass Enhancement: extra low frequency amplification Data Communication Module. Also referred to as System Card or Smartcard (for iTV). See “E-DDC”

powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.

Precautions, Notes, and Abbreviation List

2011-Apr-29

I2 C I2 D I2 S IF IR IRQ ITU-656

HDMI HP I

FPGA FTV Gb/s G-TXT H HD HDD HDCP

FDS FDW FLASH FM

EMI EPG EPLD EU EXT

EEPROM

EDID

DVB-C DVB-T DVD DVI(-d) E-DDC

DTCP

DRAM DRM DSP DST

DFI DFU DMR DMSD DNM DNR

D/K

EN 6

P50

OTC

O/C OSD OAD

NVM

NTSC

NTC

NC NICAM

MPEG MPIF MUTE MTV

MOP MOSFET

MIPS

MHEG

LPL LS LVDS Mbps M/N

LATAM LCD LED L/L'

iTV

Precautions, Notes, and Abbreviation List

Monochrome TV system. Sound carrier distance is 6.5 MHz Dynamic Frame Insertion Directions For Use: owner's manual Digital Media Reader: card reader Digital Multi Standard Decoding Digital Natural Motion Digital Noise Reduction: noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool: special remote control designed for service technicians Digital Transmission Content Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394 Digital Video Broadcast - Cable Digital Video Broadcast - Terrestrial Digital Versatile Disc Digital Visual Interface (d= digital only) Enhanced Display Data Channel (VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display. Extended Display Identification Data (VESA standard) Electrically Erasable and Programmable Read Only Memory Electro Magnetic Interference Electronic Program Guide Erasable Programmable Logic Device Europe EXTernal (source), entering the set by SCART or by cinches (jacks) Full Dual Screen (same as FDW) Full Dual Window (same as FDS) FLASH memory Field Memory or Frequency Modulation Field-Programmable Gate Array Flat TeleVision Giga bits per second Green TeleteXT H_sync to the module High Definition Hard Disk Drive High-bandwidth Digital Content Protection: A “key” encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a “snow vision” mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP “software key” decoding. High Definition Multimedia Interface HeadPhone Monochrome TV system. Sound carrier distance is 6.0 MHz Inter IC bus Inter IC Data bus Inter IC Sound bus Intermediate Frequency Infra Red Interrupt Request The ITU Radio communication Sector (ITU-R) is a standards body

L11M1.1L LA subcommittee of the International Telecommunication Union relating to radio communication. ITU-656 (a.k.a. SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz. Institutional TeleVision; TV sets for hotels, hospitals etc. Last Status; The settings last chosen by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's preferences Latin America Liquid Crystal Display Light Emitting Diode Monochrome TV system. Sound carrier distance is 6.5 MHz. L' is Band I, L is all bands except for Band I LG.Philips LCD (supplier) Loudspeaker Low Voltage Differential Signalling Mega bits per second Monochrome TV system. Sound carrier distance is 4.5 MHz Part of a set of international standards related to the presentation of multimedia information, standardised by the Multimedia and Hypermedia Experts Group. It is commonly used as a language to describe interactive television services Microprocessor without Interlocked Pipeline-Stages; A RISC-based microprocessor Matrix Output Processor Metal Oxide Silicon Field Effect Transistor, switching device Motion Pictures Experts Group Multi Platform InterFace MUTE Line Mainstream TV: TV-mode with Consumer TV features enabled (iTV) Not Connected Near Instantaneous Compounded Audio Multiplexing. This is a digital sound system, mainly used in Europe. Negative Temperature Coefficient, non-linear resistor National Television Standard Committee. Color system mainly used in North America and Japan. Color carrier NTSC M/N= 3.579545 MHz, NTSC 4.43= 4.433619 MHz (this is a VCR norm, it is not transmitted off-air) Non-Volatile Memory: IC containing TV related data such as alignments Open Circuit On Screen Display Over the Air Download. Method of software upgrade via RF transmission. Upgrade software is broadcasted in TS with TV channels. On screen display Teletext and Control; also called Artistic (SAA5800) Project 50: communication protocol between TV and peripherals

S/PDIF SRAM SRP SSB

SIF SMPS SoC SOG SOPS SPI

SCL SCL-F SD SDA SDA-F SDI SDRAM SECAM

R-TXT SAM S/C SCART

RESET ROM RSDS

RC RC5 / RC6

PWB PWM QRC QTNR QVCP RAM RGB

PTC

PSLS

PSL

POR PSDL

POD

PIP PLL

PCB PCM PDP PFC

PAL

Phase Alternating Line. Color system mainly used in West Europe (colour carrier = 4.433619 MHz) and South America (colour carrier PAL M = 3.575612 MHz and PAL N = 3.582056 MHz) Printed Circuit Board (same as “PWB”) Pulse Code Modulation Plasma Display Panel Power Factor Corrector (or Preconditioner) Picture In Picture Phase Locked Loop. Used for e.g. FST tuning systems. The customer can give directly the desired frequency Point Of Deployment: a removable CAM module, implementing the CA system for a host (e.g. a TV-set) Power On Reset, signal to reset the uP Power Supply for Direct view LED backlight with 2D-dimming Power Supply with integrated LED drivers Power Supply with integrated LED drivers with added Scanning functionality Positive Temperature Coefficient, non-linear resistor Printed Wiring Board (same as “PCB”) Pulse Width Modulation Quasi Resonant Converter Quality Temporal Noise Reduction Quality Video Composition Processor Random Access Memory Red, Green, and Blue. The primary color signals for TV. By mixing levels of R, G, and B, all colors (Y/C) are reproduced. Remote Control Signal protocol from the remote control receiver RESET signal Read Only Memory Reduced Swing Differential Signalling data interface Red TeleteXT Service Alignment Mode Short Circuit Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs Serial Clock I2C CLock Signal on Fast I2C bus Standard Definition Serial Data I2C DAta Signal on Fast I2C bus Serial Digital Interface, see “ITU-656” Synchronous DRAM SEequence Couleur Avec Mémoire. Colour system mainly used in France and East Europe. Colour carriers = 4.406250 MHz and 4.250000 MHz Sound Intermediate Frequency Switched Mode Power Supply System on Chip Sync On Green Self Oscillating Power Supply Serial Peripheral Interface bus; a 4wire synchronous serial data link standard Sony Philips Digital InterFace Static RAM Service Reference Protocol Small Signal Board YUV

YPbPr

WXGA XTAL XGA Y Y/C

WYSIWYR

VSB

VGA VL

TS TXT TXT-DW UI uP UXGA V VESA

SXGA TFT THD TMDS

STB STBY SVGA SVHS SW SWAN

SSC

Precautions, Notes, and Abbreviation List 3.

EN 7

2011-Apr-29

Spread Spectrum Clocking, used to reduce the effects of EMI Set Top Box STand-BY 800 × 600 (4:3) Super Video Home System Software Spatial temporal Weighted Averaging Noise reduction 1280 × 1024 Thin Film Transistor Total Harmonic Distortion Transmission Minimized Differential Signalling Transport Stream TeleteXT Dual Window with TeleteXT User Interface Microprocessor 1600 × 1200 (4:3) V-sync to the module Video Electronics Standards Association 640 × 480 (4:3) Variable Level out: processed audio output toward external amplifier Vestigial Side Band; modulation method What You See Is What You Record: record selection that follows main picture and sound 1280 × 768 (15:9) Quartz crystal 1024 × 768 (4:3) Luminance signal Luminance (Y) and Chrominance (C) signal Component video. Luminance and scaled color difference signals (B-Y and R-Y) Component video

L11M1.1L LA

Mechanical Instructions

Cable Dressing

2011-Apr-29

4.1

Index of this chapter: 4.1 Cable Dressing 4.2 Service Positions 4.3 Assy/Panel Removal 4.4 Set Re-assembly

19130_002_110421.eps 110421

Notes: â&#x20AC;˘ Figures below can deviate slightly from the actual situation, due to the different set executions.

Figure 4-1 Cable dressing 32"

4. Mechanical Instructions

EN 8

11 mm saddle × 1 150 mm tape × 3 70 mm tape × 4 Foam × 2

Figure 4-2 Cable dressing 40"

Mechanical Instructions L11M1.1L LA

EN 9

2011-Apr-29

19130_003_110426.eps 110426

L11M1.1L LA

Mechanical Instructions

1 1

19130_004_110426.eps 110426

measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.

Figure 4-3 Rear cover removal (40")

Warning: Disconnect the mains power cord before removing the rear cover. See Figure 4-3. 1. Remove fixation screws [2] and [3] that secure the rear cover. It is not necessary to remove the stand first [1]. 2. Lift the rear cover from the TV. Make sure that wires and flat foils are not damaged while lifting the rear cover from the set.

2 3

Rear Cover

Instructions below apply to the 40PFL3606D/78, but will be similar for other models.

Assy/Panel Removal

For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform

Service Positions

2011-Apr-29

4.3.1

4.3

4.2

EN 10

4.4

4.3.2

C 1

2 1

B 1 2 1

4. 5. 6. 7.

Notes: â&#x20AC;˘ While re-assembling, make sure that all cables are placed and connected in their original position. See Figure 4-5 â&#x20AC;˘ Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly.

EN 11

A 1

2 1

19130_006_110426.eps 110426

2011-Apr-29

19130_007_110426.eps 110426

Improper FFC insertion: Silver line is visible when connector lock is closed

Proper FFC insertion: Silver line is not visible when connector lock is closed

Figure 4-5 Flat Foil Cable (FFC) precautions

Thicker blue FFC supporting tape belong to SSB side

TCON

Thinner blue FFC supporting tape belong to Panel side

Panel

Remove the IR/LED board [F]. Remove the Local Control board [G]. Remove the clamps [1]. Remove all metal subframes [2] that do not belong to the LCD display.

L11M1.1L LA

Figure 4-4 LCD Panel removal (based on 40" model)

To re-assemble the whole set, execute all processes in reverse order.

Set Re-assembly

Refer to Figure 4-4 for details. 1. Remove the Stand [A]. 2. Remove the Speakers/Subwoofer [B]. 3. Remove the PSU [C], SSB [D] and TCON (E).

LCD Panel

Mechanical Instructions

L11M1.1L LA

Service Modes, Error Codes, and Fault Finding

ComPair Mode is used for communication between a computer and a TV on I2C /UART level and can be used by a Service engineer to quickly diagnose the TV set by reading out error codes, read and write in NVMs, communicate with ICs and the uP (PWM, registers, etc.), and by making use of a fault finding database. It will also be possible to up and download the software of the TV set via I2C with help of ComPair. To do this, ComPair has to be connected to the TV set via the ComPair connector, which will be accessible through the rear of the set (without removing the rear cover).

The CSM is a Service Mode that can be enabled by the consumer. The CSM displays diagnosis information, which the customer can forward to the dealer or call centre. In CSM mode, “CSM”, is displayed in the top right corner of the screen. The information provided in CSM and the purpose of CSM is to: • Increase the home repair hit rate. • Decrease the number of nuisance calls. • Solved customers' problem without home visit.

SDM and SAM offer features, which can be used by the Service engineer to repair/align a TV set. Some features are: • A pre-defined situation to ensure measurements can be made under uniform conditions (SDM). • Activates the blinking LED procedure for error identification when no picture is available (SDM). • The possibility to overrule software protections when SDM is entered via the Service pins. • Make alignments (e.g. White Tone), (de)select options, enter options codes, reset the error buffer (SAM). • Display information (“SDM” or “SAM” indication in upper right corner of screen, error buffer, software version, operating hours, options and option codes, sub menus).

The Service Mode feature is split into four parts: • Service Default Mode (SDM). • Service Alignment Mode (SAM). • Customer Service Mode (CSM). • Computer Aided Repair Mode (ComPair).

Service Modes

Perform measurements under the following conditions: • Service Default Mode. • Video: Colour bar signal. • Audio: 3 kHz left, 1 kHz right.

In the chassis schematics and layout overviews, the test points are mentioned. In the schematics and layouts, test points are indicated with “Fxxx” or “Ixxx”. As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. Several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective.

Test Points

2011-Apr-29

5.2

5.1

Index of this chapter: 5.1 Test Points 5.2 Service Modes 5.3 Service Tools 5.4 Error Codes 5.5 The Blinking LED Procedure 5.6 Fault Finding and Repair Tips 5.7 Software Upgrading 5.2.1

040

10000_038_090121.eps 090819

During this algorithm, the NVM-content must be filtered, because several items in the NVM are TV-related and not SSBrelated (e.g. Model and Prod. S/N). Therefore, “Model” and “Prod. S/N” data is changed into “See Type Plate”. In case a call centre or consumer reads “See Type Plate” in CSM mode, he needs to look to the side/bottom sticker to identify the set, for further actions.

Figure 5-1 Location of Display Option Code sticker

(CTN Sticker)

AG 1A0620 000001

PROD.SERIAL NO:

MODEL: 32PF9968/10

PHILIPS

39mm

Display Option Code

Display Option Code Selection When after an SSB or display exchange, the display option code is not set properly, it will result in a TV with “no display”. Therefore, it is required to set this display option code after such a repair. To do so, press the following key sequence on a standard RC transmitter: “062598” directly followed by MENU/HOME and “xxx”, where “xxx” is a 3 digit decimal value of the panel type, see sticker on the side/bottom of the cabinet. When the value is accepted and stored in NVM, the set will switch to Stand-by, to indicate that the process has been completed.

Software Identification, Version, and Cluster The software ID, version, and cluster will be shown in the main menu display of SDM, SAM, and CSM. The screen will show: “AAAAAAB-XX.YY”, where: • AAAAAA is the chassis name: L11M11. • B is the region indication: E= Europe, A= AP/China, U= NAFTA, L= LATAM. • XX is the main version number: this is updated with a major change of specification (incompatible with the previous software version). Numbering will go from 01 - 99 and AA ZZ. – If the main version number changes, the new version number is written in the NVM. – If the main version number changes, the default settings are loaded. • YY is the sub version number: this is updated with a minor change (backwards compatible with the previous versions) Numbering will go from 00 - 99. – If the sub version number changes, the new version number is written in the NVM. – If the NVM is fresh, the software identification, version, and cluster will be written to NVM.

Life Timer During the life time cycle of the TV set, a timer is kept (called “Op. Hour”). It counts the normal operation hours (not the Stand-by hours). The actual value of the timer is displayed in SDM and SAM in a decimal value. Every two soft-resets increase the hour by +1. Stand-by hours are not counted.

Next items are applicable to all Service Modes or are general.

General

5. Service Modes, Error Codes, and Fault Finding

EN 12

27mm

5.2.2

19130_008_110426.eps 110426

On Screen Menu After activating SDM, the following items are displayed, with “SDM” in the upper right corner of the screen to indicate that the television is in Service Default Mode. Menu items and explanation: • xxxxx: Operating hours (in decimal). • AAAAAAB-XX.YY: See paragraph Software Identification, Version, and Cluster for the SW name definition.

Figure 5-2 Service pads (SSB component side)

SDM

How to Activate To activate analogue SDM, use one of the following methods: • Press the following key sequence on the RC transmitter: “062596” directly followed by the MENU button. • Short one of the “Service” pads on the TV board during cold start (see Figure 5-2). Then press the mains button (remove the short after start-up). Caution: When doing this, the service-technician must know exactly what he is doing, as it could damage the television set. To activate digital SDM: • Press the following sequence on the RC transmitter: “062593” directly followed by the MENU button.

Specifications • Set linear video and audio settings to 50%, but volume to 25%. Stored user settings are not affected. • Set Smart Picture to “Game”. • Set Smart Sound to “Standard”. • Tune channel to: - for analogue SDM: channel 3 (61.25 MHz) - for digital SDM: channel 26 (545.143 MHz). • For digital SDM: set PID default from the stream. • All service-unfriendly modes (if present) are disabled, since they interfere with diagnosing/repairing a set. These service unfriendly modes are: – (Sleep) timer. – Blue mute/Wall paper. – Auto switch “off” (when there is no “ident” signal). – Hotel or hospital mode. – Child lock or parental lock (manual or via V-chip). – Skipping, blanking of “Not favourite”, “Skipped” or “Locked” presets/channels. – Automatic storing of Personal Preset or Last Status settings. – Automatic user menu time-out (menu switches back/ OFF automatically. – Auto Volume levelling (AVL).

Purpose Set the TV in SDM mode in order to be able to create a predefined setting for measurements to be made. In this platform, a simplified SDM is introduced (without protection override and without tuning to a predefined frequency).

Service Default Mode (SDM)

5.2.3

EN 13

ERR: Shows all errors detected since the last time the buffer was erased in format <xxx> <xxx> <xxx> <xxx> <xxx> (five errors possible). OP: Used to read-out the option bytes. Ten codes (in two rows) are possible.

L11M1.1L LA

2011-Apr-29

After entering SAM, the following items are displayed, with “SAM” in the upper right corner of the screen to indicate that the television is in Service Alignment Mode.

How to Activate To activate SAM, use one of the following methods: • Press the following key sequence on the remote control transmitter: “062596” directly followed by the INFO[i+] /OK button. Do not allow the display to time out between entries while keying the sequence. • Or via ComPair.

Specifications • Operation hours counter (maximum five digits displayed). • Software version, error codes, and option settings display. • Error buffer clearing. • Option settings. • Software alignments (White Tone). • NVM Editor. • Set screen mode to full screen (all content is visible). • Set Smart Picture to “Game”.

Purpose • To change option settings. • To display / clear the error code buffer. • To perform alignments.

Service Alignment Mode (SAM)

Note: • If the TV is switched “off” by a power interrupt while in SDM, the TV will show up in the last status of SDM menu as soon as the power is supplied again. The error buffer will not be cleared. • In case the set is accidentally in Factory mode (with an “F” displayed on the screen), pressing and holding “VOL-“ button for 5 seconds and then followed by pressing and holding the “CH-” button for another 5 seconds should exit the Factory mode.

How to Exit Switch the set to Stand-by by • pressing the standby button on the remote control transmitter or on the television set, or • via a standard RC-transmitter by keying the “00” sequence. If you switch the television set “off” by removing the mains (i.e., unplugging the television), the television set will remain in SDM when mains is re-applied, and the error buffer is not cleared. The error buffer will only be cleared when the “clear” command is used in the SAM menu.

How to Navigate As this mode is read only, there is not much to navigate. To switch to other modes, use one of the following methods: • Command MENU from the user remote will enter the normal user menu (brightness, contrast, color, etc...) with “SDM” OSD remaining, and pressing MENU key again will return to the last status of SDM again. • To prevent the OSD from interfering with measurements in SDM, command “OSD” or “i+” (“STATUS” or “INFO” for NAFTA and LATAM) from the user remote will toggle the OSD “on/off” with “SDM” OSD remaining always “on”. • Press the following key sequence on the remote control transmitter: “062596” directly followed by the INFO[i+]/OK button to switch to SAM (do not allow the display to time out between entries while keying the sequence).

•

Service Modes, Error Codes, and Fault Finding

L11M1.1L LA

2011-Apr-29

Note: • When the TV is switched “off” by a power interrupt while in SAM, the TV will show up in “normal operation mode” as

How to Exit Switch the set to STANDBY by pressing the mains button on the remote control transmitter or the television set, or by keying-in the “00” sequence on a standard RC-transmitter.

How to Store SAM Settings To store the settings changed in SAM mode (except the OPTIONS and RGB ALIGN settings), leave the top level SAM menu by using the POWER button on the remote control transmitter or the television set. The mentioned exceptions must be stored separately via the STORE button.

How to Navigate • In the SAM menu, select menu items with the UP/DOWN keys on the remote control transmitter. The selected item will be indicated. When not all menu items fit on the screen, use the UP/DOWN keys to display the next / previous menu items. • With the LEFT/RIGHT keys, it is possible to: – Activate the selected menu item. – Change the value of the selected menu item. – Activate the selected sub menu. • When you press the MENU button twice while in top level SAM, the set will switch to the normal user menu (with the SAM mode still active in the background). To return to the SAM menu press the MENU button. • The “INFO[i+]/OK” key from the user remote will toggle the OSD “on/off” with “SAM” OSD remaining always “on”. • Press the following key sequence on the remote control transmitter: “062596” directly followed by the MENU button to switch to SDM (do not allow the display to time out between entries while keying the sequence).

5.2.4

Menu Explanation CSM3 1. Signal Quality. Shows the signal quality (No Tuned/Poor/ Average/Good). 2. Child lock. This is a combined item for locks. If any lock (Preset lock, child lock, lock after, or Parental lock) is active, this item indicates “active”.

Menu Explanation CSM2 1. Current Main SW. Shows the main software version. 2. Standby SW. Shows the Stand-by software version. 3. Panel Code. Shows the current display code. 4. Bootloader ID. Shows the Bootloader software ID. 5. NVM Version. The NVM software version no. 6. Flash ID. Shows the flash ID.

(*) If an NVM IC is replaced or initialized, these items must be re-written to it. ComPair will foresee in a possibility to do this. Also the NVM editor in the SAM menu can be used.

Menu Explanation CSM1 1. Set Type. Type number, e.g. 32PFL3605/78. (*) 2. Production code. Product serial no., e.g. BZ1A1008123456 (*). BZ= Production centre, 1= BOM code, A= Service version change code, 10= Production year, 08= Production week, 123456= Serial number. 3. Installation date. Indicates the date of the first initialization of the TV. This date is acquired via time extraction. 4. a - Option Code 1. Option code information (group 1). b - Option Code 2. Option code information (group 2). 5. SSB. Indication of the SSB factory ID (= 12nc). (*) 6. Display. Indication of the display ID (=12 nc). (*) 7. PSU. Indication of the PSU factory ID (= 12nc).

After entering the Customer Service Mode, the following items are displayed:

How to Activate To activate CSM, press the following key sequence on a standard remote control transmitter: “123654” (do not allow the display to time out between entries while keying the sequence).

Specifications • Ignore “Service unfriendly modes”. • Set volume to 25%. • Set Smart Picture to “Game”. • Set Smart Sound to “Standard”. • Line number for every line (to make CSM language independent). • Set the screen mode to full screen (all contents on screen is visible). • After leaving the Customer Service Mode, the original settings are restored. • Possibility to use “CH+” or “CH-” for channel surfing, or enter the specific channel number on the RC.

Purpose The Customer Service Mode shows error codes and information on the TV’s operation settings. A call centre can instruct the customer (by telephone) to enter CSM in order to identify the status of the set. This helps them to diagnose problems and failures in the TV before making a service call. The CSM is a read-only mode; therefore, modifications are not possible in this mode.

Customer Service Mode (CSM)

•

soon as the power is supplied again. The error buffer will not be cleared. In case the set is in Factory mode by accident (with “F” displayed on screen), pressing and holding “VOL-“ button for 5 seconds and then followed by pressing and holding the “CH-” button for another 5 seconds should exit the Factory mode.

Service Modes, Error Codes, and Fault Finding

Menu items and explanation: 1. System Information. • Op Hour: This represents the life timer. The timer counts normal operation hours, but does not count Stand-by hours. • MAIN SW ID: See paragraph Software Identification, Version, and Cluster for the SW name definition. • ERR: Shows all errors detected since the last time the buffer was erased. Five errors possible. • OP1/OP2: Used to read-out the option bytes. See paragraph 6.6 Option Settings in the Alignments section for a detailed description. Ten codes are possible. 2. Tuner. • AGC Adjustment: See paragraph 6.3.1 for instructions. • Store: To store the data. 3. Clear. Erases the contents of the error buffer. Select this menu item and press the MENU RIGHT key on the remote control. The content of the error buffer is cleared. 4. Options. To set the option bits. See paragraph 6.6 Option Settings in the “Alignments” chapter for a detailed description. 5. RGB Align. To align the White Tone. See White Tone Alignment: for a detailed description. 6. NVM Editor. To change the NVM data in the television set. See also paragraph 5.6 Fault Finding and Repair Tips. 7. Upload to USB. 8. Download from USB. 9. Initialise NVM. To initialize a (corrupted) NVM. Be careful, this will erase all settings! 10. Auto ADC. Refer to chapter 6. Alignments for detailed information. 11. EDID Write Enable. Enables EDID writing (not applicable to Berlinale sets). 12. Service Data. Virtual Key board for character input entry.

EN 14

ComPair

5.3.1

How to Connect This is described in the ComPair chassis fault finding database.

Specifications ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The (new) ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s).

Introduction ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following: 1. ComPair helps you to quickly get an understanding on how to repair the chassis in a short and effective way. 2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. You do not have to know anything about I2C or UART commands yourself, because ComPair takes care of this. 3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the uP is working) and all repair information is directly available. 4. ComPair features TV software up possibilities.

Service Tools

5.3

How to Exit To exit CSM, use one of the following methods: • Press the MENU/HOME button on the remote control transmitter. • Press the POWER button on the remote control transmitter. • Press the POWER button on the television set.

Create a CSM dump on an USB stick There will be CSM dump to a plugged in USB-stick upon entering CSM-mode. An extended CSM dumpwill be created when the “OK” button on RC is pressed in CSM while a USB stick is plugged in. A direct CSM flash dump will be created when the buttons “red + 2679” on the remote control are pressed in CSM while a USB stick is plugged in.

3. HDCP Keys. Indicates if the HDMI keys (or HDCP keys) are valid or not. Not applicable to Berlinale series. 4. not used 5. not used 6. not used 7. not used. RC out

RS232 /UART

EN 15

Optional power 5V DC

10000_036_090121.eps 091118

ComPair II Developed by Philips Brugge

I2C

TO UART SERVICE CONNECTOR

Introduction

5.4.1

2011-Apr-29

Error codes are required to indicate failures in the TV set. In principle a unique error code is available for every: • Activated (SW) protection. • Failing I2C device. • General I2C error. The last five errors, stored in the NVM, are shown in the Service menu’s. This is called the error buffer. The error code buffer contains all errors detected since the last time the buffer was erased. The buffer is written from left to right. When an error occurs that is not yet in the error code buffer, it is displayed at the left side and all other errors shift one position to the right. An error will be added to the buffer if this error differs from any error in the buffer. The last found error is displayed on the left. An error with a designated error code never leads to a deadlock situation. It must always be diagnosable (e.g. error buffer via OSD or blinking LED or via ComPair). In case a failure identified by an error code automatically results in other error codes (cause and effect), only the error code of the MAIN failure is displayed.

Error Codes

5.4

Additional cables for VCOM Alignment • ComPair/I2C interface cable: 3122 785 90004. • ComPair/VGA adapter cable: 9965 100 09269.

Note: For this chassis, “Pgammar” and “T-con NVM” programming (VCOM alignment) are added to ComPair.

How to Order ComPair II order codes: • ComPair II interface: 3122 785 91020. • ComPair UART interface cable: 3138 188 75051. • Program software can be downloaded from the Philips Service web portal.

Caution: It is compulsory to connect the TV to the PC as shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs will be blown!

Figure 5-3 ComPair II interface connection

HDMI I2C only

TO TV TO I2C SERVICE CONNECTOR

Multi function

TO UART SERVICE CONNECTOR

L11M1.1L LA

Optional Power Link/ Mode Switch Activity

RC in

ComPair II

Service Modes, Error Codes, and Fault Finding

L11M1.1L LA

SSB SSB SSB SSB Display (Inverter)

3 2 2 2 2 4

Speaker DC protection active on SSB

LCD Panel inverter error. INV_STATUS (for 32” sets only)

Channel decoder on SSB

HDMI Mux IC I2C error on SSB - Berninale models with Mux only

Tuner I2C error on SSB

EEPROM I2C error on SSB, M24C16

POK line defective

+12 missing/low, PSU defective

Introduction

5.5.1

2011-Apr-29

Example (1): error code 4 will result in four times the sequence LED “on” for 0.25 seconds / LED “off” for 0.25 seconds. After this sequence, the LED will be “off” for 1.5 seconds. Any RC command terminates the sequence. Error code LED blinking is in red color.

Errors can also be displayed by the blinking LED procedure. The method is to repeatedly let the front LED pulse with as many pulses as the error code number, followed by a period of 1.5 seconds in which the LED is “off”. Then this sequence is repeated.

The software is capable of identifying different kinds of errors. Because it is possible that more than one error can occur over time, an error buffer is available, which is capable of storing the last five errors that occurred. This is useful if the OSD is not working properly.

The Blinking LED Procedure

Note: If you exit SAM by disconnecting the mains from the television set, the error buffer is not reset.

The error code buffer is cleared in the following cases: • By using the CLEAR command in the SAM menu: • By using the following key sequence on the remote control transmitter: “062599” directly followed by the OK button. • If the contents of the error buffer have not changed for 50 hours, the error buffer resets automatically.

How to Clear the Error Buffer

IPB/PSU

SSB IPB/PSU

Layer-2 error code Defective device

Layer-1 Defective error code board

Table 5-1 Error code table

The “layer 1” error codes are pointing to the defective board. They are triggered by LED blinking when CSM is activated. In the LC10 platform, only two boards are present: the SSB and the PSU/IPB, meaning only the following layer 1 errors are defined: • 2: SSB • 3: IPB/PSU • 4: Display

Error codes

5.6.2

5.6.1

5.6

5.5.2

Alternative method: It is also possible to upload the default values to the NVM with ComPair in case the SW is changed, the NVM is replaced with a new (empty) one, or when the NVM content is corrupted. After replacing an EEPROM (or with a defective/no EEPROM), default settings should be used to enable the set to start-up and allow the Service Default Mode and Service Alignment Mode to be accessed.

It is possible to download default values automatically into the NVM in case a blank NVM is placed or when the NVM first 20 address contents are “FF”. After the default values are downloaded, it is possible to start-up and to start aligning the TV set. To initiate a forced default download the following action has to be performed: 1. Switch “off” the TV set with the mains cord disconnected from the wall outlet (it does not matter if this is from “Standby” or “Off” situation). 2. Short-circuit the SDM pads on the SSB (keep short circuited, see Figure 5-2). 3. Press “P+” or “CH+” on the local keyboard (and keep it pressed). 4. Reconnect the mains supply to the wall outlet. 5. Release the “P+” or “CH+” when the set is started up and has entered SDM. When the downloading has completed successfully, the set will perform a restart. After this, put the set to Stand-by and remove the short-circuit on the SDM pads.

Load Default NVM Values

Caution: • Do not change these, without understanding the function of each setting, because incorrect NVM settings may seriously hamper the correct functioning of the TV set! • Always write down the existing NVM settings, before changing the settings. This will enable you to return to the original settings, if the new settings turn out to be incorrect.

In some cases, it can be convenient if one directly can change the NVM contents. This can be done with the “NVM Editor” in SAM mode. With this option, single bytes can be changed.

NVM Editor

Notes: • It is assumed that the components are mounted correctly with correct values and no bad solder joints. • Before any fault finding actions, check if the correct options are set.

Fault Finding and Repair Tips

Additionally, the entire error buffer is displayed when Service Mode “SDM” is entered.

Displaying the Entire Error Buffer

Example (2): the content of the error buffer is “12 9 6 0 0” After entering SDM, the following occurs: • 1 long blink of 5 seconds to start the sequence, • 12 short blinks followed by a pause of 1.5 seconds, • 9 short blinks followed by a pause of 1.5 seconds, • 6 short blinks followed by a pause of 1.5 seconds, • 1 long blink of 1.5 seconds to finish the sequence, • The sequence starts again with 12 short blinks.

Service Modes, Error Codes, and Fault Finding

You can read the error buffer in three ways: • On screen via the SAM/SDM/CSM (if you have a picture). Example: – ERROR: 0 0 0 0 0 : No errors detected – ERROR: 6 0 0 0 0 : Error code 6 is the last and only detected error – ERROR: 9 6 0 0 0 : Error code 6 was detected first and error code 9 is the last detected (newest) error • Via the blinking LED procedure (when you have no picture). See paragraph 5.5 The Blinking LED Procedure. • Via ComPair.

How to Read the Error Buffer

5.5

5.4.4

5.4.3

5.4.2

EN 16

5.7.3

5.7.2

Introduction

5.7.1

Write NVM Data to TV 1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "L11M11L_NVM_U2T.BIN". 2. Insert the USB stick into the USB slot while in SAM mode.

Write NVM Data to USB 1. Insert the USB stick into the USB slot while in SAM mode. 2. Execute the command "NVM Copy" > "NVM Copy to USB", to copy the NVM data to the USB stick. The NVM filename on the USB stick will be named "L11M11L_NVM_T2U.BIN" (this takes a couple of seconds).

How to Copy NVM Data to/from USB

How to upgrade: 1. Copy the “autorun.upg” file to the root of an USB stick. 2. Insert the USB stick in the side I/O while the set is “on”. The TV will prompt an upgrade message. Press “Update” to continue, after which the upgrading process will start. As soon as the programming is finished, the set must be restarted. In the “Setup” menu you can check if the latest software is running.

Automatic Software Upgrade In “normal” conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the “autorun.upg” (FUS part in the one-zip file). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu (see DFU). The “autorun.upg” file must be placed in the root of your USB stick.

Main Software Upgrade

It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set. A description on how to upgrade the main software can be found in the DFU or on the Philips website.

Software Upgrading

Possible Stand-by Controller failure. Reflash the SW.

TV Will Not Start-up from Stand-by.

Go to Home/Menu ->Setup -> Installation -> Preference and set the Easylink option to “on”. Also check if the connected device is CEC enabled.

HDMI CEC Not Functioning

Check if HDCP key is valid. This can be done in CSM.

No Picture via HDMI input

Check (via ComPair) if HDMI EDID data is properly programmed.

Unstable Picture via HDMI input

When you have no picture, first make sure you have entered the correct display code. See Display Option Code Selection for the instructions.

No Picture

5.7

5.6.7

5.6.6

5.6.5

5.6.4

5.6.3

5.7.5

5.7.4

L11M1.1L LA

EN 17

2011-Apr-29

Important: The file must be located in the "/Repair" directory of the USB stick.

Write Channel List Data to TV 1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "L11M11L_CHTB_U2T.BIN". 2. Insert the USB stick into the USB slot while in SAM mode. 3. Execute the command "Chanel list Copy from USB" to copy the USB data to the TV (this takes about a minute to complete).

Write Channel List Data to USB 1. Insert the USB stick into the USB slot while in SAM mode. 2. Execute the command "Channel list Copy to USB", to copy the channel list data to the USB stick. The filename on the USB stick will be named "L11M11L_CHTB_T2U.BIN" (this takes a couple of seconds).

How to Copy the Channel List to/from USB

Important: The file must be located in the "/Repair" directory of the USB stick.

Write EDID Data to TV 1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "L11M11L_EDID_U2T.BIN". 2. Insert the USB stick into the USB slot while in SAM mode. 3. Execute the command "NVM Copy" > "EDID Copy from USB" to copy the USB data to EDID (this takes about a minute to complete).

Write EDID Data to USB 1. Insert the USB stick into the USB slot while in SAM mode. 2. Execute the command "NVM Copy" > "EDID Copy to USB", to copy the EDID data to the USB stick. The filename on the USB stick will be named "L11M11L_EDID_T2U.BIN" (this takes a couple of seconds).

How to Copy EDID Data to/from USB

3. Execute the command "NVM Copy" > "NVM Copy from USB" to copy the USB data to NVM (this takes about a minute to complete). To write an NVM mask to the TV, ensure that the mask has the correct format: "L11M11L_NVM_U2T.MAK" (0x00 to write protect, 0xFF to overwrite). Important: The file must be located in the "/Repair" directory of the USB stick.

Service Modes, Error Codes, and Fault Finding

L11M1.1L LA

Min. 11.7

+12VS

2.38 4.75 14.82

F133 F131 F132 F125 F101 F235 F136

FM02 FJ14 FJ13 FJ05

+1V25_SW +5V_SW +1V8_SW +1V1_SW +5VS +2V5_SW

+5VTUN_DI F236 GITAL FJ01

+3V3_SW

VLS_15V6 VGH_35V VGL_-6V VCC_3V3 VCC1V8

1.71

3.14

-7.0

34.0

4.94

0.94

1.74

4.98

1.18

3.2 3.17

+3V3_STBY F113

F118

Test Description Point

1.8

3.3

-6.0

35.0

15.6

2.5

5.2

1.1

1.83

5.25

1.25

3.34

3.3

12.3

Typ.

Specifications (V)

1.89

3.47

-5.0

36.0

16.38

5.25

2.62

5.46

1.15

1.92

5.51

1.31

3.5

3.4

12.91

Max.

B08C_TCON DC/DC

B08F_MINI LVDS

B08C_TCON DC/DC

B02_Tuner_IF

B01_DC-DC

B02A_Tuner_IF

B01_DC-DC

Diagram

There are no hardware alignments foreseen for this chassis, but below find an overview of the most important DC voltages on the SSB. These can be used for checking proper functioning of the DC/DC converters.

Hardware Alignments

Perform all electrical adjustments under the following conditions: • Power supply voltage (depends on region): – AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%). – AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%). – EU: 230 VAC / 50 Hz (± 10%). – LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%). – US: 120 VAC / 60 Hz (± 10%). • Connect the set to the mains via an isolation transformer with low internal resistance. • Allow the set to warm up for approximately 15 minutes. • Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heatsinks as ground. • Test probe: Ri > 10 Mohm, Ci < 20 pF. • Use an isolated trimmer/screwdriver to perform alignments.

General Alignment Conditions

General: The Service Default Mode (SDM) and Service Alignment Mode (SAM) are described in chapter 5. Menu navigation is done with the CURSOR UP, DOWN, LEFT or RIGHT keys of the remote control transmitter.

2011-Apr-29

6.2

6.1

Alignments

Note: Figures below can deviate slightly from the actual situation, due to the different set executions.

Index of this chapter: 6.1 General Alignment Conditions 6.2 Hardware Alignments 6.3 Software Alignments 6.4 ADC gain adjustment 6.6 Option Settings

6. Alignments

EN 18

6.3.2

6.3.1

6.3

100

Contrast

0.282

0.276

0.296

0.287

0.329

0.313

If you do not have a color analyzer, you can use the default values. This is the next best solution. The default values are average values coming from production (statistics). • Set the RED, GREEN and BLUE default values per temperature according to the values in the “Tint settings” table. • When finished return to the SAM root menu and press STANDBY on the RC to store the aligned values to the NVM.

Value Cool (11000 K) Normal (9000 K) Warm (6500 K)

Table 6-1 White D alignment values

In case you have a color analyzer: • Measure with a calibrated (phosphor- independent) color analyzer (e.g. Minolta CA-210) in the centre of the screen. Consequently, the measurement needs to be done in a dark environment. • Adjust the correct x,y coordinates (while holding one of the White point registers R, G or B on max. value) by means of decreasing the value of one or two other white points to the correct x,y coordinates (see Table 6-1 White D alignment values). Tolerance: dx: ± 0.002, dy: ± 0.002. • Repeat this step for the other color Temperatures that need to be aligned. • When finished return to the SAM root menu and press STANDBY on the RC to store the aligned values to the NVM.

White Tone Alignment: • Activate SAM. • Select “RGB Align.“ and choose a color temperature. • Use a 100% white screen as input signal and set the following values: – “Red BL Offset” and “Green BL Offset” to “7” (if present). – All “White point” values initial to “127”.

50 0

Colour

Light Sensor Brightness

Unscaled Off

Picture Format

Off Off

Colour Enhancement

Off Dynamic Contrast

Dynamic backlight

Picture Setting

Before alignment, set the picture as follows:

RGB Alignment

No alignment is necessary, as the AGC alignment is done automatically.

Purpose: To keep the tuner output signal constant as the input signal amplitude varies.

Tuner Adjustment (RF AGC Take Over Point)

With the software alignments of the Service Alignment Mode (SAM) the Tuner and RGB settings can be aligned.

Software Alignments

6.4.2

6.4.1

6.4

t.b.d. t.b.d.

Cool Normal Warm

t.b.d. t.b.d.

Cool Normal Warm

t.b.d.

Following instructions result in correct alignment of ADC gain, offset and phase, related to PC VGA input signal. Apply a signal of format “DMT1060”. • Apply following signals to the PC VGA input connector: – Red signal of 0.7 Vp-p1 / 75 ohm. – Green signal of 0.7 Vp-p1 / 75 ohm. – Blue signal of 0.7 Vp-p1 / 75 ohm. • Select the input source to PC VGA input. • In SAM, initiate the “Auto ADC” calibration command. Upon appearance of the “Auto ADC Completed” message, the alignment is completed.

PC VGA

Notes: 1. Peak-to-Peak 2. Black-to-Peak.

Following instructions result in correct alignment of ADC gain, offset and phase, related to YPbPr input signal. Apply a signal of format “1080i25”. • Apply following signals to the YPbPr input connectors: – Pr signal of 0.7 Vp-p1 / 75 ohm to the red cinch connector. – Y signal of 0.7 Vb-p2 / 75 ohm with a sync pulse of 0.3 Vp-p1 to the green cinch connector. – Pb signal of 0.7 Vb-p1 / 75 ohm to the blue cinch connector. • Select the input source to YPbPr input. • In SAM, initiate the “Auto ADC” calibration command. Upon appearance of the “Auto ADC Completed” message, the alignment is completed.

YPbPr

Figure 6-1 “PgcWrgb” pattern

18920_200_100317.eps 100317

Use a Quantum Data Patters Generator 802BT and apply a “PgcWrgb” image (“dot, cross and color bar mix pattern”) according to Figure 6-1.

ADC gain adjustment

R t.b.d.

Colour Temp.

Table 6-3 Tint settings 40"

R t.b.d.

Colour Temp.

Table 6-2 Tint settings 32"

6.6.2

6.6.1

6.6

6.5

L11M1.1L LA

EN 19

2011-Apr-29

How to Change Options Codes An option code (or “option byte”) represents eight different options (bits). All options are controlled via ten option bytes (OP#1... OP#10). Activate SAM and select “Options”. Now you can select the option byte (OP#1... OP#10) with the CURSOR UP/ DOWN keys, and enter the new 3 digit (decimal) value. For the correct factory default settings, see the sticker inside the set.

When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set all option numbers. You can find the correct option numbers see sticker on the inside the cabinet.

How To Set Option Codes

Notes: • After changing the option(s), save them with the STORE command. • The new option setting becomes active after the TV is switched “off” and “on” again with the mains switch (the EAROM is then read again).

The microprocessor communicates with a large number of I2C ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address. The presence/absence of these specific ICs (or functions) is made known by the option codes.

Introduction

Option Settings

ComPair (see 5.3.1 ComPair) will foresee in a possibility to do this alignment.

New requirement for “TCON on SSB” project: • The purpose of VCOM alignment is to obtain an equal voltages for both Positive and Negative LC polarity. This is important to avoid “Flicker” and “Image Sticking”. • The P-Gamma + VCOM calibrator IC, ISL24837 is used for VCOM adjustment. • The adjusted VCOM data will be stored inside on-chip memory and will be automatically recalled during each power-up.

TCON Alignment (= VCOM alignment)

Alignments

L11M1.1L LA

Circuit Descriptions

2011-Apr-29

7.1

Refer to Figure 7-1 for details.

Interfaces for debug and SW upgrade: • UART (3.5 mm jack). • USB port. • JTAG.

19130_009_110426.eps 110429

Tuner/Frontend configuration: • Half NIM tuner (VA1E1BF2403) from Sharp. • Toshiba Channel Decoder (TC90517).

System SoC is based on MT5363: • NAND Flash – 128 Mbyte, NumOnyx/Hynix. • DDR – 128 Mbyte (32 × 16M, 2 pcs), Hynix. • Use internal MT5363 Stand-by micro-controller.

Main key components are the Mediatek MT5363 integrated “System On Chip” (SoC) that supports multimedia video/audio input, and the integrated TCON (Timing Controller) part for the LCD panel.

The xxPFL3x06D/xx sets come with the “Thriller” styling, and the xxPFL5x06D/xx come with the “Berlinale” styling.

The LC11M1.1L LA chassis is a digital chassis using a Mediatek chipset. It covers screen sizes of 32" to 40".

Introduction

Figure 7-1 L11M1.1L LA Architecture

Notes: • Only new circuits (circuits that are not published recently) are described. • Figures can deviate slightly from the actual situation, due to different set executions. • For a good understanding of the following circuit descriptions, please use chapter 9. Block Diagrams and 10. Circuit Diagrams and PWB Layouts. Where necessary, you will find a separate drawing for clarification.

Index of this chapter: 7.1 Introduction 7.2 Power Supply 7.3 Video 7.3.1 Video: Front-End 7.4 Audio 7.5 Inputs 7.5.1 Inputs: HDMI 7.5.2 Inputs: USB

7. Circuit Descriptions

EN 20

Figure 7-3 SSB key component overview

Figure 7-2 SSB cell layout

Circuit Descriptions L11M1.1L LA

EN 21

2011-Apr-29

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19130_010_110426.eps 110426

L11M1.1L LA

The mains power supply unit distribute the following voltages to the TV system: +3V3STBY, 12VS, +24Vaudio, and +24Vpanel for panel with inverter (or) high voltage (HV) for inverterless panel. Requirement of the High Voltage depend on the specification of the LCD panel.

The power supply system consists of stand-by, switched and regulated voltages. The stand-by voltage, +3V3STBY, will be available once AC supply is provided to the system. As for the other voltages, namely switched and regulated voltages, these are available once the STANDBY signal is pulled “low” to allow other supplies from the IPB to turn “on”. The switched supplies are generated from the main +12VS supply, while the regulated supplies are derived from the switched supplies. There are a number of detection circuits to detect the following supplies: +12VS, +12Vdisp and +3V3_SW. The +12VS is the main supply voltage from the IPB that enables the switched voltages to be generated. The +12Vdisp is the supply to the display timing controller, while the +3V3_SW is powering the microprocessor and its flash memory.

Refer to Figure 7-5 and Figure 7-6 for details

USB

Regulator

5.25 V ±0.26 V

3.3 V ±0.16 V

1.8 V ±0.09 V

1.1 V ±0.05 V

Tuner

5.25 V ±0.25 V

Regulator

DCDC

2.5 V ±0.12 V

Regulator

DDR2 × 2

MT5363

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Flash

EEPROM

NVM

Dig Demod

1.25 V ±0.06 V

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Figure 7-6 Power timing overview

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Figure 7-5 Power distribution overview

+3.3 VSTBY

+12 VS

Figure 7-4 TCON key component overview

Circuit Descriptions

The Power Supply Unit (PSU) in this chassis is a buy-in and is a black-box for Service. When defective, a new panel must be ordered and the defective panel must be returned for repair, unless the main fuse of the unit is broken. Always replace the fuse with one with the correct specifications! This part is commonly available in the regular market.

Power Supply

2011-Apr-29

7.2

EN 22

Video: Front-End

7.3.1

EN 23

2011-Apr-29

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Toshiba channel decoder TC90517 (external ISDB-T channel decoder). Analog demodulator (using internal MT5363 analog demodulator - pin AH35 VIP, AH37 VIN).

L11M1.1L LA

Refer to Figure 7-7 for details.

•

Figure 7-7 Front-end functional block diagram

Key components for the tuner section are: • Sharp Half NIM tuner VA1E1BF2403,

Video

7.3

Circuit Descriptions

L11M1.1L LA

Circuit Descriptions

2011-Apr-29

In this chassis, the main Mediatek MT5363 SoC has an on-chip HDMI multiplexer. Refer to Figure 7-9 for the implementation.

Inputs: HDMI

7.5.1

DC_PROT Detecting present of DC at speakers output and feedback to uP. This will trigger TV into protection mode. This is important to protect speakers

DC_PROT

Inputs

Corresponding to the MUTE button on Remote Control, to mute/unmute speakers

MUTE

DC_PROT -

HIGH

HIGH LOW

LOW

HIGH MUTE

HIGH

RESET_AUDIO LOW

LOW HIGH

SW_MUTE

19130_014_110426.eps 110426

No DC -> normal operating

DC detected -> set going to protection

MUTE

Operating (unmute)

Class D shutdown (mute)

Operating (unmute)

MUTE

A_STBY to class D Class D outputs

From uP

Table 7-2 Microprocessor control lines - 2 -

Figure 7-8 Audio signal flow

Control SHUTDOWN pin of class D amplifier: ON/OFF the amplifier

SW_MUTE Will pull audio signals to LOW upon DC drops, help to eliminate plop sound.

SW_MUTE RESET_AUDIO A_STBY

At class D Usage

From uP

Table 7-1 Microprocessor control lines - 1 -

The audio profile (optimal setting per screen size and styling) is stored at Option 10 (bit 0 to bit 4). Profile 1 for 32-inch Dali and profile 2 for 40-inch Dali.

In this chassis, audio processing is done by the following key components: • MT5363 micro-processor for input selection and audio processing, • TPA3123D2 class-D power amplifier for 2 x 10 W amplification.

Audio

7.5

7.4

EN 24

7.5.2

GPIO_7 GPIO 7

CEC

EDID

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TMDS PWR5V HDMI_HPD2 HDMI_SDA2 HDMI_SCL2

EDID_WC EDID WC

ARC eHDMI+

TMDS PWR5V SIDE_HDMI_HPD1 SIDE_HDMI_SCL1 SIDE_HDMI_SDA1

Figure 7-10 USB implementation

18980_207_100402.eps 100402

In this chassis, the main Mediatek MT5363 SoC has an on-chip USB processor. Refer to Figure 7-10 for the implementation.

Inputs: USB

Signal description: • TMDS: Signals that contain audio and video information. • PWR5V: Signal to detect the presence of any HDMI source connected to the TV’s HDMI input port. • SIDE_HDMI_HPD1 and HDMI_HPD2: Signal to initiate reading of the TV EDID data by the source device. • I2C: The EDID data reading and the HDCP authentication process runs via I2C. • CEC: Signal direct connected between inputs and uP. • EDID_WC: Signal used to disable the write protect pin of the EEPROM. When updating, the program will temporarily pull this pin “LOW” before writing new data.

Figure 7-9 HDMI implementation

Buffer & Selection circuit

ASPDIF_OUT ARC_SW

RX1 OPWR1_5V HDMI_HPD1 HDMI_SDA1 HDMI_SDA1

MT5363

HDMI_CEC

RX2 OPWR2_5V HDMI_HPD2 HDMI_SCL2 HDMI_SDA2

Circuit Descriptions L11M1.1L LA

2011-Apr-29

EN 25

L11M1.1L LA

5 6

FB1

EN1 EN2

FB2

CLK2

150 k

Soft Start 2

0.8 VREF

150 k

6 A

VDD2

Soft Start 1

0.8 VREF

SD2

FB2

FB1

CCOMP

RCOMP

0.8 VREF

f(IMAX2)

4 5 6 7

GND EN1 EN2 FB1

CLK2

f(ISLOPE2)

CLK1

f(ISLOPE1)

Anti-Cross Conduction

Ramp Gen 2

Ramp Gen 1

Anti-Cross Conduction

Figure 8-1 Internal block diagram and pin configuration

8 FB2

9 ILIM2

10 SEQ

11 BP

12 SW2

13 BOOT2 3

SW1

Thermal Pad (bottom side)

14 PVDD2 2

CLK2

HTSSOP (PWP) (Top View)

Overcurrent Comp

S R R

CLK1

Divide by 2/4

IMAX2 (Set to one of three limits)

R R

PVDD1

References

PVDD2

f(ISLOPE2)

f(IDRAIN2)

Overcurrent Comp

f(IMAX1)

1.2 MHz Oscilator

BOOT1

Level Select

5.25-V Regulator

Current Comparator

UVLO

SD2

SD1

f(ISLOPE1)

f(IDRAIN1)

Internal Control

TSD

Current Comparator

Output Undervoltage Detect

CCOMP

RCOMP

f(IDRAIN2) + DC(ofst)

Level Shift

6 A

SD1

f(IDRAIN1) + DC(ofst)

Level Shift

PIN CONNECTIONS

ILIM2

BP 11

GND

SEQ 10

GND

CLK1

BLOCK DIAGRAM

Diagram B01, Type TPS54386 (IC7116 and 7117)

2011-Apr-29

8.1

IC Data Sheets

This section shows the internal block diagrams and pin layouts of ICs that are drawn as "black boxes" in the electrical diagrams (with the exception of "memory" and "logic" ICs).

8. IC Data Sheets

EN 26

SW1

PVDD1

BOOT1

12 SW2

14 PVDD2

13 BOOT2

UDG-07124

Weak Pull-Down MOSFET

FET Switch

Weak Pull-Down MOSFET

18980_300_100402.eps 100402

8.2

DPAK

LD1117DT

L11M1.1L LA

Figure 8-2 Internal block diagram and pin configuration

Pinning information

Block diagram

Diagram B01A DC-DC, Type LD1117D (IC7119)

IC Data Sheets 8.

2011-Apr-29

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EN 27

L11M1.1L LA

IC Data Sheets

TERMINAL

BYPASS

I/O

1 2 3 4 5 6 7 8 9 10 11 12

1 F

0.22 F

}

Control

470 F

PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDR

22 H

0.68 F

DESCRIPTION

24 23 22 21 20 19 18 17 16 15 14 13

GAIN1

GAIN0

VCLAMP

PVCCR

PVCCL

BSL

LOUT

PGNDL

22 H 0.68 F

0.22 F

Connect to ground. Thermal pad should be soldered down on all applications to properly secure device to printed wiring board.

High-voltage analog power supply. Not internally connected to PVCCR or PVCCL

Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via external capacitor sizing.

Analog ground for analog cells in core

Analog ground for digital/analog cells in core

Power supply for right-channel H-bridge, not connected to PVCCL or AVCC

Power ground for right-channel H-bridge.

Class-D 1/2-H-bridge negative output for right channel

Bootstrap I/O for right channel

Internally generated voltage supply for bootstrap capacitors

Power ground for left-channel H-bridge

Class-D 1/2-H-bridge positive output for left channel

Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC

Bootstrap I/O for left channel

Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low = outputs enabled). TTL logic levels with compliance to AVCC

Gain select most-significant bit. TTL logic levels with compliance to AVCC

Gain select least-significant bit. TTL logic levels with compliance to AVCC

Audio input for left channel

Audio input for right channel

Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to AVCC

MUTE

AVCC

AGND

BYPASS

ROUT

RIN PGNDR

BSR

LIN

Figure 8-3 Internal block diagram and pin configuration

19, 20

AGND

Die pad

AGND

Thermal pad

10, 12

PVCCR

AVCC

BSR

13, 14

VCLAMP

PGNDR

23, 24

PGNDL

ROUT

MUTE

LOUT

GAIN1

GAIN0

1, 3

LIN

PVCCL

RIN

BSL

24-PIN (PWP) SD

NAME

PVCCL SD PVCCL MUTE LIN RIN BYPASS AGND AGND PVCCR VCLAMP PVCCR

1 F

I/O/P

1 F

Pinning information

Shutdown Control

Block diagram

Diagram B03 Class-D & muting, Type TPA3123 (IC7400)

2011-Apr-29

8.3

EN 28

18440_302_090303.eps 090318

8.4

PVR

BScan

Audio DAC

SPDIF, I2S

IrDA

Audio In

Audio Demod

Figure 8-4 Internal block diagram

MS,SD

Watchdog

PWM

2011-Apr-29

18850_300_100107.eps 100222

NAND Flash

Servo ADC

Standby uP CKGEN Serial Flash

EN 29

DDR DRAM Controller

Vplane scaler/PIP

Mix andPost Processing

TVE

VDAC

LVDS

OSD scaler

Audio ADC

CVBS

Panel

L11M1.1L LA

Audio Input

IO Bus

2-D Graphic

JPEG,MPEG H.264

USB2.0

RTC UART

SIF

MDDi

HDMI Rx HDMI In I/F

PreProc

VDO-In

TV Decoder

JTAG

TS Demux

ATD

VADCx4

CVBS/ YC Input

Audio I/F

Audio DSP

BIM

ARM

DVB-T

Block diagram

Diagram B04 MT5363 Power, Type MT5363 (IC7700)

IC Data Sheets

2011-Apr-29

EN 30

L11M1.1L LA

AV 1

POCE0_

OSDA0

VCCK

JTRST_

GPIO44

VCC2IO

RCLK1

RDQ16

RDQS3

RDQM2

RDQ19

RA8

RA13

RCKE

RBA2

RA5

RA9

VCC2IO

LT 1

POOE_

PDD0

VCCK

JTDI

GPIO38

VCC2IO

RDQ21

RDQS3_

RDQS2_

RDQ22

VCC2IO

RA11

RCAS_

RBA1

RA10

RA12

VCC2IO

RCLK0_

POWE_

OSCL0

VCCK

JTCK

GPIO43

VCC2IO

RCLK1_

RDQ23

DVSS

RDQS2

RDQ20

RCS_

RA2

RWE_

RBA0

RA7

VCC2IO

RCLK0

PACLE

PAALE

VCCK

JTMS

GPIO41

VCC2IO

RDQ18

RDQ29

DVSS

RDQ17

VCC2IO

RA0

DVSS

RA3

VCC2IO

RDQ13

RDQ10

PARB_

PDD1

VCCK

JTDO

GPIO37

VCC2IO

REXTDN

RDQ24

RDQ28

RDQ30

RRAS_

RA4

MEMTN

RA1

VCC2IO

RDQ5

RDQ8

Pinning information

PDD5

PDD4

VCCK

GPIO40

VCC2IO

RDQ31

RDQ27

RDQ25

RVREF

RA6

MEMTP

VCC2IO

RDQ7

RDQ0

RDQS1

PDD7

PDD6

VCCK

DVSS

RVREF

DVSS

RDQS0_

AVSS33_U

USB_DP

USB_DM

AVSS33_U

DMI

AVDD33_U SB

RDQ1

RDQ6

RDQ9

RDQ11

AVDD12_H

USB_VRT

AVDD12_U SB

DVSS

RDQM0

RDQM1

RDQ14

AVSS33_U

AVSS12_U SB

DVSS

RDQS0

Figure 8-5 Internal block diagram

PDD3

PDD2

POCE1_

VCCK

GPIO42

GPIO39

VCC2IO

RDQ26

DVSS

RDQM3

VCC2IO

RODT

DVSS

VCC2IO

RDQ2

RDQS1_

RDQ15

IC Data Sheets

RX2_CB

RX2_C

DMI

AVSS33_H

HDMI_SCL

VCCK

RDQ3

VCC2IO

RDQ12

RX2_0B

RX2_0

AVDD33_H DMI

VCCIO33-1

DVSS

VCCK

EMPLL

AVSS12_M

AVDD12_M EMPLL

RDQ4

VCC2IO

RX2_1B

RX2_1

HDMI_CEC

HDMI_SDA 2

VCCK

DVSS

VCCK

DVSS

VCCK

DVSS

VCC2IO

RX2_2B

RX2_2

PWR5V_2

VCCIO33-1

VCCK

DVSS

VCCK

DVSS

VDS

AVDD33_L

AVDD33_L VDS

AO0P

AO0N

RX1_CB

RX1_C

HDMI_HPD 2

PWR5V_1

VCCK

DVSS

VCCK

AVDD12_L VDS

AE0P

AE0N

AO1P

AO1N

RX1_1B

RX1_1

HDMI_SDA

HDMI_HPD 1

VCCK

DVSS

AVDD12_V PLL

AVSS33_L VDS

AE2P

AE2N

AOCKP

AOCKN

RX1_2B

RX1_2

OPCTRL1

VCCK

DVSS

AVSS12_V PLL

TP_VPLL

AECKP

AECKN

AO3P

AO3N

18850_301_100107.eps 100222

RX1_0B

RX1_0

HDMI_SCL 1

VCCK

DVSS

AVSS12_L VDS

AE1P

AE1N

AO2P

AO2N

HSYNC

OIRI

ORESET_

VCCK

DVSS

VCCK

DVSS

GPIO36

GPI O35

VSYNC

U0RX

U0TX

OPCTRL0

DVSS

AE4P

AE4N

DVSS

OPCTRL4

OPCTRL3

OPCTRL2

OPWRSB

VCCK

DVSS

AE3P

AE3N

AO4P

AO4N

SOG

COM

PB1P

SOY0 29

COM0

PR0P

DAC

VDAC_OUT

Figure 8-6 Internal block diagram

Y1P

COM1

AVSS33_V

VBS

AVSS33_C

VBS

DAC SOY1

VDAC_OUT 1

BYPASS0

ADIN0_SR

AVDD12_S YSPLL

GA_STB

PB0P

FS_VDAC

IG AVDD33_S

AVSS12_P

SC0

SY0

ADIN1_SR

DCPLL

AVDD12_A

ADAC0

AVDD33_

SC1

SY1

MPXP

ADIN3_SR

XTALO

DEMOD1

AVDD33_

DAC0

CVBS3P

CVBS2P

ADIN2_SR

TAL_STB

AVDD33_X

EMOD

ADCINN_D

AVICM

DC AVSS33_A

AIN2_L_AA

ADC

ADC AIN0_L_AA

AIN0_R_A

AIN1_R_A

ADC

AIN5_R_A ADC

AL2

U1TX

AIN5_L_AA

VCCIO33

AR2

OSCL1

CVBS1P

CVBS0N

MPXN

ADIN5_SR

XTALI

EMOD1

AVSS33_D

AR0

AIN3_L_AA

AIN6_L_AA

VCCIO33

AR3

U1RX

K AOSDATA1

AOSDATA0

OPWM1

CI_MOVAL

ETMDC

ETCRS

ETRXD0

TUNER_CL

AOMCLK

GPIO0

CI_MDI0

CI_MCLKI

ETRXER

ETRXD1

EN 31

2011-Apr-29

18850_302_100107.eps 100222

CVBS0P

PASS

TUNER_BY

ADIN4_SR V

TAL

AVSS33_X

EMOD

ADCINP_D

AL0

ADC

AIN3_R_A

ADC

AIN6_R_A

AL3

VCXO

AOSDATA2

AOLRCK

GPIO1

CI_MDO0

CI_MOSTR

ETMDIO

ETRXDV

TUNER_DA

AOBCK

OPWM0

CI_MIVAL

ETTXER

ETRXD3

ETRXD2

AIN2_R_A

AVSS33_A ADC

AR1

OPWM2

OSDA2

RF_AGC

ASPDIF

CI_MISTR

CI_MCLKO

ETTXCLK

ETRXCLK

AIN4_R_A

AIN4_L_AA

VCCIO33

AL1

OSDA1

AOSDATA4

ALIN

GPIO2

ETCOL

ETTXD2

ETTXD1

ETTXD0

AIN1_L_AA

AVDD33_A ADC

VCCIO33

AVDD33_A DAC1

OSCL2

IF_AGC

AOSDATA3

VCCIO33

ETPHYCLK

ETTXEN

ETTXD3

AVDD33_D

AVSS33_D

AVDD12_A PLL

VMID_AAD

EF_AADC

AVDD33_R

AVSS33_A DAC1

FSRC_WR

VCCIO33

GPIO5

GPIO6

GPIO4

GPI O3

AVSS33_SI

AVSS12_P

VDPLL

AVDD12_T

AVSS33_R EF_AADC

GPIO7

GPIO8

GPIO10

GPIO9

AVDD33_C

Y0P

GPIO13

GPIO14

GPIO12

GPIO11

AVDD33_V

PR1P

GPIO15

GPIO16

GPIO18

GPIO17

AVSS12_R

GPIO23

GPIO19

GPIO20

GPIO22

GPI O21

L11M1.1L LA

AVDD33_V

DVSS

VCCK

DVSS

GPIO25

GPIO24

GPIO27

GPIO26

AVDD12_R

GA_STB

AVSS33_V

DVSS

VCCK

DVSS

VCCK

GPIO31

GPIO29

GPIO30

GPIO28

AVDD10_L

DVSS

VCCIO33

GPIO33

GPIO34

GPIO32

Pinning information

IC Data Sheets

L11M1.1L LA

IC Data Sheets

VEE

Inputs 1

Output 1

Pinning information

2 4

Figure 8-7 Pin configuration

(Top View)

Inputs 2

Output 2

VCC

Diagram B06B Analog I/O - Audio, Type LM833 (IC7B01)

2011-Apr-29

8.5

EN 32

18520_306_090325.eps 100402

VREF

0.75 VREF

0.4V

5 6 7 8

PGND3 PGND4 CM2 FBL

4 LXL2

CB LXL1

VREF

POUT

PVIN2

C1+

ISL97653A 40 LD 6X6 QFN TOP VIEW

COM

CTL

DRN

C2-

POUT

TEMP SENSOR

LDO CONTROL LOGIC2

TEMP

LDO-FB

LDO-CTL

FBL

CM2

LXL1 LXL2

PGND1 PGND2

LX1 LX2

21 POUT

22 COM

23 DRN

24 CTL

25 CDEL

26 EN

27 HVS

28 RSET

29 FBB

30 COMP

VREF

GM AMPLIFIER

SLOPE COMPENSATION SAWTOOTH GENERATOR

(

CONTROL LOGIC

RSENSE

CURRENT LIMIT THRESHOLD

C2+

CURRENT LIMIT COMPARATOR

BUFFER CURRENT AMPLIFIER

CURRENT LIMIT THRESHOLD

SUPP

CURRENT LIMIT COMPARATOR

SEQUENCE CONTROLLER

AND

REFERENCE BIAS

CURRENT AMPLIFIER

Figure 8-8 Internal block diagram and pin configuration

SUPP

UVLO COMPARATOR

0.2V

SUPN

C1-

680kHz OSCILLATOR

REGULATOR

Pinning information

FBP

FBN

NOUT

PVIN1,2

CDEL

PVIN1,2

FREQ

0.75 VREF

CONTROL LOGIC

LDO-CTL FBN

(

BUFFER

LDO-FB SUPN

UVLO COMPARATOR

SLOPE COMPENSATION

PVIN1 NOUT

AGND

VREF

SAWTOOTH GENERATOR

PROT C1P PGND5

FBB

HVS LOGIC

LX2

GM AMPLIFIER

VREF PROT

LX1 C2P C1N

CM1

RSET HVS

PGND2 C2N

Block diagram

Diagram T01C TCON DC/DC, Type ISL97653 (IC7J00)

L11M1.1L LA

PGND1

8.6

IC Data Sheets

TEMP FBP

SUPP

EN 33

2011-Apr-29

18770_307_100217.eps 100217

L11M1.1L LA

2011-Apr-29

Personal Notes:

EN 34

IC Data Sheets

10000_012_090121.eps 090121

IR/LED BOARD (1112)

8319

1M99

14P

TO BACKLIGHT

(1005)

1308

2P3 L

MAIN POWER SUPPLY 32 PSLC-P002A

Component Level Repair Only For Authorized Workshop

Board Level Repair

WIRING DIAGRAM 32" THRILLER

Wiring Diagram 32" (Thriller)

9P 11P

9. Block Diagrams

KEYBOARD CONTROL (1114)

1M99 1M95

L11M1.1L LA

8308

2011-Apr-29

LCD DISPLAY (1004)

EN 35

INLET

8M95

8M99

LOUDSPEAKER (5213)

TO DISPLAY

8191

8G51

9P 11P 4P

1M99

1. 2. 3. 4. 5. 6. 7. 8. 9.

LEFT_SPEAKER GND-AUDIO GND-AUDIO RIGHT_SPEAKER

1735 (B03) LIGHT-SENSOR GND RC LED-2 +3V3STBY LED-1 KEYBOARD +5V_SW

1. 2. 3. 4.

VGA

1. 2. 3. 4. 5. 6. 7. 8.

51P

1G51

TUNER

1M20 (B04c)

HDMI

3139 123 6505.x (1150)

SSB

+12VDISP +12VDISP GND GND LAMP-ON BACKLIGHT-PWM BACKLIGHT-BOOST INV_STATUS POWER-OK

1M99 (B01) 1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. GND 6. +12VS 7. +12VS 8. +12VS 9. +24VAUDIO 10. GND-AUDIO 11. ...

1M95 (B01)

1M95

1M20 1735

Block Diagrams

MAINS CORD

USB HDMI

8M20

19130_044_110428.eps 110429

1. +VDISP-INT 2. +VDISP-INT 3. +VDISP-INT 4. +VDISP-INT | 51. GND

1G51 (B04D)

KEYBOARD CONTROL (1114)

TO BACKLIGHT

IR/LED BOARD (1112)

8319

(1005)

1308

2P3

MAIN POWER SUPPLY IPB 40 PLHE-P986A

1P3

HIGH VOLTAGE

1316

8316

1319

Component Level Repair Only For Authorized Workshop

9P 11P

Board Level Repair

1M99 1M95

Wiring Diagram 40" (Thriller)

8308

INLET

TO DISPLAY

8M95

8M99

LOUDSPEAKER (5213)

LCD DISPLAY (1004)

2011-Apr-29

TO DISPLAY

9P 11P 4P

1M99

80P

1KA2

1. +VDISP-INT 2. +VDISP-INT 3. +VDISP-INT 4. +VDISP-INT | 51. GND

1G51 (B04D)

51P

1G51

LIGHT-SENSOR GND RC LED-2 +3V3STBY LED-1 KEYBOARD +5V_SW

1. 2. 3. 4.

LEFT_SPEAKER GND-AUDIO GND-AUDIO RIGHT_SPEAKER

1735 (B03)

1. 2. 3. 4. 5. 6. 7. 8.

80P

1KA1

1N01

1M20 (B04c)

(1157)

TCON

8KA1

HDMI

+12VDISP +12VDISP GND GND LAMP-ON BACKLIGHT-PWM BACKLIGHT-BOOST INV_STATUS POWER-OK

1. 2. 3. 4. 5. 6. 7. 8. 9.

HDMI

3139 123 6505.x (1150)

1M99 (B01)

SSB

1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. GND 6. +12VS 7. +12VS 8. +12VS 9. +24VAUDIO 10. GND-AUDIO 11. ...

8KA2

1M95 (B01)

1M95

1M20 1735

EN 36

SPDIF

8G51

WIRING DIAGRAM 40" THRILLER

8191

PHONE

L11M1.1L LA

MAINS CORD

TUNER

VGA

USB 1. GND | 47. +VDISP-INT 48. +VDISP-INT 49. +VDISP-INT 50. +VDISP-INT | 51. GND

1N01 (T01A)

1KA1 (T01F) 1. GND | 11. VLS_15V6 12. VLS_15V6 | 33. VCC_3V3 34. VCC_3V3 | 78. VGH_35V 79. VGL_-6V 80. GND

HDMI

Block Diagrams

1. GND | 11. VLS_15V6 12. VLS_15V6 | 33. VCC_3V3 34. VCC_3V3 | 78. VGH_35V 79. VGL_-6V 80. GND

1KA2 (T01F)

19130_043_110428.eps 110429

TO BACKLIGHT

8M20

RF_AGC

7 SDA 9 IF_AGC

SCL

IF_OUT-

CVBS

B06D VGA

AVIN

CVI-2

CVI-1

VGA_B

3 13 14

HDMI 2 CONNECTOR

HDMI 1 (SIDE) CONNECTOR

SY0P

3C20

3C22

3C25

3B02

3B05

3B03

3B01

3B00

3B11

3B09

3B07

3B08

AR16

M_RX2_C M_RX2_CB

M_RX1_C M_RX1_CB

AU12

AT13 AR12

M_RX1_0B

9 10

AP13 RX2

AU14

AP15 AT15 AR14

M_RX1_1B M_RX1_0

4 6 7

M_RX1_2 M_RX1_2B M_RX1_1

AU16

AT17

1901

B05 HDMI-LVDS

COM

SOG

AP17 RX1

AU18

M_RX2_0B

M_RX2_1B M_RX2_0

9 10

4 6 7

AP19 AT19 AR18

AR24

M_RX2_2

AP23

M_RX2_2B M_RX2_1

CVBS_0N

CVBS_2P

Y1N

PR1P

PB1P

Y1P

SOY1

PBR0N

PR0P

PB0P

Y0P

SOY0

B06B AUDIO-VIDEO

AGC_RF

AGC_IF

B04C CONTROL

CI_MDIO

CI_MCLKI

CI_MISTRT

CI_MIVAL

B04C MAC-CI

AT25 RP AU24 GP AT23 BP AR22 HSYNC AU22 VSYNC

AR36

AP35

AR26

AP27

AT27

AU26

AP25

AK22

AU30

AP29

AR28

AT29

SOG

VSYNC

HSYNC

PR0P

PB0P

Y0P

Y0N

VGA_Bp

VGA_Gp

VGA_Rp

GND_CVBS

SY1N

SPR1P

SPB1P

SY1P

SOY1-AV2

3C21 SPR0P

3C23 SPB0P

3C24

SOY0-AV1

AUDIO

B06B ANALOG I/O

M33

M31

IF_AGC RF_AGC

H35

7218

F35

TSO_CLK

60 TSO_DATA0 AGCCNTI 9

H33

G34

7700 MT5363BIMG

B04 MT5363:

58 TSO_VALID DIGITAL DEMODULATOR 59 TSO_SYNC

7217 RF_AGC_SW

7302 TC90517FG

B02A DIGITAL DEMOD

1902

V-SYNC

H-SYNC

VGA_R

VGA_G

CVBS_AV3

5C00

5C01

PB1P_SC2

PR1P_SC2

5C02

SY1P_SC2

5C03

5C04

SC1_B

SC1_CVBS_OUT

5C05

SC1_G

RF_AGC_SW

DIF_P

RESET_DEMOD

B04C

1E01

1C03

1C02

1C01

B05A HDMI & MUX

VGA CONNECTOR

(I2C)

5208

+5VTUN_DIGITAL

IF_OUT+

TUNER

1201 VA1E1BF2403

2C07

B06C ANALOG I/O - VIDEO

1 2

2C06

B02A TUNER

2E08

Block Diagram Video VIDEO

2E03

B05 HDMI-LVDS

EN 37

2011-Apr-29

B04B DRAM

RDQ

PDD

USB_DM USB_DP

B04C CONTROL

MT5363

AR10 AU10

50 60

SDRAM 512Mb

7600 H5PS5162FFR

RDQ(0-31)

B04B DDR

NAND_PDD(0-7)

RA(0-13)

RXE

PX2

USB 2.0 CONNECTOR SIDE SW UPLOAD JPEG MP3

+VDISP-INT

RXO

B08A INTERFACE

7H01 VPP1501BFG

LLV(0-7)

LEVEL SHIFTER

RLV(0-7)

REF VOLTAGE GEN

61 TO DISPLAY

TO DISPLAY

19130_020_110427.eps 110427

2 1

11 10 VLS_15V6 VL

33 12

VCC_3V3

79 78

1KA2

7K00 ISL24837IRZ VGL_-6V VGH_35V

VLS_15V6

VCC_3V3

79 78 72

1KA1 81

VL/VH

CS(1-12)

VGL_-6V VGH_35V

T01F MINI LVDS

VCOM & NVM

T01D P GAMMA &

ASIC_CS

7L00 ISL24016IRTZ

T01B TCON CONTROL T01E MPD

PX1

+1V8_SW

SDRAM 512Mb

7601 H5PS5162FFR

FLASH 1Gb

7708 H27U1G8F2BTR

2 3

1D01 1

3 1

1N01 1

DISLAY

T01A LVDS

B04C CONTROLLER

USB_DM USB_DP

B05B USB

+VDISP-INT

PX2

PX1

1KA1 60

B04D LVDS DISPLAY

RDQ(0-15)

L11M1.1L LA

VDD

19 18

1 2

19 18

VDD

Block Diagrams

RDQ(16-31)

1 3 2 4

AV IN AUDIO L/R

CVI-2

1C03

1C02

1C01

1B02

HDMI 2 CONNECTOR

SPDIF_OUT

M_RX1_CB

AU18 AP17 RX0

M_RX2_2B M_RX2_1

M_RX2_1B M_RX2_0

M_RX2_C

M_RX2_CB

12 AU16

AT17 AR16

M_RX2_0B

9 10

4 6 7

AP19 AT19 AR18

M_RX2_2

1902

AU12

M_RX1_C

AT13 AR12

M_RX1_0B

9 10

4 6 7 AP13 RX1

B05 HDMI

GPIO_12 ASPDIF

AU14

E28

M_RX1_1B M_RX1_0

ARC_SW

B05 GPIO

ASPDIF

M_RX1_2B M_RX1_1

K33

AIN_AADC_3_R

AIN_AADC_3_L

ASPDIF_OUT

AB37

AC36

AIN_AADC_6_R

AIN_AADC_6_L

AIN_AADC_1_R

AIN_AADC_1_L

AIN_AADC_0_R

AIN_AADC_0_L

B06B ALI_DAC

AGC_RF

AGC_IF

B04C CONTROL

AP15 AT15 AR14

eHDMI+

+3V3

DVI_AUR_IN

DVI_AUL_IN

Y37

AA36

AC32

AB31

AC34

AD33

M33

M31

CI_MDIO

CI_MCLKI

CI_MISTRT

CI_MIVAL

B04C MAC-CI

M_RX1_2

SAV_R_IN

SAV_L_IN

AIN1_R-AV2

AIN1_L-AV2

AIN0_R-AV1

RF_AGC

AIN0_L-AV1

7S09 74LVC00 2 3 & 1

7217 RF_AGC_SW

7218

IF_AGC

H35

F35

H33

G34

MT5363:

7700 MT5363BHMG

B04

1901

HDMI & MUX

SPDIF OUT

AV IN AUDIO L/R

1B01

RF_AGC_SW

TSO_CLK

60 TSO_DATA0 AGCCNTI 9

58 TSO_VALID DIGITAL DEMODULATOR 59 TSO_SYNC

ANALOG I/O - AUDIO

HDMI 1 (SIDE) CONNECTOR

B05A

B06B

AV IN AUDIO L/R

AVIN

B04C

ANALOG I/O - VIDEO

RF_AGC

(I2C)

DIF_P

DIF_N

B04C

DIGITAL DEMOD

7302 TC90517FG

B02B

RESET_DEMOD

+5VTUN_DIG

SCL 7 SDA 9 IF_AGC

IF_OUT-

CVI-1

B06C

IF_OUT+

TUNER

1201 VA1E1BF2403

TUNER

5207

B02A

Block Diagram Audio AUDIO

EN 38

B04B DRAM

AR_R

AL_L

RDQ

PDD

USB_DM USB_DP

B04C CONTROL

B06B ALI_ADAC

2011-Apr-29

MT5363

AR10 AU10

u36

V37

B04B

SDRAM 512Mb

7600 H5PS5162FFR

RDQ(0-31)

DDR

RA(0-13)

2 3

1D01 1

STANDBY

1 6

4 2

AOUTR

MUTE A_STBY

+1V8_SW

SDRAM 512Mb

CLASS D POWER AMPLIFIER

USB 2.0 CONNECTOR SIDE SW UPLOAD JPEG MP3

7400 TPA3123D2PWP

CLASS-D & MUTING

AOUTL

B03

7601 H5PS5162FFR

FLASH 1Gb

7708 H27U1G8F2BTR

CONTROLLER

NAND_PDD(0-7)

B04C

USB_DM USB_DP

USB

SW_MUTE

RESET_AUDIO

B05B

B04C

PREAMPR

7B01

ANALOG I/O - AUDIO

PREAMPL

B06B

RDQ(0-15)

L11M1.1L LA

RDQ(16-31)

1 3 2 4

Block Diagrams

VDD

1 2

19 18

1 2

19 18

VDD

B04C

DC_PROT

1735 1

DC-DETECTION

7408

RIGHT_SPEAKER

GND-AUDIO

LEFT_SPEAKER

19130_038_110427.eps 110427

SPEAKER RIGHT

SPEAKER LEFT

PANEL

SDM 2700

2701

B02B

B06D

B03

B02A

B08C

A30

RESET_DEMOD

ORESET

LIGHT-SENSOR

+3V3STBY

KEYBOARD

LED-2

E30

USB_OCP

G30

AG6

DC_PROT

USB_PWR_EN

1700 54M

B29

RF_AGC_SW

AL22

AL36

AM35

AM37

AN22

AJ34

AJ36

A26

B25

B23

BYPASS_MODE

+3V3STBY 7701 BD45292G 5 VDD 4 VOUT

TO IR/LED PANEL AND KEYBOARD CONTROL

CONTROLLER

B04C

1M20 3

MT5363

B04

ORESET

ADIN_SRV_5

ADIN_SRV_2

ADIN_SRV_4

OIRI

XTALO

XTAL1

OPWRSB

U0_TX

U0_RX

PDD

GPIO_12

GPIO_41

GPIO_43

GPIO_35

GPIO_7

CLK

RDQ

USB_DM0 USB_DP0

OPCTRL_3

OPCTRL_4

OPCTRL_0

HDMI_CEC

B04B DRAM

MT5363

B04C CONTROL

GPIO_21

GPIO_26

GPIO_3

GPIO_6

GPIO_5

GPIO_42

GPIO_9

GPIO_32

B04C GPIO

7700 MT5363BIMG

Block Diagram Control & Clock Signals CONTROL + CLOCK SIGNALS

RCLK1# RCLK0 RCLK0#

AD3 B3 A2

USB_DP0

2011-Apr-29

USB_DM0

2 3

B01

B03

B04C

B05A

1701

B06B

B01A

UART SERVICE CONNECTOR

USB 2.0 CONNECTOR SIDE

B04C

B06 B07E B04C

1D01 1

USB_OCP

USB_PWR_EN

SW_MUTE

MUTE

AK5

7D00 TPS2041BD OUT

HDMI_CEC

STANDBY

FLASH 1Gb

7708 H27U1G8F2BTR

ARC_SW

LAMP-ON

POWER_DOWN

USB

7710

NAND_PDD(0-7)

EDID_WC LCD-PWR-ONn

POWER-OK

B06D

SDRAM 512Mb

7601 H5PS5162FFR

FLASH & EJTAG & DISPLAY INTERFACE

RA(0-13)

J8 K8

SDRAM 512Mb

RDQ(16-31)

AJ5

AR20

AU20

AM21

AN14

AL20

AP21

AT21

E28

AG4

AH3

A22

B04C

RCLK1

H29

RDQ(0-31)

DDR

EN 39

7600 H5PS5162FFR

B04B

AD1

L11M1.1L LA

RDQ(0-15)

Block Diagrams

1 3 2 4

T01D

T9 U9

RESET

50Hz_60Hz

1H00 27M

L1 A1

TCK#

TA(0-12) TCK

RTC50_60

RST

OSC_OUT

OSC_IN

OUT12

OUTCOM

P GAMMA

7K00 ISL24837IRZ

SLOPE

TCON CONTROL

7H01 VPP1501BFG

P GAMMA & VCOM & NVM

T01D

SDRAM 512Mb TDQ(0-15)

TCON CONTROL

7H00 H5PS5162FFR

T01B

INCOM

CS_L

T01F

19130_045_110428.eps 110429

T01E

VCOM

T01F

OUTCOM

T01F

CS(1-12)

VCOM BUFER

LEVEL SHIFTER

7L00 SL24016IRTZ

MPD

T01C

T01F

GSLOP

T01E

ASIC_CS

T16

RLV(0-7)

LLV(0-7)

GPIO_44

OSCL_0

OSDA_0

CONTROL

HDMI_SCL1

HDMI_SDA1

HDMI_SCL2

HDMI_SDA2

RDQ

B04B DRAM

TUNER_CLK

TUNER_DATA

U0_TX

U0_RX

PDD

MT5363

B04C

3728

3727

SIDE_HDMI_SCL1

HDMI_SDA2

HDMI_SCL2

AL12

AN18

AM17

B2B

EEPROM

EDID SW

EEPROM

7901 M24C02

FE_SCL

1902

HDMI 2 CONNECTOR

HDMI 1 (SIDE) CONNECTOR

FE_SDA

3748

3749

1901

DIGITAL DEMODULATOR

7302 TC90517FG

DIGITAL DEMOD

7900 M24C02

+3V3STBY

HDMI_PLUGPWR2

SDRAM 512Mb

HDMI & MUX

ERR 15

MAIN NVM SW

SDRAM 512Mb

RA(0-13)

EEPROM (NVM)

7702 M24C64

7601 H5PS5162FFR

RDQ(0-31) 7600 H5PS5162FFR

DDR

TUNER_SCL

SIDE_HDMI_SDA1

B05A

B4B

7703

TUNER_SDA

FLASH 1Gb

+3V3STBY

NAND

7708 H27U1G8F2BTR

SYS_EEPROM_WE

SCL-MAIN

SDA-MAIN

AL14

N36

N34

AP21

AT21

AH1

AP3

AP1

+3V3_SW

B02A

1701

2011-Apr-29

ERR 16

MAIN TUNER

1201 VA1E1BF2403

TUNER

UART SERVICE CONNECTOR

EN 40

VGA

SCL-TCON

TCON CONTROL

7H01 VPP1501BFG

TCON CONTROL

2 SDA-TCON

LVDS DISPLAY

1N01

T01B

TO SSB

EDID_WC

4E02

B04C

4E03

1E01

T01A

VGA CONNECTOR

B06D

5 1

7700 MT5363BIMG

3718

3746

3746 3352

3719

3747

10 6

CONTROLLER

3351

15 11

B04C

3907

3228

3E21

7E01

DC_5V

T01D

3E22

I²C

3717

3908

3230

EEPROM

7K04 M24C64

VCC

VOLTAGE GENERATOR

7K00 ISL24837IRZ

VCC_3V3

P GAMMA & VCOM & NVM

EDID SW

EEPROM

SCL_VGA

SDA_VGA

7E00 M24C02

3K56

3716

3915

3K40

Block Diagram I2C

3916

3K54 3K55

L11M1.1L LA

3K41

Block Diagrams

3K53

B08A

B04C

4817

4818

B04C

SDA_VCOM SCL_VCOM

4816 4814

RESET

DEBUG ONLY

RES

1 ROM_SCL

WP_TCON

2 ROM_SDA

1KQA

RES

1KQB

BYPASS_MODE

I2C SWITCH

7801 PCA9540BDP

CONTROLLER

SW SW

TO TCON

19130_011_110426.eps 110426

Programmable via ComPair

Programmable via USB

1G51

MAIN POWER SUPPLY

B01

B04a

N.C.

GND-AUDIO

+5V_SW

5222

IN OUT COM

7216

TUNER

+5V5_TUN

B02A

SENSE_1V8

5225

+12VDISP

EN_1

+1V1_SW

+1V8_SW

+2V5_SW

+5V_SW

+5V5_TUN

+1V25_SW

+3V3_SW

+5VS

+5V_SW

+5VTUN_DIGITAL

+5V5_TUN

SENSE_1V8

SENSE+1V1_MT5363

+24VAUDIO

IN OUT COM

7120

6122

IN OUT COM

7120

+12VS

B04A CONTROL

+3V3STBY

B04C CONTROL B06D CONTROL

B04C CONTROL

7124 RT8283AHGSP 5115 2 5123 Synchronous 3 Step-down Converter 7125 RT8283AHGSP 5105 2 5106 Synchronous 3 Step-down Converter 6102 3130

7123 RT8283AHGSP 5120 2 Synchronous 3 5104 Step-down Converter

7122 RT8283AHGSP 5117 2 5121 Synchronous 3 Step-down Converter

STANDBY

POWER-OK

INV_STATUS

BACKLIGHT-BOOST

BACKLIGHT-PWM

LAMP-ON

DC - DC

SENSE+1V0_MT5363

1M95 1

1M99 1

B01

Supply Lines Overview

SUPPLY LINES OVERVIEW

B03

B04a

B04a,b

B02b

B02a,B03.B04c, B06d,B05a,b

B02a

B02b,B04a

B02b,B04a,c,d, B06a,B06b

B03,B04c,B06b

B03,B04a,c,d, B05a

B04d

Block Diagrams

B01

EN 41

MTK POWER

DDR

CONTROLLER

LVDS DISPLAY

+3V3_SW

+3V3STBY

7802 LCD-PWR-ONn

7800

+12VDISP

B04D

+12VS

+5V_SW

+3V3STBY

+3V3_SW

B04C

+1V8_SW

B04B

+3V3_SW

+1V8_SW

+3V3STBY

+1V1_SW

+1V25_SW

B04A

5706

1G51

+3V3_SW

+3V3STBY

1M20 5

2 3 4

+VDISP-INT 1

2011-Apr-29

5802

5801

5800

+12VDISP

+12VS

+5V_SW

+3V3STBY

+3V3_SW

+1V8_SW

+3V3_SW

SENCE_1V8

+1V8_SW

+3V3STBY

SENCE+1V1_MT5363

+1V1_SW

+1V25_SW

+24VAUDIO

+12VS

+12VS +24VAUDIO

+5V_SW

+3V3STBY

+3V3_SW

+1V25_SW

+2V5_SW

+5V_SW

+3V3STBY

CLASS-D & MUTING

+3V3_SW

+1V25_SW

B03

DIGITAL Demod

+2V5_SW

B02B

L11M1.1L LA

TO 1N01 T01A TCON

TO IR/LED PANEL

B01

VGA

VGA CONNECTOR

+5V_SW

B06D

+12VS

1E01 3E13 9 6E05

ANALOG I/O - AUDIO

+3V3_SW

B06B

5E03

+5V_SW

+3V3STBY

DC_5V

+5V_SW

+12VS

+3V3-ARC

+3V3_SW

+5V_SW

PWR5V_1

PWR5V_2

HDMI_PLUGPWR2

HDMI_PLUGPWR1

ANOLOG I/O - HEADPHONE

USB

+3V3_SW

B06A

+5V_SW

B05B

HDMI 1 SIDE CONNECTOR

1901 18

1902 18

6901

HDMI 2 CONNECTOR

+5V_SW 6900

HDMI & MUX

+3V3STBY

B05A

T01c

B08c

T01c

T01d

T01c

T01a

T01c

TO 1G51 B04D SSB

VLS_15V6

VGH_35V

VGL_-6V

7K00 ISL24837IRZ 32 VOLTAGE GENERATOR

MINI LVDS VCC_3V3

T01F

+VDISP

VREF_15V2

T01E

MPD

VLS_15V6

+VDISP

3J10 3J26

P GAMMA & VCOM & NVM

VCC_3V3

T01D

4J01

6J02 4J02 LCD 21 SUPPLY 3,4 5J00 3J12 39

7J01 5J06

7J00 ISL97653

4J04

TCON DC/DC

5H04

5H06

5H05

5H01

19130_005_110426.eps 110426

VLS_15V6

VGH_35V

VGL_-6V

VCC_3V3

+VDISP

VREF_15V2

+VDISP

VREF_15V2

VLS_15V6

VCC_3V3

VCC_1V8

VCC_3V3

VGH_35V

VGL_-6V

VLS_15V6

VLS_15V6_B

+VDISP

+VDISP-INT

VGH_35V

DDR2VDD

VDD1V8PLL

VDD1V8

VCC_1V8

VDD3V3IO

5H03

5H00

+VDISP-INT

T01C

VGH_35V

VCC_1V8

VDD3V3LVRS

VCC_3V3

+VDISP-INT

5H02

TCON CONTROL

LVDS DISPLAY

VCC_3V3

T01B

48 49 50

1N01

T01A

T01e

T01b

T01b,d,f

T01b,f

T01f

T01f,d

T01d,e

T01c

+12VS

B01A

2102

EN_1

+12VS

DC-DC

I105

EN_1

I123

SS2_GND

2157

100K 22n

3101

33R

5115

2190

SS3_GND

I132

100K 22n

3102

33R

5105

I108

SS4_GND

22n

2195

I137

BOOT

COMP GND GND HS

VIA

VIN

BOOT

COMP GND GND HS

VIA

VIN

7123 RT8283AHGSP

SS1_GND

7124 RT8283AHGSP

BOOT

COMP GND GND HS

VIA

VIN

7125 RT8283AHGSP

SS4_GND

100K I109

3103

12V/1V0 CONVERSION

SS3_GND

EN_1

I104

SS2_GND

SS3_GND

SS2_GND

12V/1V8 CONVERSION

33R

5120

3100

100K

SS1_GND

22n

2158

I120

SS1_GND

EN_1

12V/5V CONVERSION

33R

5117

12V/3V3 CONVERSION

10u

DC-DC

6102

10-1 B01 393912365052

10u

2100

BOOT

I122

I127

SS2_GND

I111

SS3_GND

SS4_GND

2124 100n

1R0

100n

1R0

3152

2187

3151

100n

1R0

SS1_GND

1R0

3149

2123

3150

COMP GND GND HS

VIA

VIN

7122 RT8283AHGSP

I117

I138

L11M1.1L LA

100n

2170

10R

10. Circuit Diagrams and PWB Layouts

BZX384-C6V8

1K0

3130

I139

2154

2168

I131

I110

RES 3u6

5123

10u

5104

RES

3u6

5106

SS3_GND

I136

10u

5121

10.

EN 42

I141

RES

I142

SS3_GND

F125

3116

SS2_GND

3117

2011-Apr-29

SS4_GND SS4_GND

15K

6122 SS36

4K7 1% 2162

SS1_GND SS1_GND

F133

F132

F135

47K

F101

SENSE_1V8

470R 3154

RES 3155

470R

ON 3V3 0V 12V 12V 12V 25V

+5V_SW

+3V3_SW

1M95 PIN 1 2 6 7 8 9

1M99 PIN ON 1 12V 5 3V 6 >1.5V 7 1.5V 9 3V

STBY 3V3 3V 0V 0V 0V 0V

STBY 0V 0V 0V 0V 0V

1 2 3 4 5 6 7 8 9 10 11

33R

5127

33R

5124

1-2041145-1

1M95

2041145-9

1 2 3 4 5 6 7 8 9 F105 F106 F107 F108 F109

F102 F103 F104

F113 F114 F115 F116 F117 F118 F119 F120 F121 F122 F123

1X02 REF EMC HOLE

1X03 REF EMC HOLE

100p

GND-AUDIO

3126 3127 3128

68R

3129

68R 68R 68R

GND-AUDIO GND-AUDIO GND-AUDIO

I144

OUT COM

I143

I125

1X05 REF EMC HOLE

OUT COM

DGND

I126

DGND DGND

33R

DGND

1X04 EMC HOLE

100n F136

22u

2122

PCB SB SSB THRILLER BRZ DIG

ROUND 4.50mm SCREW HOLE

7120 LD1117DT25 5128

33R

5125

5V/2V5 CONVERSION

7119 LD1117DT

3V3/1V2 CONVERSION

DGND DGND

2107

ROUND 4.02mm SCREW HOLE

SENSE+1V1_MT5363

+1V1_SW

+1V8_SW

3153

SS2_GND

+5V_SW

+5V5_TUN

+3V3_SW

1M99 +12VDISP

+1V25_SW

STANDBY

2011-01-13

2011-01-31

19130_016_110426.eps 110426

3139 123 6505

1X01 REF EMC HOLE

SLOT SCREW HOLE

+2V5_SW

F131

B01A LAMP-ON BACKLIGHT-PWM BACKLIGHT-BOOST INV_STATUS POWER-OK

+24VAUDIO

+12VS

+3V3STBY

10n

Circuit Diagrams and PWB Layouts

10u 2189

10u 16V

4K7

RES 2171

2172

2175

3131

10u

2160

2163 RES

10u 2153

10u 2181

2188

2176

100n

2177

100n

3146

10u

2178

100n 9

3n3 12K

3135

I106

3138 I118

2150

10R 470p

2161

3140 100K 5% 3107 22u

2179 9 9

3136 I119

2185 I107

3122 2112 I135

3114 2167 I112

3145

RES RES

22u 2101 10u 2159 100K 1%

100u 6.3V RES 100u 6.3V 3115 3125

9 3n3 10K 4n7 12K 4n7 3K6

RES RES

3108 I134

2192

10R 470p

2186 I113

3111

RES RES

2113

27K 1%

I140 5K1 1%

RES 3113 3109

10u

1K5 1% 22u 2183

470p 10R 470p

2165

2169 2142

100p 2131

RES

100p 2127 100n

22u 2152

22u 2129

RES 22u

2164

22u 22u 2130

1n0 1n0

100n

22u 2155 12K 1%

3112 68K 1% 3118 27K 1%

2140

3105

RES 2104

2137

100n 2144

2136 2141

2139 22u 6.3V 2108

22u 22u 2106

100n

100p 2133

1n0

RES 4100 100n

15K 1% 2191 3106 3148

2u2

100p 2134

2148

2128

10u 2199 1

RES 2105 100u 6.3V

1n0 1n0

2109

100u 6.3V

2149 22u 6.3V 2197

47u 16V 2110

22u 2138 12K 1% 2151 470K 5%

2193

100p

10n

100n 2125 1n0

10n 2135

2146

2132

RES 2180 100n

2126 100n 22u

100n 2147 RES 2166 2111

2143

2145

100n

2198 10n

AGND

A225

ANT_PWR NC1 RF_AGC NC2 AS SCL SDA +B IF_AGC IF_OUT+ IF_OUTIF_OUT_ANALOG

1201 VA1E1BF2403

TUNER

1 2 3 4 5 6 7 8 9 10 11 12

AGND

F201 F202 F203 F204 F205 F206 F207 F208 F209 A212 A213 A214

AGND

1n0

F213

RES 2297

AGND

100p

2295

+5VS

1K0

I220

RES 5207 5208 2258

AGND

3265

RES 2296

Tuner

AGND

10K

3264

AGND

30R 4u7 100n

AGND

+5VTUN_DIGITAL +5VTUN_DIGITAL

7217 BC847BW

I221

7218 KTK5132E

1K0

3269

I222

RF_AGC_EX

100p

AGND

RES 2262

47n

AGND

10.

AGND

RES 2213

AGND

22u

AGND

F246

F247

F242

2011-Apr-29

10K

3261

10R

3228

10R

3230

10K

3270

EN 43

DIF_P

DIF_N

IF_AGC

FE_SDA

FE_SCL

RF_AGC

RF_AGC_SW

+5V_SW

+5V5_TUN

I254 10u

5222

22u 2278 1u0

2277

Near Tuner

DIF_P

DIF_N

AGND AGND

COM

OUT

AGND

7216 LD29150DT50R

B02A

22u

75R

3263

75R

3262

AGND

I255

2280

AGND

F235

22u

RES AGND

PCB SB SSB THRILLER BRZ DIG

Near MTK5363

27p

220n 2290

2011-01-13

2011-01-31

19130_017_110426.eps 110426

VIN_ATV

VIP_ATV

+5VS

+5VTUN_DIGITAL

B02A

3139 123 6505

10n

2289

10n

220n

2287

5230

F236

AGND

220n

5225

RES 27p 5227

2285

5229

220n

5226

AGND

2284

Tuner

47u

2283

10u

2288

2282

10-2 B02 393912365052

2294

2293 2226 2225 2263

22u

10n 2279 10n

L11M1.1L LA

33p

Circuit Diagrams and PWB Layouts

2286 5228 2291

15p 15p 47n

4209 RES 4210 RES 180p 330n 180p

2281

RES

RES 3272-1 10R 1 8 RES 3272-2 10R 2 7 RES 3272-3 10R 3 6 RES 3272-4 10R 4 5 3271-1 10R 1 8 3271-2 10R 2 7 3271-3 10R 3 6 3271-4 10R 4 5

100n

RES

2K7 3332

2K7

AGND AGND

3331

TUNER_SCL TUNER_SDA

DIF_N

DIF_P

AGND

2333

F300 F301

RES 5308

18p

1n2 RES 2341

30R

3351 3352

DGND

AGND

5304

30R

5306

30R

25.4M

1301

+3V3_SW

100n

2334

AGND AGND

100R 100R

2338

2336 2337

2339 2340

3337

3349

100n

100n 100n

I308

I307

DGND DGND

2377 2378

DGND

AGND

AGND AGND

2320

2318

2314

5307

18p

DGND

RES 2379

4 2

1u0 2321

1u0 2323

2322

10n

1 41

45 46

10K

I316

I317 I318

24 25

28 27

30 29

3 2

10K

1u0 1u0

DGND

I304

SCL SDA

CKI

AGCI

0 TSMD 1

S_INFO

DTMB

DTCLK

VDDC

DGND

AGND

DGND

AGND

AD_VREF

P AD_VREF N

P ADQ_AI N

P ADI_AI N

0 XSEL 1

7302 TC90517FG

AGND

I302

I300

VSS

VDDS

13 35 49 64

)

I305

I303

I301

DGND DGND DGND DGND

2306 0 1

SCL TN SDA

SLADRS

SYRSTN

STSFLG0

AGCCNTR

AGCCNTI

STSFLG1

SRDT

SRCK

SLOCK

SBYTE

RSEORF

RLOCK

RERR

PBVAL

FIL

I306

3357

12 14

6 5

DGND

F306

20K

33R

1n5

DGND

2011-Apr-29

F302 F303

3339

3359

60 38

3358

3353

3354

2335

DGND

I325

I320

DGND DGND

DGND DGND DGND DGND

2301

100n

100n 2307 100n 2302

+2V5_SW

39p

22 23

1u0 2324

39p RES 2380

32 AD_DVDD

20 PLLVDD

AD_AVDD AD_AVSS

100n 2308 100n 2303 2311

Digital demodulator

AD_DVSS 31

16 36 56 63 PLLVSS

100n 100n

B02B

DR1VDD

34 48

4 15 33 37 44 47 50 57 62

43 DR2VDD

100n 2309 100n 2304 100n 2312 2317

1u0 1u0 1u0 1u0

100n 100n

2310 2305 2313 2316

Digital demodulator

AGND

30R

5305

30R

5303

30R

5301

30R

5302

3335

EN 44

3344

10.

2K7

L11M1.1L LA

+2V5_SW

+1V25_SW

+3V3_SW

+1V25_SW

+3V3_SW

10K 3336 3343

+3V3_SW

AGND

2332 DGND

3350

Circuit Diagrams and PWB Layouts

10K 2K7

100n 4K7 4K7

3360

RES

FE_SCL FE_SDA

RESET_DEMOD

IF_AGC

TSO_DATA0

TSO_CLK

TSO_SYNC

TSO_VALID

1K0

DEB 3356

AGND

DGND

DEB 7301 BC847BW

FOR DEVELOPMENT USE

33R

DGND

33R

5311 5310

4309

4311

I338

4307

4306

33R

5309

1K0

DEB 3355

4310

4308

SML-310

DEB 6301

AGND

PCB SB SSB THRILLER BRZ DIG

+3V3_SW

4314

4313

4312

2011-01-13

2011-01-31

19130_018_110426.eps 110426

3139 123 6505

B02B

A_STBY

F417

RESET_AUDIO

SW_MUTE

56K

RES 3409

+5V_SW

+12VS

I445

F412

F411

3K0

3437

F414

I423

4K7

3411

VIA

I425

I424

VIA

F413

I443

1R0

RES 3415

BAS316

6401

4 7402-2 BC857BS(COL)

GND-AUDIO

7402-1 BC857BS(COL)

F408

26 27 28 29

7400-2 TPA3123D2PWP

GND-AUDIO

4K7

MUTE

BAS316

47K

RES 6400

I422

RES 3408

F402

100K

F401

1u0

AOUTL

3410

40 39 38

30 31 32 33

AOUTR

3438

4R7

1K8

3413

I433

GND-AUDIO

7414 BC847BW

1K0

3412

37 36 35 34

GND-AUDIO

2422

3400

2406

47n

2407

47n

F400

I403

I401

F416

2408 1u0 I405 2409 1u0 I406

+3V3STBY

100K

+24VAUDIO

RES 3414

22K 2432

11 7 4 2

18 17

F409

6402 BAT54C I429

PVCC

PGND R

+12VS

BSL

BSR

OUT

7404 3 BC857BW

47K

3426

2402

A_STBY

I414 220n

2412

220n

2411

EN 45

I413

GND-AUDIO

I412

GND_HS

GND-AUDIO

7403 BC847BW 3 1

)

5401

+24VAUDIO

CLASS-D AUDIO AMP

AVCC

AGND

VCLAMP BYPASS MUTE SD

0 GAIN 1

I411

GND-AUDIO

4401

7405 BSS84

2401 7400-1 TPA3123D2PWP

+3V3STBY

2433

220R 2403

Class-D & muting

470u 16V

2405

10K

RES 1K0

3428

I431

I432

F415

GND-AUDIO

2011-Apr-29

1K0

3427

I416

I415

7406 2SD2653K

I418

I417

7407 2SD2653K

22u

5403

22u

5402

GND-AUDIO

AOUTR

AOUTL

2413

B03

BAT54C 6403

RES 3416

10u 35V 2404 2423

220n 2414

Class-D & muting

10K

220n 100n

220u 35V

8 9

35V 220u

2416

35V 220u

2415

RES

47K

3431

1K0

7411 RES BC857BW 3432

RES

100K

3422-1

100K

3422-4

1K0

RES 3435

F410

I436

I437

RIGHT_SPEAKER

7413 2SD2653K

RES

7412 2SD2653K

RES

GND-AUDIO

10u

100K

3422-2

100K

3422-3

2426

LEFT_SPEAKER

RIGHT_SPEAKER

GND-AUDIO

LEFT_SPEAKER

I434

3452

10-3 B03 393912365052

3439

1u0 3417

2400

19 20 I430 3419

DC-DETECTION

PCB SB SSB THRILLER BRZ DIG

HP_ROUT

HP_LOUT

RESERVED

GND-AUDIO

7408 BC847BW

DC_PROT

1K0 1K0

5400 1 3 3418

I440

220u 35V I441

220R 13 14

220n 22K 5

220n

23 24 10K

2417

22K

22K 4

6 3 3405-3

22K

3405-4 220n 2418

3451 3453

22K 8

7 1 3405-1

3405-2 220n

10 12 1K0

22K 7 4n7

22K 6 2

3 3406-3 4n7

3406-2 3420

4 3406-4

22K 8 47K 47K

3421

I435

1402 2420 1403

10.

10K

V_NOM 10n V_NOM

L11M1.1L LA

RES

3433

1K0 1K0

3454 2427

2419

Circuit Diagrams and PWB Layouts

I442

RES

4n7 4n7

2425

3430

3406-1

2424

RES

2430 2431

RES

47K 47K

3434

1u0

10n 10n

2421

220n

F406

F404 F405

1735 LEFT +

GND SND RIGHT -

GND SND

2011-01-13

2011-01-31

19130_019_110427.eps 110427

3139 123 6505

2041145-4

1 2 3 4

B03

+3V3STBY

5501

2573 100n

100n

2593

2595 2596

10u 100n

5505 30R

1u0

2571 1u0

2592

5504 30R

I507

30R

4u7

2588

5502 5503

F500

30R 30R

100n

2584

100n

2581

100n

2568

I505

100n

2552

+3V3_SW

100n

2582

I502

2577

2597

100n

2569 100n

100n

1u0

2576

100n

2580

100n

2574

2575

2570 100n

100n

2553

I506

100n

2559

2558

Y31 AF33 T31 AN32 AG34 AK31 AM13 F15 H15 W30 AL30 AM11 AN30 AN24 AK35

AH33 AG30 AP11 N16 P13 AM25 AG32 AF29 AL10 N18

AM23

I504

100n

100n 2563

100n 2562

2598

4u7

100n 2564

LVDS MEMPLL PLL_1 PLL_2 RGB USB VPLL

AADC ADAC0 ADAC1 CVBS DEMOD1 DIG HDMI LVDS_1 LVDS_2 REF_AADC SIF USB VDAC VGA_STB XTAL_STB

F502

Y33 AE34 U30 AR32 AG36 AJ30 AN12 J18 Y29 AK29 AP9 AT9 AT11 AR30 AL24 AK37

P17 T13 AH29 AH31 AN26 AM9 P19

2567

+1V1_SW

SENSE+1V1_MT5363

AADC ADAC0 ADAC1 CVBS DEMOD1 DIG HDMI LVDS REF_AADC SIF USB_1 USB_2 USB_3 VDAC VGA_STB XTAL

AVDD33 AVSS33

ADCPLL APLL HDMI LVDS MEMPLL RGB SYSPLL TVDPLL USB VPLL

AVDD12 AVSS12

AVDD10_LDO

POWER-MISC

1R0 7700-7 MT5363BIMG

3500

100n 2561

2560

1u0

100n

MT5363 Power

F501

30R

5500 +1V25_SW

SENSE_1V8

+3V3_SW

F503

+1V8_SW

2011-Apr-29

4u7

B04A

100n 2549

2550

MT5363 Power

100n 100n 2545 2544

10-4 B04 393912365052

100n 100n 100n

2599

EN 46

100n

2543 2542 2541

2566

10.

100n

2565

5506 2514

L11M1.1L LA

2551

30R 4u7

2540

4u7

100n 2515

2538

2579

4u7

100n 100n 100n

22u

2537 2536 2535

2507

100n 2516

100n 100n 100n 2534 2533 2532

Circuit Diagrams and PWB Layouts

100u 6.3V

100n 2501

100n 2518

100n 100n 100n

2500

100n 2517 100n 2502 100n

100n

100n 2520

2531 2530 2529

2508

100n 2519 100n

2503 100n

2504 100n 2510

100n 2505 100n

100n 100n 100n

2512

100n 2522

2528 2527 2526

2509

100n 2521 100n 2506 100n 2513 100n 100n 100n 2525 2524 2523

4u7

R16 U14 V13 Y13 Y15 AA14 AD15 AD17 AD19 AE14 AE16 AE18 AG12 AH7 AJ6 AJ8 AK5 AK7 AL2 AL4 AL6 AL8 AM1 AM3 AM5 AM7 AN2 AN4 N22 N24 T25 V25 W24 Y25 AA24 AB25 AE20 AE22

B1 B13 C2 C12 D3 D13 E4 E12 E14 F5 F13 G6 G14 H7 J14 R2 R4 R6 AC6 AD5 AD7 AE2 AE4 AF1 AF3

AF13 AF15

H23 H31 J30 V31 W32 W34 W36

VCCK

VCC2IO

VCCIO33-1

VCCIO33

DVSS

POWER-MAIN

7700-8 MT5363BIMG C8 D9 E8 F9 G8 G10 J4 J6 L4 L6 N14 P15 R14 R18 T15 T17 T19 U16 U18 V15 V17 V19 W4 W6 W14 W16 W18 Y3 Y17 Y19 AA16 AA18 AB13 AB15 AB17 AB19 AC14 AC16 AC18 AD13 AE8 AF9 B21 D21 E22 G22 N20 P21 P23 P25 R20 R22 R24 T21 T23 U20 U22 U24 V21 V23 W20 W22 Y21 Y23 AA20 AA22 AB21 AB23 AC20 AC22 AC24 AD21 AD23 AD25 AE24

PCB SB SSB THRILLER BRZ DIG

2011-01-13

2011-01-31

19130_021_110427.eps 110427

3139 123 6505

B04A

+1V8_SW

2630

RODT RCS# RWE# RCAS# RRAS#

RCLK0 RCLK0# RCLK1 RCLK1# RCKE

RBA(0) RBA(1) RBA(2)

RA(0) RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12) RA(13)

1K0 1%

3622

F602

DDR

100R

1K0 1%

B04B

AB5 N6 P3 K3 L2 P5

B3 A2 AD1 AD3 K1

H3 J2 H1

N4 H5 M3 G4 M5 F1 M7 F3 P1 D1 G2 N2 E2 M1

N8 P7

REXTDN RODT RCS RWE RCAS RRAS

RCKE

RCLK1

RCLK0

0 1 RBA 2

0 1 2 3 4 5 6 RA 7 8 9 10 11 12 13

1 RVREF 2

DRAM

7700-3 MT5363BIMG

0 1 2 3

RDQS3

RDQS2

RDQS1

RDQS0

RDQM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RDQ 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RDQ(0) RDQ(1) RDQ(2) RDQ(3) RDQ(4) RDQ(5) RDQ(6) RDQ(7) RDQ(8) RDQ(9) RDQ(10) RDQ(11) RDQ(12) RDQ(13) RDQ(14) RDQ(15) RDQ(16) RDQ(17) RDQ(18) RDQ(19) RDQ(20) RDQ(21) RDQ(22) RDQ(23) RDQ(24) RDQ(25) RDQ(26) RDQ(27) RDQ(28) RDQ(29) RDQ(30) RDQ(31) RDQM(0) RDQM(1) RDQM(2) RDQM(3) RDQS(0) RDQS(0)# RDQS(1) RDQS(1)# RDQS(2) RDQS(2)# RDQS(3) RDQS(3)#

D7 H11 E6 G12 H13 D5 F11 F7 B5 D11 A4 B11 A12 C4 A10 A6 AB1 U4 AC4 T1 T3 AC2 U2 AB3 Y5 T7 AA6 V7 V5 AA4 T5 Y7

E10 C10 V1 U6

B9 A8 B7 C6 V3 W2 Y1 AA2

RDQS(2) RDQS(2)# RDQS(3) RDQS(3)#

RCLK1#

RCLK1

RA(0) RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12)

RBA(0) RBA(1)

RODT RCKE RWE# RCS# RRAS# RCAS#

RDQS(0) RDQS(0)# RDQS(1) RDQS(1)#

RCLK0#

RCLK0

RA(0) RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12)

RBA(0) RBA(1)

RODT RCKE RWE# RCS# RRAS# RCAS#

L11M1.1L LA

22R 1%

3613

22R 1%

3612

3614 3617

22R 1%

3618

+1V8_SW

56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R

3603-4 3603-3 3600-2 3604-2 3602-4 3604-4 3602-2 3601-4 3602-3 3601-3 3600-4 3601-1 3604-3 3602-1 3601-2 3605-1 CK

LDQS

UDQS

F7 E8 B7 A8

0 1 2 3 4 5 6 A 7 8 9 10 11 12

0 BA 1

ODT CKE WE CS RAS CAS

J8 K8

M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2

L2 L3

K9 K2 K3 L8 K7 L7

+1V8_SW

L2 L3 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R

3610-1 3610-2 3606-2 3609-3 3608-1 3609-1 3608-3 3607-1 3608-2 3607-2 3606-4 3607-4 3609-2 3608-4 3607-3 3611-4

B7 A8

F7 E8

J8 K8

M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2

K9 K2 K3 L8 K7 L7

56R 56R 56R 56R 56R 56R

3611-3 3610-3 3610-4 3611-1 3611-2 3606-1

7601 H5PS5162FFR-G7C

56R 56R 56R 56R 56R 56R

7600 H5PS5162FFR-G7C 3605-2 3603-2 3603-1 3605-4 3605-3 3600-1

EN 47

3619

2011-Apr-29

100R

22R 1%

10.

VSS

VDD

A1 E1 J9 M9 R1

DDR

100n 3623

3624

Circuit Diagrams and PWB Layouts

100R

UDQS

LDQS

0 1 2 3 4 5 6 A 7 8 9 10 11 12

0 BA 1

ODT CKE WE CS RAS CAS

VSS

VDD

SDRAM

VSSQ

VDDQ

) SDRAM

VSSQ

VDDQ

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

VREF

UDM LDM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

VREF

UDM LDM

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

)

B3 F3

G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9

A2 E2 L1 R3 R7 R8

F600

56R

56R 3600-3

3604-1

B3 F3

G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9

A2 E2 L1 R3 R7 R8

F601

56R

56R 3606-3

3609-4

100n 2620

VDDL

100n 2600 100n 2621

VSSDL

100n

100n 2601 100n 2622

1K0 1%

3615

2608

1K0 1%

3620

2628

2602 100n 2623

A3 E3 J3 N1 P9 A1 E1 J9 M9 R1 A3 E3 J3 N1 P9

100n 2603 100n 2624

J7 J1 VDDL VSSDL J7

100n 2604

3616

100n 1K0 1% 2629

2625

100n

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

100n 2605

1K0 1% 2609

3621

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

100n 2606 100n 2626

100n

100n 2607 100n 2627

47u 16V 47u 16V

+1V8_SW

PCB SB SSB THRILLER BRZ DIG

RDQM(3) RDQM(2)

RDQ(16) RDQ(17) RDQ(18) RDQ(19) RDQ(20) RDQ(21) RDQ(22) RDQ(23) RDQ(24) RDQ(25) RDQ(26) RDQ(27) RDQ(28) RDQ(29) RDQ(30) RDQ(31)

RA(13)

RBA(2)

RDQM(1) RDQM(0)

RDQ(0) RDQ(1) RDQ(2) RDQ(3) RDQ(4) RDQ(5) RDQ(6) RDQ(7) RDQ(8) RDQ(9) RDQ(10) RDQ(11) RDQ(12) RDQ(13) RDQ(14) RDQ(15)

RA(13)

RBA(2)

2011-01-13

2011-01-31

19130_022_110427.eps 110427

3139 123 6505

B04B

USB_DP USB_DM

LIGHT-SENSOR

LED-2

3732

+3V3_SW

100R

+3V3STBY

54M

1700

3758

F742

F741

OPCTRL3(0) 0

AOSDATA0 1

TRAP2 XTAL 54MHZ

10K

TRAP1 PDWNC Normal

0 0

AOLRCK

+3V3_SW

VOUT

SUB GND

VDD

F702

10p

10K

+3V3_SW

+3V3STBY

ICE mode + Serial Boot ICE mode +ROM mode

TRAP0

SDA-MAIN SDA-DISP

SCL-MAIN SCL-DISP

KEYBOARD RESET_AUDIO

LED-1

10K

7701 BD45292G

I725 1

30R

5701

4u7

2710

6707

3701

100n

INV_STATUS

2709

3769

BAS316

2730

RES

10p

3706

4K7

100n

3707

RES 2701

F701

I758

+3V3_SW

4K7

F721

1K0

3700

2716

4u7

100K

RES 37AB

OPWM1 0

0 0

AOBCK

10K

RES 3731

3735 3737

0 1

ASPDIF

+3V3STBY

100R 100R

RES 3788

3787

10K 10K

3761 10K

3722 3723

JTCK JTDO JTRST JTDI JTMS

I747

I733

I754 I753

I759 I756 I757

ORESET

I735

AU10 AR10 AN10

AL32 AK33 AM35 AL34 AM37 AL36

AP1 R32 P33

AP3 R34 P31

AK3 AH5 AK1 AJ2 AJ4

AL22 L30 K5 K7 M19

T37

AJ34

AJ36

7700-1 MT5363BIMG

DP DM USB VRT

0 1 2 ADIN_SRV 3 4 5

0 1 OSDA 2

0 1 OSCL 2

JTCK JTDO JTRST JTDI JTMS

RX TX RX TX

CLK DATA BYPASS

AGC

IF RF

BYPASS0 ADCINP ADCINN

DEMOD

TUNER

PWR5V

CEC SDA1 HDMI SCL1 SDA2 SCL2

OPWRSB

0 1 OPCTRL 2 3 4

OIRI

0 OPWM 1 2

PAALE PACLE POWE POOE

PARB

0 1

0 1 2 3 PDD 4 5 6 7

1K0

3741

POCE

CONTROL

ORESET FSRC_WR MEMTN MEMTP TP_VPLL

VCXO

XTALO

XTALI

BACKLIGHT-BOOST

1u0

4K7

SDM

2717

100n RES

2700

2706

37AA

BAS316 3768

100n

PANEL

10K

RES

4K7

4K7 4K7

3718 3719

4K7

6706

2711

RES

10K

RES 4K7

3720 3721

RES 3757

37A5

+3V3_SW

RES 2705

10K

3783

3734

3738

3744

3751

I760

I746

I734 I739

I750

AM21 AM19 AN20 AR20 AU20

AL20

+5V_SW

M31 M33

AM31 AH37 AH35

N36 N34 AP37

AL16 AM15

AN14 AN18 AM17 AL14 AL12

AN22

J34 J36 T33

AT21 AP21 R36 T35

3727 3728

1R0

3739

I744 I745

AR4 AU4 AT3 AU2

AT5

AT1 AN6

3796

RES 37A9 100R

3784 3785

100R

100R 100R

100R

4K7

100R 100R

I713

+3V3_SW

10K

4707 4708

10K 10K

+3V3_SW

I749

3709 100R 3710 4K7

+3V3_SW

NAND_PARB

NAND_PCLE NAND_PALE NAND_POCE NAND_POOE NAND_POWE

NAND_PDD(0) NAND_PDD(1) NAND_PDD(2) NAND_PDD(3) NAND_PDD(4) NAND_PDD(5) NAND_PDD(6) NAND_PDD(7)

+3V3_SW

NAND_PALE NAND_PCLE NAND_POWE NAND_POOE

NAND_PARB

NAND_POCE

NAND_PDD(0) NAND_PDD(1) NAND_PDD(2) NAND_PDD(3) NAND_PDD(4) NAND_PDD(5) NAND_PDD(6) NAND_PDD(7)

RES RES

RES FOR ITV

BOOST_CONTROL

4700 RES

SYS_EEPROM_WE

F738 F739 F740

I711

AR2 AP5 AR6 AU6 AP7 AT7 AR8 AU8

10K

10K 10K

ARC_SW

5K1 1%

10n

3740 RES

3782 RES

F737

2K2

3703

RESET_DEMOD

47n

RF_AGC_SW

37A8

3786

2719

J26 F25 H25 B25 D25 C24 G24 E24 J24 B23 F23 D23 A22 C22 AF5 AG2 AE6 AF7 AG4 AG6 AH3 AH1

3753

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

4K7

47n

2720

F759

F760

4K7 4K7

RES 3774 RES 3775

GPIO 0 1 2 3 4 5 6 7 8 9 10 11 GPIO GPIO 12 13 14 15 16 17 18 19 20 21 22

+3V3_SW

VCOM_SW POWER-OK DC_PROT

LAMP-ON

BYPASS_MODE LCD-PWR-ONn

F761

+3V3STBY

+3V3_SW

+3V3STBY +3V3STBY

3733

K35 K37 J32 A30 C30 G30 E30 H29 F29 B29 D29 C28 E28 J28 G28 H27 F27 B27 D27 G26 E26 A26 C26

4K7

3746 10K 10K 10K

RES 37A6 RES 37A7

F766

10K

3730

33R

3749

I755

HDMI_CEC

MUTE

POWER_DOWN SDA-LCD SCL-LCD SW_MUTE

I761

STANDBY

2011-Apr-29

VIP_ATV VIN_ATV IF_AGC RF_AGC

HDMI_SDA2 HDMI_SCL2 SIDE_HDMI_SDA1 SIDE_HDMI_SCL1 F743 PWR5V_2 F744 PWR5V_1 TUNER_SCL TUNER_SDA

7710 BC847BW

33R

3748

I726

I727

I742 I743

SDA-MAIN

SCL-MAIN

+3V3STBY

+3V3_SW

4K7

3716 3717

CLE ALE CE_ RE WE WP SE R B

0 1 2 3 IO 4 5 6 7

I731

VSS

VCC

3724

POWER_DOWN

22R 22R

F717

1 2 3 4 5 10 11 14 15 20 21 22 23 24 25 26 27 28 33 34 35 38 39 40 45 46 47 48

F718

F707 I708

33R

3712

7703 BC847BW

F705

BACKLIGHT-PWM

16 17 9 8 18 19 6 7

29 30 31 32 41 42 43 44

7708 H27U1G8F2B

F736

F708

F706

+3V3_SW

F725

F716

+3V3_SW

100n I737 2

1701

I738

I716

7705 BC847BW

+3V3_SW

7709-2 3 BC847BS(COL) 5

2 3 1

MSJ-035-29D PPO UART (SERVICE)

1 2 3

I741

1K0

3770

+3V3_SW

6709 BZX384-C8V2

F724

4K7

3745

PWM DIMMING

BACKLIGHT_CONTROL

+3V3_SW

0 1 2

4K7

ADR

I715

3767 15K

100n

3711

2702

EEPROM

(8K × 8)

)

+3V3STBY

7709-1 BC847BS(COL)

1K0

3764

100R

3781

220R

5705

SDA

SCL

7702 M24C64-WDW6

F704

30R

USB_PWR_EN USB_OCP EDID_WC

3754

4K7 3747 3729

4K7 3777

4K7 3776 4K7 10K

I732 RES 3779 3756

10K 10K 3715 3714

4K7

1R0

10K 3778 4K7

4K7

12 13 BZX384-C6V8

I700 I701

3789

3702

2703

100R 100R

6700

3713

10K BZX384-C6V8

3704 3705

6708

8 4

RES

1705

RES

36 6701

10p 2704 2713 1706

10p 100n 2712

5700 F719

3726

3742

7700-4 MT5363BIMG

2721

+3V3_SW

1K0

+3V3_SW

+12VS

3736

Controller

BZX384-C3V3

B31 E32 C32 A32

E34

D31

D33

E36

D37

F33

H37

G36

F37

F751

KEYBOARD

LED-1

LED-2

D3 D2 D1 D0

CLK

H33

C34 A34 B35 A36

B37

D35

B33

F31

G32

C36

F35

H35

G34

+3V3_SW

6K8

3794

100R

3793

100R

3792

100R

3791

10p +3V3_SW

PCB SB SSB THRILLER BRZ DIG

10R

3795

RES100R

+3V3_SW

3798

33R

DEB 3765

ETRX

+3V3STBY

LIGHT-SENSOR

JTDO

ETCOL

ETCRS

MCLKI

MDI0

MIVAL

MISTRT

ETPHYCLK

MAC-CI

ETTX

JTRST JTDI JTMS JTCK

D3 D2 D1 D0

CLK

ETMDC

ETMDIO

MCLKO

MDO0

MOVAL

MOSTRT

7700-6 MT5363BIMG

RES 3790

B04C

680R 220n

1K0

4K7 I714

RES 2729

10K 10K 10K 10K 10K

DEB 3780 DEB 3763-1 DEB 3763-2 DEB 3763-3 DEB 3763-4 100K

1K0

DEB

Controller

RES 3743 3771

DEB 2722 2724 RES 2725 2726

2723

3762

1n0 1n0 1n0 1n0 100n

TSO_SYNC

3759

DEB 10K

+5V_SW

+3V3STBY 5706 30R

F763

TSO_CLK

TSO_DATA0

TSO_VALID

1702

F754 F755 F756 F757 F758

F753

F765

DEB

502382-1170

1 2 3 4 5 6 7 8 9 10 11 13

1M20

2011-01-13

2011-01-31

19130_023_110427.eps 110427

2041145-8

1 2 3 4 5 6 7 8

FOR DEBUGGING ONLY

B04C

3139 123 6505

F745 F746 F747 F748 F749 F750

10K

EN 48

2727

10.

100n

L11M1.1L LA

2728

Circuit Diagrams and PWB Layouts

100n

3760

7803 BC857BW

47R

3803

47K 6800

3802

10K

3808

I806

I802

BZX384-C6V8

I800

+12VDISP

+5V_SW

RES 4800 RES 4801 RES 4802

4811

4821 4822

4812 4815 4813

4819 4820

Y Y -

I807

10K 7802-1 BC847BS(COL) 1

3807

1u0

2806

Y Y Y

Y Y

4806 RES 4807 RES 4808 RES 8 3 7 6 2 1 5

4803 4804 4805

I808

+3V3STBY

7800 SI4835DDY

I801

7802-2 BC847BS(COL) 4

47K

Y Y

3805

4817 4818

Y Y

15K

4810 4814 4816

PCA9515 - (RES)

PCA5940

3806

LVDS Display

33R

33R 5802

33R 5801

5800

2807

B04D

I809

1K0

3809

+VDISP-INT

1K0

F800

PX2EPX2E+

PX2DPX2D+

PX2CLKPX2CLK+

PX2CPX2C+

PX2BPX2B+

PX2APX2A+

PX1EPX1E+

PX1DPX1D+

PX1CLKPX1CLK+

PX1CPX1C+

PX1BPX1B+

PX1APX1A+

VCOM_SW

SDA_VGA

SCL_VGA

LCD-PWR-ONn

10.

RES

4820

4818

2011-Apr-29

4817

EN 49

100n

2802

RES 4812

1 SDA

SCL

4819

INP FIL

7801 PCA9540B

+3V3_SW

VSS 6

I2 C -BUS CTRL

VDD

4810

LVDS Display

220n 3810

SD1

SC1 SD0

SC0

RES 4821

4816

RES 4824

4814

RES 4813

2803

RES

F833

F825 F826 F827 F828

F823 F824

F831 F817 F818 F819 F820 F821 F822

F813 F814 F815 F816

F811 F812

F805 F806 F807 F808 F809 F810

RES 4823 +VDISP-INT

10n

SDA-VCOM

SCL-VCOM

F829

60 58 56 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

61 59 57 55 53

LVDS#1 1G51

F801

PCB SB SSB THRILLER BRZ DIG

FI-RNE51SZ-HF-R1500

F834

BYPASS_MODE

F832

SCL-DISP

SDA-DISP

RES 4815 2804

L11M1.1L LA

100u 16V 2805

Circuit Diagrams and PWB Layouts

100n

4822 RES

4811 RES

2011-01-13

2011-01-31

19130_024_110427.eps 110427

3139 123 6505

B04D

AP17 AT17 AR18 AU18 AP19 AT19 AR16 AU16

AL18

AP13 AT13 AR14 AU14 AP15 AT15 AR12 AU12

AN16

M_RX2_0 M_RX2_0B M_RX2_1 M_RX2_1B M_RX2_2 M_RX2_2B M_RX2_C M_RX2_CB

HDMI_HPD2

M_RX1_0 M_RX1_0B M_RX1_1 M_RX1_1B M_RX1_2 M_RX1_2B M_RX1_C M_RX1_CB

SIDE_HDMI_HPD1

M_RX2_0 M_RX2_0B

M_RX2_0

M_RX2_CB

M_RX2_2 M_RX2_2B

M_RX2_2

M_RX2_1B

M_RX1_0 M_RX1_0B

M_RX1_0

M_RX1_CB

M_RX1_2 M_RX1_2B

M_RX1_2

M_RX1_1B

9 10

HDMI_HPD2

0 0B 1 1B RX2 2 2B C CB

HDMI_HPD1

0P 0N 1P 1N 2P 2N AE 3P 3N 4P 4N CKP CKN

0P 0N 1P 1N 2P 2N AO 3P 3N 4P 4N CKP CKN

HDMI-LVDS

7700-5 MT5363BIMG

6 7

RES 6916 IP4281CZ10

6 7

RES 6915 IP4281CZ10

6 7

RES 6914 IP4281CZ10

6 7

0 0B 1 1B RX1 2 2B C CB

8 5

1 3

8 5

1 3

8 5

1 3

8 5

1 3

PX2A+ PX2APX2B+ PX2BPX2C+ PX2CPX2D+ PX2DPX2E+ PX2EPX2CLK+ PX2CLK-

PX1A+ PX1APX1B+ PX1BPX1C+ PX1CPX1D+ PX1DPX1E+ PX1EPX1CLK+ PX1CLK-

G16 E16 H17 F17 G18 E18 G20 E20 H21 F21 H19 F19

D15 B15 C16 A16 D17 B17 D19 B19 C20 A20 C18 A18

M_RX2_CB M_RX2_C

M_RX2_0B

M_RX2_C

M_RX2_1B M_RX2_1

M_RX2_2B

M_RX2_1

M_RX1_CB M_RX1_C

M_RX1_0B

M_RX1_C

M_RX1_1B M_RX1_1

M_RX1_2B

M_RX1_1

F900

HDMI_HPD2

HDMI_SDA2

HDMI_SCL2

SIDE_HDMI_HPD1

eHDMI+ SIDE_HDMI_SCL1 SIDE_HDMI_SDA1

RES 3914 F912

RES 4901

4900

5900

4K7 RES 3921

6902

HDMI_PLUGPWR1

RB521S-30

I902

I906

RES 7907 MMBT3904

2011-Apr-29

I905

RES 4903

HDMI_CEC_A

HDMI_CEC ARC_eHDMI+

27K

HDMI_PLUGPWR2

4902

PWR5V_2

RES 7905 MMBT3904

F915

PWR5V_1

30R

+3V3STBY

3908

RES 6913 IP4281CZ10

HDMI_CEC_A

7908 BSH111 RES

F914

M_RX2_CB HDMI_CEC_A

M_RX2_0B M_RX2_C

M_RX2_1B M_RX2_0

M_RX2_2B M_RX2_1

M_RX2_2

1902

21 23 47266-9002

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22

HDMI PORT 2 (SIDE)

4904

+3V3STBY

10p

HDMI & Multiplexer

2902

B05A

M_RX1_CB

M_RX1_0B M_RX1_C

M_RX1_1B M_RX1_0

M_RX1_2B M_RX1_1

1901

21 23

0 1 2

F911

0 1 2

SCL

+5V_SW

ADR

+5V_SW

10K

3904

F905

7903 MMBT3904

PCB SB SSB THRILLER BRZ DIG

PWR5V_2

I916

F908 HDMI_SDA2 5

F906 6

SCL

SDA

F904

F907 HDMI_SCL2

F913

HDMI_PLUGPWR1

H : WRITE

L : WP

EDID_WC

1 2 3

(256 × 8) EEPROM

)

HDMI_PLUGPWR1

7900 M24C02-WMN6

HDMI_PLUGPWR1

SDA

F909

EDID_WC

ADR

HDMI_PLUGPWR2

1 2 3

) (256 × 8) EEPROM

7901 M24C02-WMN6

HDMI_PLUGPWR2

47266-9002

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22

HDMI PORT 1 M_RX1_2

6903

HDMI & Multiplexer

2901

10-5 B05 393912365052

4K7

3K3

3916 3919 3920

3912 3913

3K3 3907 1K0 100K 3K3 3915 1K0 100K

CDS2C05HDMI2 5.6V 100n

EN 50

RES 6917

3906 3K3

BAT54C

10.

CDS2C05HDMI2 5.6V

4 DEB 3923

6900

L11M1.1L LA

10K

3901

PWR5V_1

SIDE_HDMI_SDA1

7902 MMBT3904

2011-01-13

2011-01-31

19130_025_110427.eps 110427

3139 123 6505

I915

F903

SIDE_HDMI_SCL1

F901 F902

B05A

10K

Circuit Diagrams and PWB Layouts

68K 3905 BAT54C

8 4 DEB 3924 1 2

100n 6901

4K7 10K

2900 4K7 1 2

68K 3902 3903

3900

USB

1 5V 2 USB_DM 3 USB_DP FD00 4 5

USB-01-PBT-B-30-CU2

1D01

USB FD01

1D04

B05B

FD02

1D05

USB

FD03

6D00

Circuit Diagrams and PWB Layouts L11M1.1L LA

10.

33R

5D00 5

FD06

OC_

2 OUT

7D00 TPS2041BD

2011-Apr-29

FD07

EN 51

GND 1

2D11 10u

BZX384-C6V8

1D03

IN 2

EN_

FD04

FD05

2D12 100n

2D14 100u 16V

+5V_SW

USB_DP

USB_DM

USB_OCP

USB_PWR_EN

PCB SB SSB THRILLER BRZ DIG

2011-01-13

2011-01-31

19130_026_110427.eps 110427

3139 123 6505

B05B

PBS_HPR

RESET_AUDIO

HPOUTR

HPOUTL

PBS_HPL

4A03 RES

4A02 RES

HP_ROUT

1u0

1u0 RES 2A08

FA07

RES 3A18

RES 2A07

FA06

RES

10K

RES 3A17

3A19

10K 10K

RES 2A02

HP_LOUT

RES

1R0

3A03

RES

1R0

3A04

1n0

RESERVED

22K

RES 3A09

1u0

RES 2A11

10K

RES 3A16

IA03 IA04

10K

RES 3A15

IA02

22K

RES 3A10

RES RES

Analog I/O - Headphone

6A01 6A00

B06A

1n0 1n0

1n0 RES 2A13

PESD5V0S1BA RES 1A03 PESD5V0S1BA RES 1A02

Analog I/O - Headphone

RES 2A05 RES 2A04

10-6 B06 393912365052

47n 47n

IA10 3

FA02

RIGHT

IN-

VDD

VO 2

VIA GND GND_HS

BYPASS

SHUTDOWN

)

AMPLIFIER 1

+3V3_SW

RES 7A00 TPA6111A2DGN

FA03

EN 52

LEFT

10.

2011-Apr-29

RES 2A01

RES 2A12

L11M1.1L LA

Circuit Diagrams and PWB Layouts

RES 2A10 10 11

IA08

IA09

FA04

1u0

100u 4V

100u 4V RES 2A09

RES 2A06

IA01

IA00

MSJ-035-12D-B-AG-PBT-BRF

1A01 2 RES 3 1

HEADPHONE

33R

33R RES 3A14

RES 3A13

33R

RES 3A12

33R

RES 3A11

PCB SB SSB THRILLER BRZ DIG

FA09

FA08

HP_ROUT

HP_LOUT

2011-01-13

2011-01-31

19130_027_110427.eps 110427

3139 123 6505

B06A

CVBS_AV3

GND_CVBS

SOY0-AV1

SOY1-AV2

SY0N SY1N

SPR0P SPR1P SPB0P SPB1P SY0P SY1P

PREAMPL

3B00

3B02

3B01

3B03

3B05

PREAMPR

10u

2B51

1R0

100R

68R

IB27

2B55

10u

1n5

2B00

+12VS

IB53

10K

3B45

10K

3B41

10n

2B02

IB48

10n

2B03

2B01

10n

2B05

FB08

IB37

IB35

IB33

IB31

IB29

IB52

22K

3B46

5K1

3B52

IB51

IB49 5K1

3B50

22K

3B40

100R

1u0 3B14

2B15

3B06

3B08

3B07

3B09

3B11

2B14

7B01-2 LM833

IB50

LM833 7B01-1

47n

+12VS

1n5

2B08 10n

100R

2B06

2B07 10n

68R

1R0

2B09 10n

68R

10n

2B11

68R

IB47

IB45

IB43

IB41

IB39

10u

2B58

10u

2B59

IB63

IB61

DEB

3B51

GP BP

3B53

IB25 IB26

75R AOUTR

AOUTL

AR24

AU24 AT23

AP23 AT25

AM29

AP31 AT31

AR36 AT37 AU36 AP35 AT35

AP25 AP33 AR34 AT33 AU34

SOY0AU28

AR26

Y0NAT29

AP27 PB0PAP29 AT27 Y0PAR28 AU26

FS_VDAC

OUT1 VDAC OUT2

0N 0P 1P CVBS 2P 3P

0 SOY 1 0 SY 1 0 SC 1

0 COM 1

0P PR 1P 0P PB 1P 0P Y 1P

COM

GP BP

SOG RP

HSYNC VSYNC

0 1 2 3 IB22

AF35

4K7

2B25

ASPDIF_OUT

ARC_SW

10u

RES 2B24

2B17

RES 2B16

4K7

100n RES 3B39

4K7 IB17 2B42

+3V3_SW

10u

1R0

3B54

+3V3_SW

IB71

IB21

IB19

+3V3_SW

4K7 4K7

SAV_L_IN SAV_R_IN

3B37

3B38

3B35 3B36

+3V3_SW

IB20

IB18

IB16

IB14 IB15

IB10 FB02 IB12 IB13

AE36 V33 U34 U36

AF37 U32 V35 V37

L32

K33

L36 P35 P37 K31 N32

L34 M37 M35

AA30

AD33 AC34 AB31 AC32 AD35 AB35 AC36 AB37 AA32 AB33 AA34 Y35 AA36 Y37

AN34 AN36

AM33

2011-Apr-29

AVICM

0 1 AL 2 3

ALIN

ASPDIF

0 1 AOSDATA 2 3 4

AOBCK AOLRCK AOMCLK

VMID_AADC

0_L 0_R 1_L 1_R 2_L 2_R 3_L AIN_AADC 3_R 4_L 4_R 5_L 5_R 6_L 6_R

P N

MPX

AUDIO-VIDEO

7700-2 MT5363BIMG

1u0

+3V3-ARC

FB09

7B05-2 74LVC00APW 4

+3V3_SW

7B05-1 74LVC00APW 1

IB70

DVI_AUL_IN DVI_AUR_IN

AIN0_L-AV1 AIN0_R-AV1 AIN1_L-AV2 AIN1_R-AV2

+3V3-ARC

2B40

AR22 AU22

PR0PAU30

560R

IB23 IB24

10u

47K

EN 53

2B43

SOG RP

220p

100n

FB03

RES 3B18 +3V3_SW

+3V3_SW

100n

2B61

47K

3B49 13

7B05-4 74LVC00APW 12

7B05-3 74LVC00APW 9

IB72

+3V3-ARC

30K

3B34

30K

3B31

IB09

IB01

3B56 180R 100n

SPDIF_OUT

10u

2B37

10u

2B34

2B62

HPOUTR PREAMPR

HPOUTL PREAMPL

ASPDIF_OUT

NEAR CONNECTOR

IB03

IB02

RES IB74

2B20

3B16

3B15

IB00

IB08

1n0 33p

100R

240R

1R0

3B33

1R0

3B32

100n

2B63

FB04

PCB SB SSB THRILLER BRZ DIG

1n0

IB66 IB67

2B52

2B56

DEB 3B58 47K

100n

RES 3B17

2B35

RES 2B38

10.

3B57

HSYNC VSYNC

3B43

100n

RES 2B36 RES 2B39

Analog I/O - Audio

47K

3B44

47K

RES 6B00 RES 6B01

B06B

2B54

3B48

1n0 1n0

L11M1.1L LA

68R

1B03 eHDMI+

33p

FB07

FB06

MSJ-035-29D PPO

1B01

2011-01-13

2011-01-31

19130_028_110427.eps 110427

MTJ-032-21B-43-NI

1B02

SPDIF

2 3 1

AUDIO IN

B06B

3139 123 6505

FB01

FB00

SPDIF_OUT

1B04

Circuit Diagrams and PWB Layouts

1B05

PESD5V0S1BA PESD5V0S1BA

Analog I/O - Audio

820p

3B42

2B60

2B50

2B57

30R

1u0

2B53

1u0

3B55

2B44

10K

2B41

14 7 14 7

47K 14 7 14 7

2B19

3B47

47K

WHITE

1C03-3 RED

5 4 6

MTJ-032-37BAA-432 NI

(RED)

MTJ-032-37BAA-432 NI

(WHITE)

LEFT1C03-2

1C03-1 YELLOW2

MTJ-032-37BAA-432 NI

(YELLOW)

RIGHT

CVBS

8 7 9

FC00

SIDE AV

SY1N

SY1P

SOY1-AV2

SPB1P

SPR1P

AIN1_L-AV2

FC01

FC02

FC03

30K

3C27

30K

IC18

IC17

IC16

IC15

RES 6C05

RES 6C06

RES 6C07

AIN1_R-AV2

3C26

PESD5V0S1BA

10u

2C23

10u

2C22

3C09

1R0

3C11

1R0

IC05

1R0

3C06

IC03

IC07

IC01

IC02

RES 2C00 RES 2C02

NEAR CONNECTOR

75R

RES 2C08

RES 2C11

30K

3C10

3C19 30K

10u

NEAR CONNECTOR

IC04

56R

2C14

10u

2C09

1R0

3C07

5C02

3C25 60R

60R

18R

5C01

18R

60R

18R

3C22

5C00

3C20

1R0

3C01

1R0

3C00

RES 2C01 RES 2C03

Analog I/O - Video

3C08

15p

1n0

RES 2C12

1n0 1n0

B06C

2C07

RES 6C00 RES 6C01

Analog I/O - Video

1C05

1C06

1C07

47p

RES 2C10

RES 2C13

2C06

1n0 1n0 56R 56R

PESD5V0S1BA

RES 6C03 RES 6C04

RES 6C02

PESD5V0S1BA 1202 PESD5V0S1BA 1C17 PESD5V0S1BA 1C18 PESD5V0S1BA 1C19

IC20

IC19

SY_CVI2

PB_CVI2

PR_CVI2

10.

FC06

FC05

FC04

FC07

SAV_R_IN

SAV_L_IN

CVBS_AV3

1C02 MSP-636V1-01

2011-Apr-29

GND_CVBS

10 11 12

1 FC08 2 3

FC09

CVI 2

EN 54

SY0N

SY0P

SOY0-AV1

SPB0P

SPR0P

AIN0_L-AV1

AIN0_R-AV1

10u

IC22

IC21

IC13

2C25

30K

10u

3C29

2C24

30K

IC11

1R0

3C18

NEAR CONNECTOR 3C28

IC14

IC10

IC09

60R

60R 5C05

3C24 18R

5C04

18R

60R

5C03

3C23

18R

3C21

1R0

3C13

1R0

3C12

RES 2C21

L11M1.1L LA

2C15

15p 15p

15p 3C02 15p 3C04 15p 3C05

2C17 2C16

1n0 1n0

RES 2C19

Circuit Diagrams and PWB Layouts

15p

RES 2C20 3C17

1n0 1n0 56R 56R

2C04 2C05 1n0 1n0

RES

6C09 RES 6C10

RES 2C18 3C14 3C16

6C19 RES 6C20 RES 6C08

PESD5V0S1BA 1C14 PESD5V0S1BA 1C15 PESD5V0S1BA 1C10 PESD5V0S1BA 1C09 PESD5V0S1BA 1C08

56R

1C16

0001

SY_CVI1

PB_CVI1

PR_CVI1

PCB SB SSB THRILLER BRZ DIG

FC14

FC13

FC12

FC11

FC15

FC10

10 11 12

2011-01-13

2011-01-31

19130_029_110427.eps 110427

3139 123 6505

1C01 1 MSP-636H1-01-NI 2 3

CVI 1

B06C

VSYNC

HSYNC

SOG

3E04

100R

3E05

68R

10n

2E05

10n

68R

10n

2E04

1R0

3E02

2E02

3E03

68R

3E00

1n5

2E03

10n

VGA_Bp

VGA_Gn

VGA_Gp

VGA_Rp

DC_5V 60R

5E03

30R

5E05

30R

5E04

BAS316

6E05

1R0

3E10

VSYNC

150R

3E13

60R

5E02

60R

5E01

60R

5E00

H_SYNC

RES

2011-Apr-29

RES RES

2E00

2E07 2E08

EN 55

6E00 6E01 6E02

5p6 5p6 5p6

2E10

75R 75R 75R

3E16 3E15 3E14

1E00

PESD5V0S1BA

PESD5V0S1BA 1E05 1E02

PESD5V0S1BA

EDID_WC

2E12

1n0

FE02

VGA_G

VGA_B

FE05 FE06

FE04

FE03

FE01

DC_5V

VGA_R

0001 0001

VGA

5p6 5p6

2E13

68K FE07

FE13

FE16

1216-02D-15L-2EC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1E01

10K

3E25

FE14

4E03

4E02

7E01 BC847BW

IE00

DC_5V

3E21

B06D

RES 3E17

10K 330p

2E14

VGA

2K2 2K2

RES 3E18

10.

RES 3E19

3E23 SDA_VGA

SCL_VGA

10K 330p

2E09

RES RES

100n 6E03 6E04

3E22 2E15

L11M1.1L LA

RES 3E20

Circuit Diagrams and PWB Layouts

PESD5V0S1BA PESD5V0S1BA

2E11 1E03 1E04

1% 6K2

33R

RES 3E27

10K

3E26

FE09

FE08

FE10

6E06

FE11

BAS316

FE15

)

ADR

0 1 2

100n

6K2 1% 2E16

PCB SB SSB THRILLER BRZ DIG

EEPROM

(256 × 8)

FE12

SDA

SCL

7E00 M24C02-WMN6 8

4E04

RES 3E24

+5V_SW

1 2 3

DC_5V

2011-01-13

2011-01-31

19130_030_110427.eps 110427

3139 123 6505

B06D

B07

Hospitality

10-7 B07 393912365052

502382-0570

SDA_CLOCK SCL_CLOCK

FF04

RES 5F00 RES 3F00 RES 3F01 RES 5F01

FF00 FF01 FF02 FF03 33R

+5V_SW

SDA-LCD SCL-LCD

2011-Apr-29

4 502382-0370

1 2 3 5

DMMC3 1F01

+3V3STBY

EN 56

RES 33R 100R 100R

10.

1F00

1 2 3 4 5 7

L11M1.1L LA

RES

DMMC1

Circuit Diagrams and PWB Layouts

FF11

FF13

FF12

1n0

RES

2F01 2F00

1n0

RES

PBS_HPL PBS_HPR

PCB SB SSB THRILLER BRZ DIG

2011-01-13

2011-01-31

19130_031_110427.eps 110427

3139 123 6505

B07

1402

2134

2133

2132

2145

2147

2148

2137 3129

2180

2169 2199

2142

2143

2419

1M99

5115 2188

6C00

1202

2726 3795 3798 2728 5706

2725 3794

2724 3793 2727

2723 3792

3791 3790 2722

1X02

1403

2141 2144

2421 2420

1M95

1M20 1735

2146 2136

2189

2C00

1C14

2175

2C22

2C20

2C21

2149

2172

5105 2176

6C19

3C00

2C01

7124

2181

2C24

3C27

2151

1C16

2C23

2C25

5106

7125

3C29

2198

3C13

2C18

3C12

U23

2C19

2C03

3C01

1C15

2411

1C10

1C02

1C17

2B55 3B45

1C18

3C22

2401

2400

3B49

2402

2403

1C01

2412

3611

3605

3606

3600

2B57

3B52

2B56

2B50

2704 2703 3717 3716

3607 3609 3610

3614

7703

1C08

3713

1C19

5C02

3619

3718

3719

3715 3709

3617 3618

3612 3613

3796

7601

3608

3602

2609

7600

3615

3763 3762

2B19

1B05

3B16

7801

2B63

2B60

7B05

7700

4810 4811

4818 4812

2011-Apr-29

1F00

3760

4817 4820

4824

2C02

6C20

6C01

2416 2415 2422

3C28

2105

2405 5402

5403

5117 2154

2106

6C02

2129

3C02

4100

3C20

2130

2C17

2131 3128

3C21

2128 3127

3C14

2127 3126

2C05

2163 5C00

5401 5400 3C04

5123

5C01

2100

7400

7122 5C03

3B46

2126 2125

3C26

6C08 2C04

2551 2628 2C16

6C03

3C16 3C23

1C09 6C09

5121

5C04

5700

2135

3B48

2162

3C17

2191

3C24

2152

2C15

2138

3759 3F01

2183

5C05

3765 3780

5F01

4813 37A9

1702

3C18

2608 2101 2B52

4819

4814 4822 4816 4821

37A8

3784 2720 3785 2719

3B37

2729

3748

1706

6701

2290

5311

4306

2716

2285

2287 5227

2289 5230

2B43

2B17

2B25

3753

3754

1901

6914 6913

3788 3787

3737 3757 3735 3731 3758

5229 5226

2B16

2B24

2700

3707 3706

2701

2803

2171

5120 2168

5104

2161

2155

7216

1F01

2D14

2B36

3B32

6B00

3B33 2B39

1B04

6B01

2E10

5E03

1E02 1E05 1E00

2E11

3E13

5309

6E04

5E05

3E18

6E00

6E01

3E14

2E09

3C11

2C12

6C07

3C10

3C19

2C11

3C09

6C05

2C07

3C08

2C08

3C07

6C06

3E15

5E00

3E10

2E08

6A00

2A01

3A03

6A01

1B01

1E01

2109

7120 2159

2804

2805

1201

1G51

1705

6700

2288

1701

1X03

2E05 3E05

2104

2C06

2E02 3E02

3711 2702

7702 3B40

7B01 3B50 3C25

3712 3C05

2E00 3E00

4700 3726

2E04 3E04

4815 2B00 3B00

1X05

3C06

2B03

4823 37AA

2B01 3B01

2140 6C10 6C04

2B05

3B03

2B40

Overview top side

3B54

2B06

3B05

3B18 3B17

2291

EN 57

1E04

10-8 313912365052 SSB Layout

2B20

3F00

3B15

1B02 5F00

2B07 3B07

3B06

5506

2B08 3B08

2B41 2B11 3B11

2514 2B02 3B02

2B44

2717 2B09 3B09

1700 3749

2297 2295

2258

5207 2B35

5228

7123 6E05

2286

2153

2294 5208 2296

3B31

2B34

1B03

3A13

10.

2B62 3B56

5E02

1D05 1D04

7A00 3A14

6E02

2802 3B57

2B61 3B55

3A12

2A06 2A02

2A09 3B34

2B37 2B38

1E03

2C13 2C10 1C20 3A04

5E01 2E13

3A11

2164 2C14 2C09

L11M1.1L LA

2E07

Circuit Diagrams and PWB Layouts

3E17

6122 3E16

6E03

SSB Layout Top

1X01

6917

1902

1A01

1C03

1D01

1X04

1C05 1A03 1A02 6916 6915 2E12

1C07 1C06 5E04

2011-01-31

19130_040_110428.eps 110428

3139 123 6505

FA03

F907

3915

I905

FD00

1D03

FA02

FC03

FC02

F912

IB66

FE05

F909

IC04

IB67

FE01

FA09

FA08

FA04

FB08

IC05

IC07

I254

FD07

5D00

FD04

IA02

IA09

IA01

IA08

FE06

FE07

2901

F906

FF12

I916

FB00

F905

FB06

IB00

IB01

IB02

2A13

3A19

3A17

F417

FF11

IA03

IB09

IB03

3A09

2A04

IA10

7903

FB01

IA00

4A02

2A07

FF13

3A18

2F01

FD01

FD06

I119

I138

I122

FA07

IA04

2123 3150

FE02

3101 2177

I120

4209 4210

F236

3272

I800

4311

I125

I255

2282

2278

2277

FE03

I123

FE04

3271

F209

A212

A213

A214

F201

F202

F203

F204

F206

F207

I801

I126

I802

3803

3263

3262

F301

F300

5305

I306

I338

2111 F136

6800

3802

F235

F205

F829

I808

2311 2303 2309

3350

3270

I222

I221

A225

3806

I301

I316

I304

F247

F242

I809

I806

I302

5306 2318 2323 I300

5307 2320 2321 2322

4312

4313

4314

F815 F816

I303

2304 2305 5301

6301

FE13 4E02

4E03

FE14

3353 2308 3356 2310 5302

I320

U1 I308

F716

I716

3E25

FE16

I325

F302

F303

1301 I307

F701

F702

F814

F808

F807

I715

2306 3344 2301 3343

I733

I747

F718

F717

3E27

3337 3335 3336 3349

3745

3B14

F805

F806

F813

7302

2340 2339

4310

I305

I318

I317

F306

F800

7803

7802

F246

F834

F831

F809

F811

FE11

F213

IE00

3704

3705

3739

IB22

I714

F719

IB15

F500

I713

I754

IB45

IB63

3B35

FE12

IB43

IB47

37AB

I507

2561 3723

2517

IB14

F503

F828

F824

6900

2E16

F914

3E24

F915

I758

2599 2570

37A5

I759

F826

2597

2573

IB37

2902

3912

F744

F903

IB35

IB33

F818

2536

I502

F904

3E03

2E03

IB27

I749

IB23

IB25

IB26

2593 5504 2592

IB24

F737

3900

F901

F821

2538

2534

2535

2527

2537

2526

2525

F817 F822

2522 2515

3722 2574

2580

I505

F825

F832

2011-Apr-29

F913

F902

I700

F827

F823

2577

I760

I701

IB29

IB31

7E00

IB39

IB61

F741

F742

I506

IB16

5502

FE15 4E04

FE10

I711

IB20

6E06

3E26

3E23

FE08

3740

IB41

2B42

3B38

FE09

2B15

2B14

IB18

2706

F833

F801

I504

F721

I739

I744

I734

3756

3769 I725

6707

F411

4900

37A6

F900

IB74

3622 2552 2553

2504

I745

IB70

I746

4707

2508

3624 2545

2579

I750

I915

I757

2566

2567

5500

3623

2584

2503

2502 2501

4708

3901 3924 3902 2900

IB71

3768

6706

2711

FB09

F820

F819

F502

3789

I735

2505 I755

FF01

FF02

FB07

F751

F748

2544

FF03

I738

3603

IC22

IC14

7908

6902

F706

3604

2607

IC21

FC06

F745

2625

F601

3601

I143

7119

F760

2622 2621

3710

3714

3786

F759

2620

F736

F600

2606

3616

F740

I906

F761

F738

2507

6709

FF04

F724

2705

2500

2603 2605

2602

F746

2604

2601

3703 5501 F739

I761

F725

FB04

3767

7709

6708

FF00

I737

F766

I756

F749

2543

F750

2506

2509

F602

F763

IC18

3761

FC14

F705

CXXX

F707

2626

IB19 IB48

F704

I741

IC16

IC17

2B51

I708

F131

5125

2185

2186

7D00

FD05

2A12

I140

2166

I107

2107

3153 3154 3155

F132

2F00

3809

3122 3125 3105 3115

3805

F135

6D00

IC20

IC19

4307

3136

5222

2284

2D12

2283

FC01

7901

4902 3920

F911

3916

FC00

6901

F743

3A15

2A05

2280

5225

2281

2D11

3A10

2A10

FD02

7907

2193 FC13

IB49

IB51

I144

F501

2165

2139

3B42

IB52

2122

2157

4800 4806 5127 4801 4807 4802 4808 2279

2110

FD03

4903 3921

F908

3919

IB08

FA06

3904 3905

2A11

3903

3A16

4A03

2A08

3923

F208

2807 3807 3810

7800 5128 2226 2225 3230 3228

3808

5801 5802 5800 3264 3269

I807

4309

2806

5304 2262 2324 2263 2314 3261

2213 7218

7301

3741 3782 3700 3701 5503

F747

2550

4803 4804 4805 2338

2337 2336

2378 2377 3355

5303 3360 2313 3352 3351 2316 2312 2379 2380 2317 I220

7217 2293

2335

2623

IB50

IB53

F133

IC13

IB21

FC05

I412

3107 3146 3140

3135 I136

2160

I406

I118

2150

I106

I411

IC11

I441

I117

2170 3149

I105

2179 3100

I742 I731

I727

I726

3776 3777

I401

I431

IC03

3437

I445

F412

FC12

I443

I436

FC04

7413

7412

2432

2433 3439

3428

I432

F402

2424 3420

7407

F401

C400

I403

I405

2713

7708

I732

I743

I137

2158

I442

I437

4401 I430

I415

3419

7404

F400

I435

F415

3431

F414

F101

I414

3145 3109 3148 3117 3106

I429

6402

F409

F125

FC07

FC11

I416

I111

7402

IC10

2417

2418

3400

2413

I417

3409 3410 3408

I423

F413

IC02

I134

I109

I131

I127

2112

3414

I108

IB12

IB10

I418

F408

I425

F410

FC09

IB13

IC09

I434

I139

3131

I132

3452 3451

2102

6102

IC01

F115

F116

F117

F114

F113

F109

F108

F107

F106

F105

F754

F753

F406

F405

F404

F123

F122

F121

F118

F119

FC10

F758

F757

F756

FC08

FC15

F765

2427 3453 3454

F103

F102

SSB Layout Bottom

I433

I104

2187 3151

2178 3102

2195

2124 3152

3415

3416

I135

2192

6401

F416

I113

2414

3405

7403

I422

2167

2113

I142

I112

3113

3114

3118 3116 3112 I141

Overview bottom side

5310

3332 3331 5308 2341 3265

2334

3354 3357 3359 3358 2307 2302

2197 2627

F812

7E01

2624

EN 58

2B59

10.

3B41

F810

7705

3781 2333

IB17

5505

2581

3B39 I753

2518

2521 2516

3742 3743

3339 2332

3736

3E21 3E22

2529

3721 3720

4308 3E19 3E20

2596

3783 2575

2531

FB03 2E14

2595 6903

2569 2558 2576

2524 2565 2530

3732 5701 2730 2562 2563

3B36

5900

2E15

3B58

3908 3907

IB72

3B47

3724

7900 I902

2560 2528

2598 3500

2523 2564 3913

37A7

2533 3727

2512 3728

2532 3733 2709

2513 2630 3746

2600 2510 2549

2559 2541 3747 3764

3621

5705

L11M1.1L LA

3771

2540 2542 2568

3734 3751 3729 3702 3730

3744

7905

4904 3906

2571 2588 7710 2721

F708

2629 3620

3108

Circuit Diagrams and PWB Layouts

3B53

2519 2520 2582

2710 4901

3770

3738

7701 7902 3914

3427

5124 3B44 3B51

3B43

2B54 2B58

2B53

3138

2409

6403

2425 3421

7406 IC15

3779 3778 3775 3774

2406 2407

7411

3412

2712

2430 3430 2431 3434

2408 7414 3438

3432 3435

2423 3417 3433

6400

F104

2190 3130

3103 I110

3411 3413 FB02

3111 3418 I440

7405 3426 I413

2404

2426 7408

I424

3406

3422

F120 F755

2108

2011-01-31

19130_041_110428.eps 110428

3139 123 6505

T01A

LVDS Display

1X01 REF EMC HOLE

PX2EPX2E+

PX2DPX2D+

PX2CLKPX2CLK+

PX2CPX2C+

PX2BPX2B+

PX2APX2A+

PX1EPX1E+

PX1DPX1D+

PX1CLKPX1CLK+

PX1CPX1C+

PX1BPX1B+

PX1APX1A+

LVDS Display

1X02 REF EMC HOLE

10.

2011-Apr-29

EN 59

RES 2N03

FN25 FN26 FN27 FN28

FN23 FN24

FN31 FN17 FN18 FN19 FN20 FN21 FN22

+VDISP-INT

10n

FN13 FN14 FN15 FN16

FN11 FN12

FN05 FN06 FN07 FN08 FN09 FN10

SDA-TCON SCL-TCON BYPASS_MODE

2N01

10-9 T01 393912365071

L11M1.1L LA

FN29

100u 16V 2N02

Circuit Diagrams and PWB Layouts

100n

FN32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 54 56 58 60 53 55 57 59 61

FN33

FN01

FI-RE51S-HF

1N01

LVDS#1

PCB SB THRILLER BRZ TCON

2010-06-29

19130_032_110427.eps 110427

3139 123 6507

T01A

VCC_3V3

VCC1V8

60R

5H03

60R

5H02

60R

5H01

60R

5H00

2H43

2H44

VDD3V3IO

VSS

VDD18

7H01-1 VPP1501BFG

FH00

50Hz_60Hz

SCL-TCON SDA-TCON

RESET

FH02

FH03

FH04

3H26

P7 R7

FH01

3H25

VSS

RES 1R0 RES 1R0

VDD33IO

VDD33LVML

OSCOUT

C6 R6 R9 R12

C8 C11 C13 E15 J15 N15 R13

VSS

VDD18

VSS

VDD18

VDD18PLL

VSS

VDD18

C3 C4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E2 E4 E5 E8 E9 E12 E13 E14 F6 F7 F10 F11 G4 G6 G7 G10 G11 H5 H8 H9 H12 H13 J1 J2 J4 J5 J8 J9 J12 J13 J14 J16 K6 K7 K10 K11 L4 L6 L7 L10 L11 M5 M8 M9 M12 M13 N4 N5 N8 N9 N12 N13 N14 P5 P6 P8 P9 P10 P11 P12 P13 P14 U4

RTC50_60

ATTN

SCL SDA

0 1 2 3

TESTSE

TESTMOD

TESTAGN

MISC

OSC

SCL DB SDA

RST

OUT

4H04

4 3

3H02 B7 A7 B6 A6 B5 A5 B3 A3 B2 A2 B4 A4

PX2A+ PX2APX2B+ PX2BPX2C+ PX2CPX2D+ PX2DPX2E+ PX2E-

B13 A13 B12 A12 B11 A11 B9 A9 B8 A8

PX2CLK+ PX2CLK-

CLKP RXE CLKN

RXO

CLKP CLKN

B10 A10

VCC_3V3

GSP2 GSP1

GOE

GCK

REV

RDIO1 RDIO2

LDIO1 LDIO2

SELLVDS

FH35

ASIC_CS11

ASIC_CS9

ASIC_CS7

ASIC_CS5

ASIC_CS3

ASIC_CS1

100R

3H23

RES

T17

T10 U10

U16 U17

T16

T12 U12

U11

T11

U13

T13

H15 H14

U15 U14

J17

M16 M17 N16 N17 P16 P17 R14 R15 R16 R17 T14 T15

7H01-3 VPP1501BFG

U_D_INV

2011-Apr-29

1K0

3H06

2K4

3H05

VCC_3V3 7H02-1 74LVC2G04 1

7H02-2 74LVC2G04 3

2K2

RES 3H22

33R

3H21

R_L U_D

0P 0N 1P 1N 2P RXO 2N 3P 3N 4P 4N

GCK

U_D

RESET

GSP2

GSP1

0P 0N 1P 1N 2P RXE 2N 3P 3N 4P 4N

ROM_SCL ROM_SDA SCL-TCON SDA-TCON

100n 2H10

LVDS

100n 2H09 1R0 1R0

100n

GSLOP

7H01-2 VPP1501BFG

RES 3H27 RES 3H28

FH06

OSCIN

100n 2H13

U5 T5 U6 T6

R10

T8 U8

560R

100n 2H08

OSCOUT

EN 60

LCD

SELLVOS

L|R_ U|D_

GP01 GP02

SLOPE

STVU STVD

CPV

POL

B1 STH B2

F1 STH F2

RESPI

1 2 3 4 5 6 CS 7 8 9 10 11 12

7H03 74LVC1G74DC 7 S 1 C1 2 1D 6 R Q

VCC_3V3

CKP CKN

PX1A+ PX1APX1B+ PX1BPX1C+ PX1CPX1D+ PX1DPX1E+ PX1E-

CKP CKN

PX1CLK+ PX1CLK-

LLV

0P 0N 1P 1N 2P 2N 3P 3N LLV 4P 4N 5P 5N 6P 6N 7P 7N

RLV

0P 0N 1P 1N 2P 2N 3P 3N RLV 4P 4N 5P 5N 6P 6N 7P 7N

7H04 74LVC1G74DC 7 S 1 C1 2 1D 6 R

2H25

LLV6+ LLV6LLV5+ LLV5LLV4+ LLV4LLV3+ LLV3LLV2+ LLV2LLV1+ LLV1LLV0+ LLV0LLV7+ LLV7LCK+ LCK-

RLV6+ RLV6RLV5+ RLV5RLV4+ RLV4RLV3+ RLV3RLV2+ RLV2RLV1+ RLV1RLV0+ RLV0RLV7+ RLV7RCK+ RCK-

M14 M15

A14 A15 A16 A17 B14 B15 B16 B17 C14 C15 C16 C17 D16 D17 E16 E17 F14 F15

1u0

2H54

100n 2H26

F16 F17 G14 G15 G16 G17 H16 H17 K14 K15 K16 K17 L14 L15 L16 L17

100n

7H05 74LVC1G86GW 2

100n 2H27

FH37 2H28 4

FH38

VDD3V3IO

100n

4H05 REV

FH39

VDD1V8PLL

2H30

VDD3V3LVRS

100n 2H29

FH36

10.

100n 2H31

VDD1V8

100n 2H06

3H01

100n 2H05 10p FH05

RESET

27M

1H00 DSX321G 2 NC 1

VGH_35V

2H01

3H03

3H04

10p

POWER

OSCIN

VDD3V3LVRS

C7 C10 C12 G3

C5 C9 D15 E3 E6 E7 E10 E11 F5 F8 F9 F12 F13 G5 G8 G9 G12 G13 H6 H7 H10 H11 J3 J6 J7 J10 J11 K5 K8 K9 K12 K13 L3 L5 L8 L9 L12 L13 M6 M7 M10 M11 N3 N6 N7 N10 N11 P15 R5 R8 R11

100n 2H02

2H40

150K

16K

2H41

100n 2H07 1M0

7H01-5 VPP1501BFG VDD1V8

VDD1V8PLL

10u

2H45

2H46

100n 2H34

100n 2H33

60R

5H05

VCC1V8

60R

5H04

1K0

3H00

DDR2VDD

LDQS

UDQS

M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 J8 K8 F7 E8 B7 A8

TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 TA10 TA11 TA12 TCK TCK# TLDQS TLDQS# TUDQS TUDQS#

0 1 2 3 4 5 6 A 7 8 9 10 11 12

0 BA 1

L2 L3 TBA0 TBA1

ODT CKE WE CS RAS CAS

7H00 H5PS5162FFR-S6C

TBA0 TBA1

TODT

TCKE

TCK TCK#

TCS# TRAS# TCAS# TWE#

K9 K2 K3 L8 K7 L7

2H32 TODT TCKE TWE# TCS# TRAS# TCAS#

VCC1V8

100n 2H35 TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 TA10 TA11 TA12

FH40

DDR2VDD

100n 2H36

TCON Control

100R

3H07

100R

3H08

100R

3H09

2H52

T01B

3H10

100R

100n

TCON Control

2H42

5 2

100n 2H03

100R

3H11

5 2

5 3

100n 2H04 100n 100R 3H12

100R 3H13

100R 3H14

100R 3H15

100R 3H16

100R 3H17

100R 3H18

100n 2H37 100n RES 2H53 10u

100n 2H38 2H50 VSS

VDD

100n

P1 P2

L2 L1

N2 M3 N1 M2

P4 R2 P3 T1 R4 T2 R3 U1 T4 U2 R1 T3 U3

DRAM

60R

5H06

DDR2VDD

RESIMP

0 BA 1

ODT

CKE

CS RAS CAS WE

0 1 2 3 4 5 6 A 7 8 9 10 11 12

VCC1V8

7H01-4 VPP1501BFG

A1 E1 J9 M9 R1 A3 E3 J3 N1 P9

10u

100n 2H39 J1

) SDRAM

VDDL VSSDL J7

2H51

UDQS

VSSQ

VDDQ

VREF

UDM LDM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C2 C1

PCB SB THRILLER BRZ TCON

B3 F3

G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9

A2 E2 L1 R3 R7 R8

G2 G1

H3 H2 K3 K2 K1 K4 H1 H4 D3 D2 F3 F2 F1 F4 D1 D4

LDQS

0 1 2 3 4 5 6 DQ 7 8 9 10 11 12 13 14 15

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

L11M1.1L LA

FH34

TDQ0 TDQ1 TDQ2 TDQ3 TDQ4 TDQ5 TDQ6 TDQ7 TDQ8 TDQ9 TDQ10 TDQ11 TDQ12 TDQ13 TDQ14 TDQ15

TUDQS TUDQS#

TLDQS TLDQS#

TDQ0 TDQ1 TDQ2 TDQ3 TDQ4 TDQ5 TDQ6 TDQ7 TDQ8 TDQ9 TDQ10 TDQ11 TDQ12 TDQ13 TDQ14 TDQ15

100R

3H20

DDR2VDD

2010-06-29

19130_033_110427.eps 110427

T01B

3139 123 6507

100n 3H19

Circuit Diagrams and PWB Layouts

100R RES 2H47

100n 2H48

100n

GSLOP

220n

4u7

4n7

2J20

2J21

FJ60

2J19

2J44

6J02 RB550EA 1 2 3

SGND1

4n7

SGND1

100n

2J17

2J18

10K 1%

3J07

10u

3J08 2K2 RES

SGND1

RES 2J51

GSLOP

FJ04

FJ56

2u2

2J15

RES 2J47

SGND1

47u RES 2J52

2J49

VLS_15V6

24 25

17 18

15 16

26 36

CM2

CTL CDEL

P C2 N

P C1 N

EN PROT

HVS

COMP

7J00-1 ISL97653AIRZ

RES 3J13

SUPP

2J14

VCC_3V3

VLS_15V6_B

cK00

SGND1

42 43 44 45

7J00-2 ISL97653AIRZ

2u2

PGND

)

VIA

VIA VIA

RSET

VREF FBN NOUT

DRN COM

POUT FBP

SGND1

RES

53 52 51 50

4J05

TEMP

LDO-CTL LDO-FB 31

40 39

2 3 4 8

10 11 13

23 22

21 20

34 35 29

2J00 1 2 FBB

4u7

2J13 LX

2u2 2J01

CB 1 LXL 2 FBL

PVIN

10u 2J02 SGND1

10n SGND1

7J03 KTB1124-C 3 1

2J03 FJ06

SGND1

VCC_3V3

SGND1

2u2

SGND1

0.5%

10K 13K

RES 2J16 100n

2K2

RES 3J06

3J11 3J12

10K

3J01

RES

6u8

FJ05

FJ58

SS34

6J06

RES

2J32

10u 2J05

VCC1V8

SGND1

FJ02

SGND1

2011-Apr-29

220n

2J34

39K

220n

820p

10u

RES 2J33

3J10

FJ00

FJ03

SGND1

39K 3K3

5J06

FJ07

4J01-1 4J01-2 4J01-3 4J01-4

8 7 6 5

2K2

RES 3J09

FJ59

RES 7J02 FDS9435A 8 3 7 2 6 5 1 10n

VLS_15V6_B

RES 2J11 RES 2J12

47u 25V

2u2

SUPN

2K2 2J22

AGND

38 1 GND_HS 41

FJ57

2J23

3J03 3J04

1n0 1n0

7J01 FDS9435A 8 7 3 6 2 5 1

2u2

39K 2K2

RES 3J05 VGL_-6V

RES 3J02 RES 3J19

1 2 3 4

4J02-1 4J02-2 4J02-3 4J02-4

47u 25V 2J07 1

8 7 6 5

10u 2J09

RES 7J05 2N7002

FJ09

RES 7J04 2SB1767 2 3

1 2 3 4

VLS_15V6

RES 3J21

+VDISP

RES 2J24

8 7 6 5

100K 100n

4J00-1 4J00-2 4J00-3 4J00-4

1u0

2J35

FJ11

FJ01

6J05

1 2 3 4

2u2 SS24 10K

3J22

RES RES RES RES

4u5

5J00

VLS_15V6

FJ10

20K SGND1

VGH_35V

SGND1

12K

+VDISP

3J24 3J25

47u

4J03

+VDISP

100n 3J00 24K 0.5% 3J14

32 33 5 6 14

57 56 55 54

46 47 48 49

2J25

3J15 3J16

RES 2J36

2K2 3J17 3J18

27K 750K

22u 16V

2K2 2K2

1n0 2J38 1n0

RES 2J37

TCON DC/DC

240K

1u0

VCC_3V3

2J40 3J26

FJ14

6J01 RB550EA 1 2 3

100n

VGL_-6V

+VDISP-INT

30R

1 2 3 4

8 7 6 5

2K2

3J28

6J07

+VDISP

2010-06-29

19130_034_110427.eps 110427

T01C

3139 123 6507

LTST-C190KGKT

FJ55 FOR DEBUG ONLY

PCB SB THRILLER BRZ TCON

4J04-1 4J04-2 4J04-3 4J04-4

3.0A 32V

RES 1J01 30R RES 5J08

3.0A 32V

RES 5J07

RES 1J00

DISPLAY INTERFACING - VDISP

FJ13

2u2

T01C

RES 2J28 2J29

2J26 2J27

2J41

EN 61

RES 2J42

2J04 120p 120p

3J27

TCON DC/DC

100n 100p

RES 2J06 RES 3J20 2J30

2K2 4u7 RES 2J31

16V 22u

10.

22u

RES 2J08 2K2

2K2 RES 3J29

10u RES 2J10 PMEG1030EJ 3K6

RES 6J00 RES 3J23

2K2 RES 2J50

L11M1.1L LA

10u

Circuit Diagrams and PWB Layouts

2J43

22u RES 2J39

3K00

2K01

1u0

FK02

2K00

1u0

3K3 5%

3K06

34 35 36 37 38 39 40 41

13 12

7K00 ISL24837IRZ-T13

VCC_3V3

VLS_15V6

AVDD

100n

32" 5K1 JUMPER JUMPER JUMPER JUMPER

VLS_15V6

FK07

VIA

GND

BANKSEL

V_THERM

SET_COMP

SCL SDA

SET

REFIN

REFIN_INN

40" 10K JUMPER JUMPER JUMPER JUMPER -

100n

INNCOM

OUTCOM

OUT12

OUT11

OUT10

OUT9

INN8

OUT8

INN7

OUT7

INN6

OUT6

INN5

OUT5

OUT4

OUT3

OUT2

OUT1

GND_HS

INPCOM|DVR_OUT

VSD

FK03

+VDISP

7K01 PBSS4540X

VCOM BUFFER

2K02

VCC_3V3

FK04 FK05

FK06

ITEM NO. 3K45 3K51 4K01 4K02 4K03 4K04 4K09 4K13 4K16 4K18

VCOM

SCL-TCON SDA-TCON

FK01

3K01

100K 0.5%

6K2 0.5%

10K 0.5%

3K02

VLS_15V6

RES 3K08

7K02 PBSS5330X

FK08

FK57

560R 5%

3K16

FK56

3K05

VLS_15V6

2K2

10u OUTCOM

INNCOM

OUTCOM

10.

EN 62

3K34

2011-Apr-29

FK22 FK23 FK24

RES 4K20 RES 4K21 4K05

FK52

FK51

FK19 FK20

CS_L

VL191

VL31 VL159 VL127

VL127 VL63 VL247 VL95

VL127 VL95 VL31 VL63

VL0

FK47

FK18

VH127 VH95 VH31 VH63 VH0

VH127 VH63 VH247 VH95

VH127 VH31 VH159

FK14 FK15 FK16 FK46

FK44

FK42

FK11

VH191

FK40

RES 4K17 RES 4K18 4K04 RES 4K19

RES 4K14 RES 4K15 RES 4K16 4K03

RES 4K11 RES 4K12 RES 4K13 4K02

RES 4K08 RES 4K09 4K01 RES 4K10

4K00 RES 4K22 RES 4K07

VH255

FK10

VCC_3V3

1n0

FK35

1 2 3

FK36 0 1 2

10 11

RES 1KQA

RES 1KQB

502382-0470

1 2 3 4

502382-0970

1 2 3 4 5 6 7 8 9

NC NC NC

VCC

FK53

ADR

WC SCL

FK33

SDA

) (8K × 8) EEPROM

7K04 M24C64-WDW6

100n

2K28

VCC_3V3

SSB-TCON EEPROM

6K8

3K40

DEBUG ONLY

6K8 3K41

VREF_15V2

22K 5%

18K 5%

3K03

3K04

10K

3K10

100n

FK00

2K19

68p

2K03

2K21

3K14

3K15

6 20

10u

100n

2K04

8 7 6 5

4K06-1 4K06-2 4K06-3 4K06-4

1 2 3 4

5R6 0.5%

2K2 5%

cK01

2K18

3K17

2K05

RES 3K07

5K1 0.5%

6 10R 3K11-3

7 10R 3K11-2

5 3K11-4 4 2K06 5 3K12-4 4 2K10 5 3K13-4 4 2K14

10R 100n

8 10R 3K11-1 1 100n 2K09

RES 3K60 3K61

P Gamma & Vcom & NVM

2K20

3K62

3 100n 2K07 6 10R 3K12-3 3 100n 2K11 6 10R 3K13-3 3 100n 2K15

MSS1P4

2 100n 2K08 7 10R 3K12-2 2 100n 2K12 7 10R 3K13-2 2 100n 2K16

6K00 8

8 10R 3K12-1

RES 3K44 3K49

T01D

22u 16V

100R

1 100n 2K13 8

10K 10K RES 2K30 4

10R 100n 10R 100n

10R 3K13-1 1 100n 2K17

10K 1 0K RES 2K24

FK55

FK54

FK37

2K2

VCC

3K56

3K55

SDA-TCON SCL-TCON

WP_TCON RESET

ROM_SDA

ROM_SCL

WP_TCON

2010-06-29

19130_035_110427.eps 110427

SELLVDS R_L U_D

50Hz_60Hz

3139 123 6507

BYPASS_MODE

2K0

FK38 FK27 FK28 FK29

SDA-TCON SCL-TCON

T01D ASIC OPTIONS

PCB SB THRILLER BRZ TCON

RES 3K35

P Gamma & Vcom & NVM

L11M1.1L LA

3K52 10K 10K

1n0

Circuit Diagrams and PWB Layouts

6K8

RES 3K45 1n0 3K51

RES 3K36

RES 3K46 1n0 3K50 6K8 3K54

5K1 0.5% 10K RES 2K25 3K53

10K 10K RES 2K26

2K2

VCOM

RES

4L02-1

RES

4L02-2

RES

4L02-3

RES

4L02-4

RES

4L01-1

RES

4L01-2

RES

4L01-3

RES

4L01-4

RES

4L00-1

4L00-2 RES

4L00-3 RES

4L00-4 RES

MPD

FL11

FL10

FL09

FL08

FL07

FL06

FL05

FL04

FL03

FL02

FL01

FL00

10R

10.

2011-Apr-29

CS12

CS11

CS10

CS9

CS8

CS7

CS6

CS5

CS4

CS3

CS2

CS1

EN 63

CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 CS12

GND_HS

OUTB

OUTA

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

FL15

VIA

+ + INB INA

REFH REFL

1 2 3 IN 4 5 6 7

FL14

+VDISP

7L02 2SC5886A 3

GND

AVDD

34 35 36 37 38 39 40 41 42

13 14 15 16

10 11

32 31 30 29 27 26 25

ITEM NO. 3L12 3L13 3L14

32" 47K 2K2 56K

FL16

33R 0.5%

3L16

40" 68K 2K 82K

7L00 ISL24016IRTZ

FOR 32" / 40"

NC NC

1 2 3 4 5 6 7 8 19 20 21 22 23 24

2L14 12

3L17 100n 2L15

1R0 22u 16V

T01E

L11M1.1L LA

2L12

VREF_15V2

FL13

FL12

PCB SB THRILLER BRZ TCON

CS_L

ASIC_CS1 ASIC_CS3 ASIC_CS5 ASIC_CS7 ASIC_CS9 ASIC_CS11

7L01 NJM2125F 4

33R 0.5%

3L15

+VDISP

5 2

3L14 3L13 3L12

82K 0.5% 2L16 10K 0.5% 62K

MPD

3L00-1

2L00

10R 3L00-2

100n 2L01

3 3L00-3 6

10R

100n 2L02

10R 3L00-4

100n 2L03

10R

100n

3L01-1

2L04

10R 3L01-2

100n 2L05

6 3L01-3 3

10R 100n 2L06

5 10R 3L01-4 4 100n 2L07

10R 100n

8 3L02-1 1 2L08

2 3L02-2 7

10R 100n 2L09

6 10R 3L02-3 3 100n 2L10

4 3L02-4 5

100n 2L11

10R 100n

Circuit Diagrams and PWB Layouts

2L13

2010-06-29

19130_036_110427.eps 110427

T01E

3139 123 6507

100n

1n0

T01F

VL0 VL31 VL63 VL95 VL127 VL159 VL191 VL247

RLV2+ RLV2RLV1+ RLV1RLV0+ RLV0-

RCK+ RCK-

RLV5+ RLV5RLV4+ RLV4RLV3+ RLV3-

GSP2 GSP1 REV LS

RDIO2 R_L RDIO1

RLV7+ RLV7RLV6+ RLV6-

GSP2 GSP1 GCK GOE U_D_INV CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 CS12 VCOM VH255 VH247 VH191 VH159 VH127 VH95 VH63 VH31 VH0

3M16

RES 3M15

Mini LVDS

68R

1 2 3 4 4 1 2 3

VGL_-6V VGH_35V

VLS_15V6

VCC_3V3

8 7 6 5 5 8 7 6

68R 68R 68R 68R

4M00-1 4M00-2 4M00-3 4M00-4 4M04-4 4M04-1 4M04-2 4M04-3

4M11

RES RES RES RES

3M02 3M07 3M09 3M10

FM49 FM50 FM51 FM52 FM53 FM54

FM47 FM48

FM41 FM42 FM43 FM44 FM45 FM46

FM40

FM38

FM34 FM35 FM36

FM30 FM31 FM32 FM33

FM00

FM65

FM01 FM02 FM03 FM04 FM05 FM06 FM97

20R

Mini LVDS

L11M1.1L LA

FM68

EN 64

2011-Apr-29

81 82 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RES 36 2M02 35 34 100n 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 501559-8093

1KA2

10.

8 7 6 5

RES 1 4M13-1 RES 2 4M13-2 RES 3 4M13-3 RES 4 4M13-4

LDIO2 R_L LDIO1 LLV6+ LLV6LLV7+ LLV7-

VL0 VL31 VL63 VL95 VL127 VL159 VL191 VL247

7 6 5

68R 8

3M14

2 4M08-2 3 4M08-3 4 4M08-4

68R 68R 68R 68R

1 4M08-1

RES 3M13

68R

3M00 3M01 3M03 3M08

GSP2 GSP1 REV LS

LLV2+ LLV2LLV1+ LLV1LLV0+ LLV0-

LCK+ LCK-

GSP2 GSP1 GCK GOE U_D CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 CS12 VCOM VH255 VH247 VH191 VH159 VH127 VH95 VH63 VH31 VH0 LLV5+ LLV5LLV4+ LLV4LLV3+ LLV3-

VLS_15V6

VCC_3V3

VGL_-6V VGH_35V

FM95 FM96

FM93 FM94

FM90 FM91 FM92

FM89

FM87

FM81 FM82 FM83 FM84 FM85 FM86

FM79 FM80

FM73 FM74 FM75 FM76 FM77 FM78

FM69 FM70 FM71 FM72

1KA1 82

FM67

501559-8093

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

FM98 81

100n

RES 2M01

PCB SB THRILLER BRZ TCON

20R

Circuit Diagrams and PWB Layouts

3M17 RES 2M03

10u

3M18 10u

RES 2M04

2010-06-29

19130_037_110427.eps 110427

3139 123 6507

T01F

7J05

7J04

2K02

3K06

3K04

3K03

2K00

cK01

6J01

3J26 3J10

2J40

3K13

2K17

2K16

3K11

2J34 2J17 2J18

2J28

3J18

2J38

2J39

2K13

2K12

2K10

CK00

2J01

2J44

3J04 3J03 2J15

2J03

7J01

7J03

2J13

3J14

3J12

3J11

6J05

2K11

2J12 2J11 3J07

2J35 2J00

7J00

2J32

3K10

3K08

4M00 4M04

5J00

4K08

2K05

2K03

7K00

2J31 2J14

2J30

6J02

3J29

3J27

2J50

3J21

4K06

3K17

3J22

1X01

2K20

2K09

2K15

3K12

4K17

4K19

4K18

4K04

5J06

4K21

4K05

3H05

4L02

2J07 2J09

3J05 3J02

2J06

7J02

2J10

2J08

3H13

3H14

3H15

3H18

3H16

3H17

3H10

3H07

3H09

3H08

3H02

1N01

3H12

3H11

7H01

2H40

1H00

4M08 4M13

7H03

7H05

3K50

7H04

3K56

3J28

6J07 3K35

3K41

3K40

1J01 1J00 2J43

5J07

5J08

3K54

3K55

3H21

3M13

3M14

1X02

2J47

2011-Apr-29

2N01 2J49

4H05

2M03

FM98

FK04

FK33

FK05

FK53

FK55

FK54

FK29

FM67

FK37

FK36

FK35

FN29

FK38

FM92

FM91

FH34

FM97

FM94

2H48

2H47

FM89

FM90

FM87

FM84

2H51

2H33

FH40

FM82

FM81

FJ05

2H32

FM83

FH35

2H34

FM86

FM77

FM78

FM79

FM80

FN33

5H04

FM85

2H52

1KA1 2K26 3K61

3K46 3K60

2H54

3K15 3K14

2K18

3K16

3K05

2K19

3J16 3J15

4J02

3K01

3K00

3K02

2J27 2J26

3J23 6J00

2K07

2K01

7K01

2K08

2J52

2J33

2J22

2K21

3J19 3J09

3J13 4J03

2K06

3K07

2K04

3J25 2J36

2J16

4K13

3H23

7K04

7K02

3J08

4K12

3K34

4L01

4L00

3H22

2K30 3K53

6K00 2K28 3K62

4J04

7H02 3K52 3K36

2K14

2J51

3J20

4K01

2J20 2J37 3J24

4K09

4K07

4K02

4K22

FN31

FN01

2H35

2H39

FK46

FM76

FM75

2H50

FM93

3H19

FM96

2H36

FN28

FN27

FM74

FM73

FN26

FN25

FN22

3H00

FN24

FK10

FK15 FK16

FN21

FN20

FN23

FK14

FN17

FN18

FN19

FL09

FH00

FK42

FK11

FN16

FN15

FN14

FN13

FH38

FN12

FN11

2H09

2H29

2H13

2H07

FN08

FH39

FN07

FN10

FN09

FH36

FH04 2H28

2H04

FN06

FN05

FL10

2H30

2H01

2H25

2H03

2H27

3H06

FH37

FN32

FJ01

FL08

FH03

3K49

2K24

FH01

4H04

FJ59

FL01

3H04

FL02

3M01

FH06

3H27

FL03

FM01

FL12

FL11

FL15

FK00

3L13

3M18

FL05

FK23

FK20

FK47

FM50

FM52

FK22

FK52

FM49

FM51

3L16

3L15

FM48

FM47

FM46

FM45

FM44

FM43

FK28

4M11

FM42

FM41

FM40

3M16

FJ02

FJ56

TCON THRILLER

FJ57

FJ13

FM02

FM31

FM33

FM38

FM30

FM32

FJ55

3M15

7L02

FL16

2L07 2L06 2L05 2L04 2L03 2L02 2L01 2L00

FK18

4K15

7L01

FJ58

FM54

FM53

2M04

FK19

2L15

FL13

4K14

FL04

FM65

FK51

FL07

FL14

FM00

FL06

FK08

7L00

FK27

FM72

FM70

FH02

3H03

3K44

3M03

3M00

2H42

FM71

FM69

FL00

3H25

FM95

3H20

1KQA 1KQB

4K10

4K00

2J21

2J19

2J41

3J17 2J29

4J05 2J02 3J01 3J00

2H37 2H38

5H05

2M02

2J25

2J23

6J06

2J05 2J04

2J24

4J00

5H03

3H28

1KA2

4J01

2H53 5H06

2M01

7H00 2J42

2H10

2H43

2H06

5H01

2H02 2H08

2H44

3M08

Overview top/bottom side

2N03

4K11

3J06

2H46

3K51

10-10 313912365071 TCON Layout

2H45

2L12

EN 65

5H02

4K20

10.

FK06

FM34

FJ11

FM35

FK40

FJ03

FK07

FK44

FJ04

FJ10

FM36

FK03

FM68

FJ06

FJ60

FK57

3M02

FM04

FM06

FJ07

FJ00

FJ09

2011-04-28

19130_042_110428.eps 110428

3139 123 6506

FK01

FK02

FK56

FM03

FM05

3M07

L11M1.1L LA

2H26

2H05 2H31

5H00

2K25

3M09 3M10

3H01

2H41

Circuit Diagrams and PWB Layouts

2N02

3K45

3H26

2L09 3L02

FH05

2L08 2L10 2L11

2L13 3L12 2L16 3L14

FK24

3L01

4K16

3L17

3L00

4K03

2L14

FJ14

3M17

THRILLER 32"

Styling Sheet Thriller 32"

11. Styling Sheets

Styling Sheets

0004

0024

0021

1150

L11M1.1L LA

11.

2011-Apr-29

1004

5213

EN 66

1112

1114

0154

1005

Pos No. 0004 0012 0021 0024 0154 0260 1004 1005 1112 1114 1150 5213 8191 8G51 1085

Description Front Cabinet Back Cover Side IO Bracket Bottom IO Bracket Speaker Bracket Stand Display panel Power Supply Unit IR/LED Keyboard + Board SSB Loudspeaker box Mainscord 1.8m Cable LVDS FFC Remote Control

Not Displayed Not Displayed Not Displayed

0260

19130_039_110428.eps 110428

Remarks

0012

THRILLER 40"

Styling Sheet Thriller 40"

1150

0004

L11M1.1L LA

0024

0021

Styling Sheets

1157

11.

2011-Apr-29

1004

5213

EN 67

1112

1114

0154

1005

Pos No. 0004 0012 0021 0024 0154 0260 1004 1005 1112 1114 1150 1157 5213 8191 8G50 8KA1 8KA2 1085

Front Cabinet Back Cover Side IO Bracket Bottom IO Bracket Speaker Bracket Stand Display panel Power Supply Unit IR/LED Keyboard + Board SSB TCON module Loudspeaker box Mainscord 1.8m Cable LVDS FFC Cable LVDS FFC Cable LVDS FFC Remote Control

Description

0260

0012

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