Internal Use Only North/Latin America Europe/Africa Asia/Oceania
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LCD TV SERVICE MANUAL CHASSIS : LJ91D
MODEL : 42LH70YD
42LH70YD-SE
CAUTION BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL61862401 (0905-REV01)
Printed in Korea
CONTENTS
CONTENTS .............................................................................................. 2 PRODUCT SAFETY ..................................................................................3 SPECIFICATION ........................................................................................6 ADJUSTMENT INSTRUCTION ...............................................................14 TROUBLE SHOOTING ............................................................................17 BLOCK DIAGRAM...................................................................................58 EXPLODED VIEW .................................................................................. 59 SVC. SHEET ...............................................................................................
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
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LGE Internal Use Only
SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.
Leakage Current Hot Check (See below Figure) Plug the AC cord directly into the AC outlet.
General Guidance An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks. It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1W), keep the resistor 10mm away from PCB.
Do not use a line Isolation Transformer during this check. Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to 0.5mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.
Leakage Current Hot Check circuit Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. To Instrument’s exposed METALLIC PARTS
Leakage Current Cold Check(Antenna Cold Check) With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1MΩ and 5.2MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
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Good Earth Ground such as WATER PIPE, CONDUIT etc. 0.15uF
1.5 Kohm/10W
When 25A is impressed between Earth and 2nd Ground for 1 second, Resistance must be less than 0.1 Ω *Base on Adjustment standard
LGE Internal Use Only
SERVICING PRECAUTIONS CAUTION: Before servicing receivers covered by this service manual and its supplements and addenda, read and follow the SAFETY PRECAUTIONS on page 3 of this publication. NOTE: If unforeseen circumstances create conflict between the following servicing precautions and any of the safety precautions on page 3 of this publication, always follow the safety precautions. Remember: Safety First. General Servicing Precautions 1. Always unplug the receiver AC power cord from the AC power source before; a. Removing or reinstalling any component, circuit board module or any other receiver assembly. b. Disconnecting or reconnecting any receiver electrical plug or other electrical connection. c. Connecting a test substitute in parallel with an electrolytic capacitor in the receiver. CAUTION: A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion hazard. 2. Test high voltage only by measuring it with an appropriate high voltage meter or other voltage measuring device (DVM, FETVOM, etc) equipped with a suitable high voltage probe. Do not test high voltage by "drawing an arc". 3. Do not spray chemicals on or near this receiver or any of its assemblies. 4. Unless specified otherwise in this service manual, clean electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable non-abrasive applicator; 10% (by volume) Acetone and 90% (by volume) isopropyl alcohol (90%-99% strength) CAUTION: This is a flammable mixture. Unless specified otherwise in this service manual, lubrication of contacts in not required. 5. Do not defeat any plug/socket B+ voltage interlocks with which receivers covered by this service manual might be equipped. 6. Do not apply AC power to this instrument and/or any of its electrical assemblies unless all solid-state device heat sinks are correctly installed. 7. Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last. 8. Use with this receiver only the test fixtures specified in this service manual. CAUTION: Do not connect the test fixture ground strap to any heat sink in this receiver. Electrostatically Sensitive (ES) Devices Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES devices are integrated circuits and some field-effect transistors and semiconductor "chip" components. The following techniques should be used to help reduce the incidence of component damage caused by static by static electricity. 1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
unit under test. 2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly. 3. Use only a grounded-tip soldering iron to solder or unsolder ES devices. 4. Use only an anti-static type solder removal device. Some solder removal devices not classified as "anti-static" can generate electrical charges sufficient to damage ES devices. 5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES devices. 6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material). 7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will be installed. CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions. 8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can generate static electricity sufficient to damage an ES device.) General Soldering Guidelines 1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within the range or 500°F to 600°F. 2. Use an appropriate gauge of RMA resin-core solder composed of 60 parts tin/40 parts lead. 3. Keep the soldering iron tip clean and well tinned. 4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25cm) brush with a metal handle. Do not use freon-propelled spray-on cleaners. 5. Use the following unsoldering technique a. Allow the soldering iron tip to reach normal temperature. (500°F to 600°F) b. Heat the component lead until the solder melts. c. Quickly draw the melted solder with an anti-static, suctiontype solder removal device or with solder braid. CAUTION: Work quickly to avoid overheating the circuit board printed foil. 6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature (500°F to 600°F) b. First, hold the soldering iron tip and solder the strand against the component lead until the solder melts. c. Quickly move the soldering iron tip to the junction of the component lead and the printed circuit foil, and hold it there only until the solder flows onto and around both the component lead and the foil. CAUTION: Work quickly to avoid overheating the circuit board printed foil. d. Closely inspect the solder area and remove any excess or splashed solder with a small wire-bristle brush.
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LGE Internal Use Only
IC Remove/Replacement Some chassis circuit boards have slotted holes (oblong) through which the IC leads are inserted and then bent flat against the circuit foil. When holes are the slotted type, the following technique should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique as outlined in paragraphs 5 and 6 above. Removal 1. Desolder and straighten each IC lead in one operation by gently prying up on the lead with the soldering iron tip as the solder melts. 2. Draw away the melted solder with an anti-static suction-type solder removal device (or with solder braid) before removing the IC. Replacement 1. Carefully insert the replacement IC in the circuit board. 2. Carefully bend each IC lead against the circuit foil pad and solder it. 3. Clean the soldered areas with a small wire-bristle brush. (It is not necessary to reapply acrylic coating to the areas). "Small-Signal" Discrete Transistor Removal/Replacement 1. Remove the defective transistor by clipping its leads as close as possible to the component body. 2. Bend into a "U" shape the end of each of three leads remaining on the circuit board. 3. Bend into a "U" shape the replacement transistor leads. 4. Connect the replacement transistor leads to the corresponding leads extending from the circuit board and crimp the "U" with long nose pliers to insure metal to metal contact then solder each connection. Power Output, Transistor Device Removal/Replacement 1. Heat and remove all solder from around the transistor leads. 2. Remove the heat sink mounting screw (if so equipped). 3. Carefully remove the transistor from the heat sink of the circuit board. 4. Insert new transistor in the circuit board. 5. Solder each transistor lead, and clip off excess lead. 6. Replace heat sink.
Circuit Board Foil Repair Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil to separate from or "lift-off" the board. The following guidelines and procedures should be followed whenever this condition is encountered. At IC Connections To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board. (Use this technique only on IC connections). 1. Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary). 2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern. 3. Bend a small "U" in one end of a small gauge jumper wire and carefully crimp it around the IC pin. Solder the IC connection. 4. Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire. At Other Connections Use the following technique to repair the defective copper pattern at connections other than IC Pins. This technique involves the installation of a jumper wire on the component side of the circuit board. 1. Remove the defective copper pattern with a sharp knife. Remove at least 1/4 inch of copper, to ensure that a hazardous condition will not exist if the jumper wire opens. 2. Trace along the copper pattern from both sides of the pattern break and locate the nearest component that is directly connected to the affected copper pattern. 3. Connect insulated 20-gauge jumper wire from the lead of the nearest component on one side of the pattern break to the lead of the nearest component on the other side. Carefully crimp and solder the connections. CAUTION: Be sure the insulated jumper wire is dressed so the it does not touch components or sharp edges.
Diode Removal/Replacement 1. Remove defective diode by clipping its leads as close as possible to diode body. 2. Bend the two remaining leads perpendicular y to the circuit board. 3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board. 4. Securely crimp each connection and solder it. 5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder. Fuse and Conventional Resistor Removal/Replacement 1. Clip each fuse or resistor lead at top of the circuit board hollow stake. 2. Securely crimp the leads of replacement component around notch at stake top. 3. Solder the connections. CAUTION: Maintain original spacing between the replaced component and adjacent components and the circuit board to prevent excessive component temperatures. Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
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LGE Internal Use Only
SPECIFICATION NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
3. Test method
This specification is applied to the LCD TV used LJ91D chassis.
2. Requirement for Test
1) Performance: LGE TV test method followed 2) Demanded other specification - Safety: CE, IEC specification - EMC: CE, IEC specification
Each part is tested as below without special appointment. 1) Temperature : 25±5ºC (77±9ºF), CST : 40±5ºC 2) Relative Humidity : 65±10% 3) Power Voltage : Standard input voltage(100~240V@50/60Hz) * Standard Voltage of each products is marked by models. 4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. 5) The receiver must be operated for about 5 minutes prior to the adjustment.
4. Electrical specification 4.1 General Specification No 1. 2.
Item Receiving System Available Channel
3. 4. 5.
Input Voltage Market Screen Size
6. 7. 8.
Aspect Ratio Tuning System Module
9.
Operating Environment
10.
Storage Environment
Specification 1) SBTVD / NTSC / PAL-M / PAL-N 1) VHF : 02~13 2) UHF : 14~69 3) DTV : 02-69 4) CATV : 01~135 1) AC 100 ~ 240V 50/60Hz Central and South AMERICA 32 inch Wide(1920x1080) 42 inch Wide(1920x1080) 47 inch Wide(1920x1080)
Remark
Mark : 110V, 60Hz 32LH70YD-SH 42LH70YD-SE 47LH70YD-SE
16:9 FS LC320WUD-SBA1(Vitaz 4) LC420WUD-SBT1(Vitaz 4) LC470WUD-SAT1(Vitaz 4) 1) Temp : 0 ~ 40 deg 2) Humidity : ~ 80 % 1) Temp : -20 ~ 60 deg 2) Humidity : ~ 85 %
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
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32LH70YD-SH 42LH70YD-SE 47LH70YD-SE
LGE Internal Use Only
5. Chromiance & Luminance spec. 42LH70YD-SE No 1.
2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
12.
Item Max Luminance (Center 1-point / Full White Pattern) Luminance uniformity Color RED coordinate GREEN
Module Set
BLUE WHITE
Cool Standard Warm
13. 14. 15. 16.
Typ 500
400
500
77 Typ. -0.03
X Y X Y X Y X Y
Color coordinate uniformity Contrast ratio
Color Temperature
Min 400
Color Distortion, DG Color Distortion, DP Color S/N, AM/FM Color Killer Sensitivity
Max
Unit cd/m cd/m %
Full white
Typ. +0.03
0.637 0.335 0.290 0.606 0.145 0.062 0.279 0.292
1000:1 70000:1
1400:1 100000:1
0.274 0.281 0.283 0.291 0.311 0.327
0.276 0.283 0.285 0.293 0.313 0.329
N/A NORMAL DCR
0.278 0.285 0.287 0.295 0.315 0.331 10.0 10.0
43.0 -80
Remark
<Test Condition> 85% Full white pattern ** The W/B Tolerance is â&#x20AC;&#x201C;0.015 for Adjustment Dynamic contrast : off Dynamic color : off OPC : off % deg dB dBm
6. Component Input (Y, CB/PB, CR/PR) No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
Resolution 720*480 720*480 720*480 720*480 1280*720 1280*720 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080
H-freq(kHz) 15.73 15.73 31.47 31.47 45.00 44.96 33.75 33.72 67.500 67.432 27.000 26.97 33.75 33.71 56.25 28.125
V-freq.(kHz) 60 59.94 60 59.94 60.00 59.94 60.00 59.94 60 59.939 24.000 23.94 30.000 29.97 50.000 25.000
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Pixel clock 13.5135 13.5 27.027 27.0 74.25 74.176 74.25 74.176 148.50 148.352 74.25 74.176 74.25 74.176 148.5 74.25
Proposed SDTV ,DVD 480I SDTV ,DVD 480I SDTV 480P SDTV 480P HDTV 720P HDTV 720P HDTV 1080I HDTV 1080I HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P
LGE Internal Use Only
7. RGB Input (PC) No
Resolution PC 1. 640*350 2. 720*400 3. 640*480 4. 800*600 5. 800*600 6. 1024*768 7. 1280*768 8. 1360*768 9. 1280*1024 10. 1600*1200 11 1920*1080
H-freq(kHz) 31.468 31.469 31.469 35.156 37.879 48.363 47.776 47.712 63.981 75.00 67.5
V-freq.(Hz) 70.09 70.08 59.94 56.25 60.31 60.00 59.870 60.015 60.020 60.00 60
Pixel clock(MHz) 25.17 28.32 25.17 36.00 40.00 65.00 79.5 85.50 108.00 162 148.5
Proposed EGA DOS VESA(VGA) VESA(SVGA) VESA(SVGA) VESA(XGA) CVT(WXGA) VESA (WXGA) VESA VESA (UXGA) HDTV 1080P
DDC X O O O O O O O O O O
** RGB PC Monitor Range Limits - Min Vertical Freq - 56 Hz - Max Vertical Freq - 62 Hz - Min Horiz. Freq - 30 kHz - Max Horiz. Freq - 80 kHz - Pixel Clock - 170 MHz
8. HDMI Input (PC/DTV) No 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 12 17. 18.
Resolution PC 640*350 720*400 640*480 800*600 800*600 1024*768 1280*768 1360*768 1280*1024 1600*1200 1920*1080 DTV 720*480 720*480 1280*720 1280*720 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080 1920*1080
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
31.468 31.469 31.469 35.156 37.879 48.363 47.776 47.712 63.981 75.00 66.587
70.09 70.08 59.94 56.25 60.31 60.00 59.870 60.015 60.020 60.00 59.934
25.17 28.32 25.17 36.00 40.00 65.00 79.5 85.50 108.00 162 138.5
EGA DOS VESA(VGA) VESA(SVGA) VESA(SVGA) VESA(XGA) CVT(WXGA) VESA (WXGA) VESA (SXGA) VESA (UXGA) HDTV 1080P
31.47 31.47 45.00 44.96 33.75 33.72 67.500 67.432 27.000 26.97 33.75 33.71 56.25 28.125
60 59.94 60.00 59.94 60.00 59.94 60 59.939 24.000 23.94 30.000 29.97 50.000 25.000
27.027 27.00 74.25 74.176 74.25 74.176 148.50 148.352 74.25 74.176 74.25 74.176 148.5 74.25
SDTV 480P SDTV 480P HDTV 720P HDTV 720P HDTV 1080I HDTV 1080I HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P HDTV 1080P
DDC X O O O O O O O O O O
** HDMI Monitor Range Limits - Min Vertical Freq - 56 Hz - Max Vertical Freq - 62 Hz - Min Horiz. Freq - 30 kHz - Max Horiz. Freq - 80 kHz - Pixel Clock - 170 MHz Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
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LGE Internal Use Only
9. Consignment Setting (OUTGOING CONDITION) No 1. 2. 3. 4. 5. 6 7.
8.
9.
10.
11.
Item Input Mode Volume Level Mute Aspect Ratio System Color Booster Picture Picture Mode Backlight Contrast Brightness Sharpness Color Tint Color Temperature Picture Reset Audio Sound Mode Auto Volume Clear Voice SRS TruSurround XT Balance TV Speaker Time Clock Off Timer / On Timer Sleep Timer / Auto Sleep Option Language (Menu/Audio) SimpLink Key Lock Caption Set ID Channel Memory
Condition TV02CH 10 Off 16:9 PAL-M On Vivid 100 100 50 70 70 0 Cool Standard Off Off Off 0 On Auto Off Portugues On Off Off 1 RF : 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 30, 51, 63 CATV : 15, 16, 17
10. Mechanical Specification 42LH70YD-SE No. 1.
Item Product Dim ension
Width (W)
Con tent Length (D)
1009.7
334.4
1009.7
39.7
753.6 695.4
1330
228
1120
228 19.8
W/O Packing With Packing
2.
Product Weight
W/O Packing With Packing
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
-9-
Unit mm
Remark
mm
With Stand
770
mm mm
W/O Stand With Stand
770
mm
W/O Stand
Kg
With Stand
17.2
Kg
W/O Stand
24.0
Kg
With Stand
21.0
Kg
W/O Stand
Height (H)
LGE Internal Use Only
ADJUSTMENT INSTRUCTION 1. Application Range
4. PCB Assembly Adjustment
This specification sheet is applied all of the LJ91D, LJ92J LCD TV models, which produced in manufacture department or similar LG TV factory.
4.1. CPLD DOWNLOAD : JTAG MODE
2. Notice 1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument. 2) Adjustment must be done in the correct order. But it is flexible when its factory local problem occurs. . 3) The adjustment must be performed in the circumstance of 25 ±5°C of temperature and 65±10% of relative humidity if there is no specific designation. 4) The input voltage of the receiver must keep 100~220V, 50/60Hz. 5) Before adjustment, execute Heat-Run for 5 minutes.
4.2. << PRINT PORT >> PIN MAP
• After Receive 100% Full white pattern (06CH) then process Heat-run (or “8. Test pattern” condition of Ez-Adjust status) • How to make set white pattern 1) Press Power ON button of Service Remocon 2) Press ADJ button of Service remocon. Select “8. Test pattern” and, after select “White” using navigation button, and then you can see 100% Full White pattern.
Pin
JTAG Mode Signal Name
2
TCK
3
TMS
8
TDI
11
TDO
13
-
15
VCC
18 TO 25
GND
* In this status you can maintain Heat-Run useless any pattern generator * Notice: if you maintain one picture over 20 minutes (Especially sharp distinction black with white pattern – 13Ch, or Cross hatch pattern – 09Ch) then it can appear image stick near black level.
3. Adjustment Items 3.1 PCB Assembly adjustment • CPLD DOWNLOAD • Adjust 480i Comp1 • Adjust 1080p Comp1/RGB - If it is necessary, it can adjustment at Manufacture Line - You can see set adjustment status at “1. ADJUST CHECK” of the “In-start menu”
3.2 Set Assembly Adjustment • EDID (The Extended Display Identification Data ) / DDC (Display Data Channel) download • Color Temperature (White Balance) Adjustment • Make sure RS-232C control • Selection Factory output option
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
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LGE Internal Use Only
4.3. << 10P WAFER >> PIN MAP
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
- 11 -
LGE Internal Use Only
4.4. Using RS-232C Adjust 3 items at 3.1 PCB assembly adjustments “4.1.3 sequence” one after the order. O Adjustment protocol Order
Command
Set response
1. Inter the
ad 00 00
d 00 OK00x
kb 00 40
b 00 OK40x (Adjust 480i Comp1/1080p Comp1)
kb 00 60
b 00 OK60x (Adjust 1080p RGB)
Adjustment mode 2. Change the Source
3.Start Adjustment ad 00 10 4.Return the
OKx ( Success condition )
Response 5.Read Adjustment data
6.Confirm
NGx ( Failed condition ) (main)
(main : component1 480i, RGB 1080p)
ad 00 20
000000000000000000000000007c007b006dx
(main)
(main : component1 1080p)
ad 00 30
000000070000000000000000007c00830077x
ad 00 99
Adjustment
NG 03 00x (Failed condition) NG 03 01x (Failed condition) NG 03 02x (Failed condition) OK 03 03x (Success condition)
7. End of Adjustment ad 00 90
d 00 OK90x
See ADC Adjustment RS232C Protocol_Ver1.0 O Adjustment protocol - Pattern Generator : (MSPG-925FA) - Adjust 480i Comp1 (MSPG-925FA : model :209 , pattern : 65) - Adjust 1080p Comp1/RGB(MSPG-925FA:model : 225 , pattern : 65) - Adjust RGB (MSPG-925FA:model :225 , Pattern :65) – RGB-PC Mode * If you want more information then see the below Adjustment method (Factory Adjustment) O Adjustment sequence - ad 00 00 : Enter the ADC Adjustment mode. - xb 00 40: Change the mode to Component1 (No actions) - ad 00 10: Adjust 480i Comp - ad 00 10: Adjust 1080p Comp - xb 00 60: Change to RGB-PC mode(No action) - ad 00 10: Adjust 1080p RGB - ad 00 90: End of the adjustment
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
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LGE Internal Use Only
5. Factory Adjustment 5.1 Manual Adjust Component 480i/1080p RGB 1080p O Summary : Adjustment component 480i/1080i and RGB 1080p is Gain and Black levelsetting at Analog to Digital converter, and compensate the RGB deviation O Using instrument - Adjustment remocon, 801GF(802B, 802F, 802R) or MSPG925FA pattern generator (It can output 480i/1080i horizontal 100% color bar pattern signal, and its output level must setting 0.7V±0.1V p-p correctly)
5.2 EDID (The Extended Display Identification Data) / DDC (Display Data Channel) Download. <Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern >
O Summary • It is established in VESA, for communication between PC and Monitor without order from user for building user condition. It helps to make easily use realize “Plug and Play” function. • For EDID data write, we use DDC2B protocol.
* You must make it sure its resolution and pattern cause every instrument can have different setting O Adjustment method 480i Comp1, Adjust 1080p Comp1/RGB (Factory adjustment) • ADC 480i Component1 adjustment - Check connection of Component1 - MSPG-925FA Ë Model: 209, Pattern 65 • Set Component 480i mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to “NORMAL” • ADC 1080p Component1 / RGB adjustment - Check connection both of Component1 and RGB - MSPG-925FA Model: 225, Pattern 65 • Set Component 1080p mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to “NORMAL” • After get each the signal, wait more a second and enter the “IN-START” with press IN-START key of Service remocon. After then select “7. External ADC” with navigator button and press “Enter”. • After Then Press key of Service remocon “Right Arrow(VOL+)” • You can see “ADC Component1 Success” • Component1 1080p, RGB 1080p Adjust is same method. • Component 1080p Adjustment in Component1 input mode • RGB 1080p adjustment in RGB input mode • If you success RGB 1080p Adjust. You can see “ADC RGB-DTV Success”
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
O Auto Download • After enter Service Mode by pushing “ADJ” key, • Enter EDID D/L mode. • Enter “START” by pushing “OK” key. Caution: - Never connect HDMI & D-sub Cable when the user downloading . - Use the proper cables below for EDID Writing.
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LGE Internal Use Only
- HDM2 EDID table (0x33, 0x1C)
Edid data and Model option download (RS232) NO Enter download MODE
Item Download ModeIn
CMD 1
CMD 2
Data 0
A
E
0
0
Edid data and Model option download
Download
A
E
*Note1
*Note2
Adjust Mode Out
A
E
9
0
Adjustment Confirmation
A
E
9
9
When transfer the ’Mode In’ , Carry the command. Automaticall y download (The use of a internal Data) To check Download on Assembly line.
O Manual Download • Write HDMI EDID data - Using instruments => Jig. (PC Serial to D-Sub connection) for PC, DDC adjustment. => S/W for DDC recording (EDID data write and read) => D-sub jack => Additional HDMI cable connection Jig. - Preparing and setting. => Set instruments and Jig. Like pic.5), then turn on PC and Jig. => Operate DDC write S/W (EDID write & read) => It will operate in the DOS mode.
- HDMI-3 EDID table (0x33, 0x0C)
Download jig
Main
PC
B/D RGB cable
Pic.3) For write EDID data, setting Jig and another instruments. • EDID data for LJ91D Chassis (Model name = LG TV) - HDMI-1 EDID table (0x33, 0x2C)
- Analog (RGB) EDID table (0x9B, 0x25)
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
- 14 -
LGE Internal Use Only
5.3 Adjustment Color Temperature(White balance) O Using Instruments • Color Analyzer: CA-210 (CH 9) - Using LCD color temperature, Color Analyzer (CA-210) must use CH 9, which Matrix compensated (White, Red, Green, Blue compensation) with CS-2100. See the Coordination bellowed one. • Auto-adjustment Equipment (It needs when Autoadjustment – It is availed communicate with RS-232C : Baud rate: 115200) • Video Signal Generator MSPG-925F 720p, 216Gray (Model: 217, Pattern 78)
O White Balance Adjustment If you can’t adjust with inner pattern, then you can adjust it using HDMI pattern. You can select option at "Ez-Adjust Menu – 7. White Balance" there items "NONE, INNER, HDMI". It is normally setting at inner basically. If you can’t adjust using inner pattern you can select HDMI item, and you can adjust. In manual Adjust case, if you press ADJ button of service remocon, and enter "Ez-Adjust Menu – 7. White Balance", then automatically inner pattern operates. (In case of "Inner" originally "Inner" will be selected. • Connect all cables and equipments like Pic.5) • Set Baud Rate of RS-232C to 115200. It may set 115200 orignally. • Connect RS-232C cable to set • Connect HDMI cable to set
O Connection Diagram (Auto Adjustment) • Using Inner Pattern
F u l l W h i t e P at t er n
C A -100+ COL OR A NA L Y ZER T Y PE ; C A -100+
R S-232C
• Using HDMI input
¢ RS-232C Command (Commonly apply) 00 00
00 10
wb wb
00 00
1f 20
wb wb
00 00
2f ff
White Balance adjustment start. Start of adjust gain (Inner white pattern) End of gain adjust Start of offset adjust(Inner white pattern) End of offset adjust End of White Balance adjust(Inner pattern disappeared)
• "wb 00 00": Start Auto-adjustment of white balance. • "wb 00 10": Start Gain Adjustment (Inner pattern) • "jb 00 c0" : •… • "wb 00 1f": End of Adjustment * If it needs, offset adjustment (wb 00 20-start, wb 00 2f-end) • "wb 00 ff": End of white balance adjustment (inner pattern disappear)
<Pic.5 Connection Diagram for Adjustment White balance> .
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
wb wb
- 15 -
LGE Internal Use Only
O White Balance Adjustment (Manual adjustment) • Test Equipment: CA-210 - Using LCD color temperature, Color Analyzer (CA210) must use CH 9, which Matrix compensated (White, Red, Green, Blue compensation) with CS2100. See the Coordination bellowed one. • Manual adjustment sequence is like bellowed one. - Turn to "Ez-Adjust" mode with press ADJ button of service remocon. - Select "10.Test Pattern" with CH+/- button and press enter. Then set will go on Heat-run mode. Over 30 minutes set let on Heat-run mode. - Let CA-210 to zero calibration and must has gap more 10cm from center of LCD module when adjustment. - Press "ADJ" button of service remocon and select "7.White-Balance" in "Ez-Adjust" then press "▶" button of navigation key. (When press "▶" button then set will go to full white mode) - Adjust at three mode (Cool, Medium, Warm) - If "cool" mode Let B-Gain to 192 and R, G, B-Cut to 64 and then control R, G gain adjustment High Light adjustment. - If "Medium" and "Warm" mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - All of the three mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - With volume button (+/-) you can adjust. - After all adjustment finished, with Enter (■ key) turn to Ez-Adjust mode. Then with ADJ button, exit from adjustment mode Attachment: White Balance adjustment coordination and color temperature. O Using CS-1000 Equipment. - COOL : T=11000K, △uv=0.000, x=0.276 y=0.283
5.5 Test of RS-232C control Press IN-Start button of service remocon then set the “4.Baud rate” to 15200, Then check RS-232C control and
5.6 Selection of Country option. Selection of country option is allowed only North American model (Not allowed Korean model). It is selection of Country about Rating and Time Zone. • Models: All models which use LA75A Chassis (See the first page.) • Press “In-Start” button of Service Remocon, then enter the “Option” Menu with “PIP CH-“ Button • Select one of these three (USA, CANADA, MEXICO) defends on its market using “Vol. +/-“button. * Caution : Don’t push The Instop Key ater completing the function inspection.
6. GND and ESD Testing 6.1 Prepare GND and ESD Testing. • Check the connection between set and power cord
- MEDIUM : T=9300K, △uv=0.000, x=0.285 y=0.293
6.2 Operate GND and ESD auto-test.
- WARM : T=6500K, △uv=0.000, x=0.313 y=0.329
• Fully connected (Between set and power cord) set enter the Auto-test sequence. • Connect D-Jack AV jack test equipment. • Turn on Auto-controller(GWS103-4) • Start Auto GND test. • If its result is NG, then notice with buzzer. • If its result is OK, then automatically it turns to ESD Test. • Operate ESD test • If its result is NG, then notice with buzzer. • If its result is OK, then process next steps. Notice it with Good lamp and STOPER Down.
5.4 EYE-Q Function check. 1) Turn on TV 2) Press EYE Key of Adj R/C 3) Cover the Eye Q II sensor on the front of the using your hand and wait for 6 seconds 4) Confirm that R/G/B va;ie os ;pwer tjam 10 of the ‘Raw Data (Sensor data, Back light)”. If after 6 seconds, R/G/B value is not lower than 10, re[;ace EYE Q II sensor. 5) Remove your hand from the EYE Q II sensor and wait for 6 sencond 6) Confirm that “OK” pop up. If change is not seen, replace EYE Q II sensor
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
6.3 Check Items.
- 16 -
• Test Voltage - GND: 1.5KV/min at 100mA - Signal: 3KV/min at 100mA • Test time: just 1 second. • Test point - GND test: Test between Power cord GND and Signal cable metal GND. - ESD test: Test between Power cord GND and Live and neutral. • Leakage current: Set to 0.5mA(rms) LGE Internal Use Only
Block Diagram Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
I2C I2C & & RS232 RS232 Communication Communication
22 ohm
22 ohm 22 ohm
SCL0 SDA0
+3.3V_HDMI
2.7k ohm
4.7k ohm
D3.3V
4.7k ohm
4.7k ohm
VA1G5BF8005
P 7 0 1
22 ohm
47PF
Main B/D
D3.3V
2.7k ohm
Sub B/D
4.7k ohm
Block Diagram
SCL1
22 ohm
0 ohm
SDA1
22 ohm
0 ohm
HDMI S/W
47PF
100 ohm
NTP3100L
100 ohm
33PF 33PF
MAX3232
4.7k ohm
22 ohm
22 ohm
SDA3
22 ohm
22 ohm
MICOM
100 ohm 100 ohm D3.3V
4.7k ohm
RS232C_TxD
P 7 0 2
SCL3
SCL2 SDA2
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
22 ohm 22 ohm
4.7k ohm
RS232C_RxD
BCM3556
4.7k ohm
4.7k ohm
+5V_ST
4.7k ohm
D3.3V
100 ohm
MST7323
100 ohm
LGE Internal Use Only
Block Diagram
• I2C channel [LH70] CH0 (+3.3V)
CH0 TUNER TUNER 11 0xC2 0xC2 Demod(0x30) Demod(0x30) QPSK(0x32) QPSK(0x32)
CH1
CH1 (+ 3.3V) AMP AMP NTP3100L NTP3100L 0x54 0x54
HDMI HDMI SW SW TDA9996 TDA9996
BCM3556 BCM3556
CH2 (+3.3V)
CH2 EEPROM EEPROM AT24C512 AT24C512 0xA6 0xA6
Micom Micom MTV416 MTV416 0x50 0x50
CH3 (+3.3V)
CH3 FRC FRC MST7323 MST7323
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
Block Diagram
D1.2V, D2.5V, +3.3V, +5.0V_ST SPDIF , EDID_WP …. SCL0_3.3V, SDA0_3.3V, DDC_SCL, DDC_SDA
Jack Board
MAIN Board
CVBS, SIF, AV, RGB ,COMPONENT, R/L,
TU_SCLK, TU_DATA, TU_SYNK’’..
< Signal Interface >
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
1. Power-Up Boot Fail Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
1. Power-Up Boot Fail Trouble Shooting Check P801 All Voltage Level (24V, 12V, 5V_ST)
N
Y Check Power connector
Replace Power board
Y Check All Voltage Level at L805/L807/L808
N
Replace one of L805/L807/L808 & Recheck
N
Replace one of IC809/Q812/L828/L829/L830/L822 & Recheck
N
N
Replace one of IC803/L824/L827 & Recheck
N
Y Check Voltage Level 3.3V at L830 Y Check Voltage Level 2.5V at L827
Check Micom IC406 Redownload or replace
Y Check Voltage Level 1.8V at IC802 #2 pin or L815
N
Replace one of IC802/IC805/L815 & Recheck
N
N
Replace one of IC804/Q809/L811/L817/L821 & Recheck
N
Y Check Voltage Level 1.2V at L821 Y Check X903 Clock 54MHz
N
Replace X903
Y Check signal transition at IC101 #9 pin
N
Maybe BCM3556 has troubles
Y Replace IC101 Flash Memory
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
2. No OSD Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
2. No OSD Trouble Shooting Check 12V Voltage Level at P801 #13 Pin
N
Y Check Power connector
Replace Power board
Y Check 12V Voltage Level at L801
N
Replace one of L801/Q804 & Recheck
N
Replace one of Q802/Q803/Q804/L801 & Recheck
N
Replace one of IC803/L824/L827 & Recheck
N
Replace one of IC802/IC805/L815 & Recheck
N
Replace IC807 & Recheck
N
Maybe BCM3556(IC100) or 7329A(IC901) has troubles
Y Check 12V Voltage Level at L909 Y Check Voltage Level 2.5V at L827 Y Check Voltage Level 1.8V at IC802 #2 pin or L815 Y Check Voltage Level 1.26V at IC807 #6 pin Y Check P903 #16(TXAC-), #17(TXAC+), #32(TXBC-), #33(TXBC+) Y Check LVDS Cable
N
Replace Cable
Y Check Voltage LCD Module
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
3. Digital TV Video Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
3. Digital TV Video Trouble Shooting
Check RF Cable Y Check Tuner(TU101) Power (5.0V, 2.5V, 3.3V, 1.2V)
N
Replace one of IC101, IC102 at Jack Board or IC803/ IQ812/ C804/ Q809/+5V_ST and +12V of P801 at Main Board& Recheck
Y Check TP Clock, Data, Sync R107, R108, R109
N
Maybe Tuner(TU101) has problems
Y Check cable between P203 at Jack Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y Maybe BCM3556(IC100) has problems
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
4. Analog TV Video Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
4. Analog TV Video Trouble Shooting
Check RF Cable Y Check Tuner(TU101) Power (5.0V, 2.5V, 3.3V, 1.2V)
N
Replace one of IC101, IC102 at Jack Board or IC803/ Q812/ IC804/ IC809/Q809/+5V_ST and +12V of P801 at Main Board& Recheck
Y Check CVBS Signal TU101 #7 Pin and R118
N
Maybe Tuner(TU101) has problems
Y Check cable between P203 at Jack Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y Check CVBS Signal R703 and C110 at Main Baord
N
Replace one of R703 and C110 & Recheck
Y Maybe BCM3556(IC100) has problems
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
5. Component Video Trouble Shooting Overall Block Diagram for Brazil DTV (LH70) ) (
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
5. Component Video Trouble Shooting Check Signal Format Is it supported signal? Y Check Component Cable Y Check Component Jack JK209 at Jack Board
N
Replace Jack at Jack board
Y Check Component Signal R292, R293, R294 R295, R296, R297 at Jack Board
N
Replace one of R292, R293, R294, R295, R296, R297 L212, L213, L214, L215, L216, L217 & Recheck
Y Check cable between P203 at Jack Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y Check Component Signal C130, C131, C132 C133, C134. C135
N
Replace it
Y Maybe BCM3556(IC100) has problems
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
6. RGB Video Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
6. RGB Video Trouble Shooting Check Signal Format Is it supported signal? Y Check RGB Cable Y Check RGB Jack JK208 at Jack Board
N
Replace JK208 at Jack board
Y Check RGB Signal L207, L208, L209 at Jack Board
N
Replace one of L207, L208, L209 at Jack Board & Recheck
Y Check cable between P203 at Jack Board and P701 at Main Board
N
Maybe Cable Pin has problems
Y Check RGB Signal C127, C128, C129 at Main Board
N
Replace it
Y Maybe BCM3556(IC100) has problems
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
7. AV Video Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
7. AV Video Trouble Shooting Check Signal Format Is it supported signal? Y Check AV Cable Y Check AV Jack JK209 at Jack Board
N
Replace JK209 at Jack board
Y Check AV Signal R203, R204, R214, R215 at Jack Board
N
Replace one of R203, R204, R214, R215 at Jack Board & Recheck
Y Check cable between P203 at Jack Board and P701 at Main Board
N
Maybe Cable Pin has problems
Y Check AV Signal C124, C125 at Main Board
N
Replace it
Y Maybe BCM3556(IC100) has problems
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
8. HDMI Video Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
8. HDMI Video Trouble Shooting Check Signal Format Is it supported signal? Y Check HDMI Cable Y Check HDMI Jack JK600, JK601, JK602
N
Replace Jack
Y Check IC601 Voltage Level +1.8V_HDMI, +5.0V_HDMI
N
Replace one of L601/L602/R619/R615
Y Check I2C Signal R624/R625/R157/R158
N
Replace It & Recheck
Y Maybe BCM3556(IC100) has problems
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
9. All Source Audio Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
9. All Source Audio Trouble Shooting
Make sure you can’t hear any audio Y Check Speaker
N
Replace Speaker
Y Check Connector P501
N
Replace Connector
Y Check Signal L504, L505
N
Replace one of L508/L509/L510/L507/L504/L505 & Recheck
N
N
Replace one of L511L503/L501 and IC503 & Recheck
N
Y Check IC501 Power 24V, 3.3V, 1.8V L511, L503, L501
Maybe NTP3100 has problems. Replace It
Y Check BCM3556 I2S Output R505, R506, R507
N
N Replace It & Recheck
Y Maybe BCM3556(IC100) has problems
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
N
LGE Internal Use Only
10. Digital TV Audio Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
10. Digital TV Audio Trouble Shooting
Check video output
N
Follow procedure digital TV video trouble shooting
N
Maybe BCM3556 internal audio DSP has problems. Replace It
Y Follow procedure All source audio trouble shooting
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
11. Analog TV Audio Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
11. Analog TV Audio Trouble Shooting
Check video output
N
Y Check Tuner(TU101) Power (5.0V, 2.5V, 3.3V, 1.2V)
N
Follow procedure analog TV video trouble shooting Replace one of IC101, IC102 at Jack Board or IC803/ Q812/ IC804/ IC809/Q809/+5V_ST and +12V of P801 at Main Board& Recheck
Y Check SIF Signal TU101 #6 Pin and R118 at Jack Board
N
Maybe Tuner(TU101) has problems
Y Check SIF Signal IC501 #4 Pin
N
Replace one of L505/L514/C502/C511/Q500/Q502 IC501 & Recheck
N
Replace one of C123, R120, R121, R124, L109, Q101, C128 & Recheck
Y Check SIF Signal C128 at Jack Board Y Check cable between P203 at Jack Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y Check SIF Signal R704 and C106 at Main Board
N
Replace one of R704/R128/C106 & Recheck
N
Maybe BCM3556 audio block has problems. Replace It
Y Follow procedure All source audio trouble shooting
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
12. Component / RGB / AV Audio Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS
(FHD, 120Hz)
FRC Block
CVBS, L/R, AV_DET SIDE_CVBS, SIDE_L/R, SIDE_DET
X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
FRC IC (MST7323S)
RF_Switch, Gain_Switch
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
12. Component / RGB / AV Audio Trouble Shooting
Check Video Output
N
Follow procedure external input video trouble shooting
Y Check Jack JK208/JK209
N
Replace Jack
Y Check Signal R235, R236 (Comp1) R216, R217 (Comp2) R249, R250 (RGB) R219, R221 (AV1) R218, R220 (AV2) at Jack Board
N
Replace one of R235/R236/C231/C232 (Comp1) R216/R217/C207/C208 (Comp2) R219/R221/C210/C212 (AV1) R218/R220/C209/C211 (AV2) R249/R250/C246/C247 (RGB) & Recheck at Jack Board
Y Check cable between P203 at Jack Board and P701 at Main Baord
N
Y Check Signal C206, C210, C211, C232, C220, C221, C224, C225, C226, C227 at Main Board
N
Maybe Cable Pin has problems
Replace one of R215/R228/C211/C232 (Comp1) R229/R230/C220/C221 (Comp2) R204/R214/C206/C210 (AV1) R231/R232/C224/C225 (AV2) R233/R234/C226/C227 (RGB) & Recheck at Main Board
Y Follow procedure All source audio trouble shooting
N
Maybe BCM3556 audio block has problems. Replace It
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
13. HDMI Audio Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
13. HDMI Audio Trouble Shooting N Check video output
Follow procedure HDMI video trouble shooting
Y Re-download EDID data
N
Replace IC601
Y Follow procedure All source audio trouble shooting
N
Maybe BCM3556 audio block has problems. Replace it
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
14. USB Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
14. USB Trouble Shooting
Check USB 2.0 Cable Y Check USB device If devuce is 2.5 inch HDD, Check power adaptor Y Check P704
N
Replace Jack
Y Check 5V voltage level at L703
N
Replace one of IC701/L703/IC806/Q810/L819 & Recheck
Y Maybe BCM3556(IC100) has problems. Replace It.
• Exception - USB power could be disabled by inrushing current - In this case, remove the device and try to reboot the TV (AC power off/on)
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
14. Bluetooth Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
14. USB Trouble Shooting
Check Bluetooth Module
N
Replace Bluetooth
Y Check Cable between Bluetooth and Main Board
N
Replace cable
Y Check P705
N
Replace Jack
Y Check Signal R3022, R3023
N
Replace one of R3022, R3023 & Recheck
Y Maybe BCM3556(IC100) has problems. Replace It.
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
15. Digital TV Recording Fail Trouble Shooting Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
15. Digital TV Recording Fail Trouble Shooting N Check video/audio output
Follow procedure digital TV video/audio trouble shooting
Y Check USB
N
Follow procedure USB trouble shooting
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
18. Digital TV Video Trouble Shooting while recording (Watch & Record) Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
18. Digital TV Video Trouble Shooting while recording (Watch & Record)
Check RF Cable Y N Check video/audio output
Follow procedure digital TV video/audio trouble shooting
Y Check USB
N
Follow procedure USB trouble shooting
N
Follow procedure OSD trouble shooting
Y Check Watch
Y Check HDD (User)
N
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
Replace Jack
LGE Internal Use Only
19. Digital TV Audio Trouble Shooting while recording (Watch & Record) Overall Block Diagram for Brazil DTV (LH70)
TU_SCLK, TU_SDATA, TU_SYNC
VA1G5BF8005
Qimonda/Hynix
TU_SIF SDA0/SCL0_3.3V LVDS RF_Switch, Gain_Switch
FRC IC (MST7323S)
CVBS, L/R, AV_DET
FRC Block
AV1 AV2
DDR2(256Mbit)
TU_CVBS_IN
(FHD, 120Hz)
SIDE_CVBS, SIDE_L/R, SIDE_DET X-tal 12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM … RGB/H/V
DDR2 (1Gbit)
D-sub RGB
Elpida/Hynix
Addr.[0:13], ctrl. data
Audio L/R
Audio L/R (for RGB) JACK BACK at REAR
LCD Module
BCM3556
HDMI 1
(Brazil)
3x1 HDMI Switch
HDMI 2 HDMI 3
DDR2 (1Gbit) Elpida/Hynix
Data[16:31]
Data [0 … 7] CS ,RE,WE…… SPDIF
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
RX/TX
Reset Switch
Copyright ⓒ 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
RX/TX
MAX3232
Bluetooth Module USB
NAND Flash (512Mbit)
+5V
DP1/DM1
USB_DM1
DP2/DM2
USB_DP1 USB_DM2
O.C. Protector
USB_DP2 +5V
Reset IC
X-tal
I2S
SCL, SDA_3.3V
SCL, SDA_3.3V
54MHz
CLK,TDI,TDO,MS,RST
Digital AMP NTP3100L
NVRAM MICOM (MTV416GMF) JTAG
X-tal 24MHz
LGE Internal Use Only
19. Digital TV Audio Trouble Shooting while recording (Watch & Record)
Check video output
N
Follow procedure digital TV video trouble shooting while recording (watch & record)
N
Maybe BCM3556 internal audio DSP has problems. Replace It
Y Follow procedure All source audio trouble shooting
Copyright â&#x201C;&#x2019; 2009 LG Electronics. Inc. All right reserved. Only for training and service purposes
LGE Internal Use Only
EXPLODED VIEW IMPORTANT SAFETY NOTICE
LV2
510
A2
580
560
300
310
LV1
500
121
122
200N
120
A10
200T
200
801
802
910
550
530
200N
803
805
800
804
571
540
570
541
900
400
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.
Copyright LG Electronics. Inc. All right reserved. Only for training and service purposes
-59-
LGE Internal Use Only
HDMI3 * HDMI_CEC
+3.3V_VDDP_ST
9:G4;N10;AA14
R693 47K
HDMI_POWER_0
+1.8V_AMP
+3.3V_VDDP_ST HDMI_HPD_0
15 14 13 12 11 10 9 8 7 6 5 4 3 2
DDC_CLK
GND
GND
R605
SDA_HDMI_0
O8;Z13
SCL_HDMI_0
O8;Z12
CE_REMOTE
R657
0
R656
0 Z12
CK_GND R658
0
D0-
R607
0
D0+
R609
0
D1-
R603
0
D804 30V DRAIN1
H16;H26;I7;AL11
GATE2
H16;I7;Y26;AL11
CEC_REMOTE TMDS0_RXC-
CK+
L602
TMDS0_RXC+
Z12
TMDS0_RX0-
Z12
TMDS0_RX0+
Z11
TMDS0_RX1-
Z11
SOURCE2
9.1K
6
1
5
2
4
3
GND
D0_GND
C629 0.1uF 16V
R611 Q601 SSM6N15FU
CEC_REMOTE
NC
CK-
BLM18PG121SN1D
R3021 68K
OPT
OPT
Z13
MMBD301LT1G
VR601 10V
OPT
DDC_DATA
C608 0.1uF 16V
+3.3V_HDMI
D3.3V
L601 BLM18PG121SN1D
10V VR604
16
GND
OPT
17
5V 3.6K R601
18
OPT R684 0
R690 1K
HP_DET
10V VR607
20 19
+1.8V_HDMI
OPT
R687 0
0
20 GND
R608
C612 0.1uF 16V
12:E6
SOURCE1
HDMI_CEC GATE1
DRAIN2
C602 0.1uF 16V
0 GND
OPT
D1_GND D1+
R662
0
D2-
R663
0
R664
0
TMDS0_RX1+
Z11
TMDS0_RX2-
Z10
TMDS0_RX2+
Z10
D2_GND D2+
1 +3.3V_HDMI
JK602
@optio
R619 0
NO FLANGE
YKF45-7058V
C624
R692 1K
OPT 10V VR609
OPT
VR606 10V
OPT
GND
H26;O8
SDA_HDMI_0
H26;O8 H25
SCL_HDMI_0 TMDS0_RXC-
H25
TMDS0_RXC+
YKF45-7058V
NO FLANGE
@optio
HDMI1
H24
TMDS0_RX0-
H24
TMDS0_RX0+
H24
TMDS0_RX1TMDS0_RX1+
H23
+3.3V_VDDP_ST
9:G5;R6;AK15 HDMI_POWER_2
R694 47K
HDMI_HPD_2
TMDS0_RX2TMDS0_RX2+
+5.0V R615
C615
C614 0.1uF
C613 0.1uF
C610 0.1uF
C609 0.1uF
0.1uF
C607 0.1uF
RXD_5V
RXD_DDC_DAT
RXD_DDC_CLK
RXD_HPD 76
77
78
79
RXD_DC+
VDDH[3V3]_7
RXD_D0-
RXD_D0+
VSS_10
RXD_D1-
RXD_D1+
VDDH[3V3]_8
RXD_D2-
RXD_D2+
VDDC[1V8]_3
VSS_11
RXD_DC80
81
82
83
84
85
86
87
88
89
90
OUT_D2+
OUT_D2-
VDDO[1V8]
OUT_D1+
OUT_D1-
RXC_D2-
TMDS2_RX2+
I4
VDDH[3V3]_6
TMDS2_RX2-
I4
70
VSS_2
7
69
RXC_D1+
VDDC[1V8]_1
RXC_D1-
I5
68
I5
67
VSS_8
TMDS2_RX1-
9
IC601
TMDS2_RX1+
8
RXA_HPD
TDA9996HL
66
RXC_D0+
RXA_5V
10
RXA_DDC_DAT
I6
65
RXC_D0-
TMDS2_RX0+
11
RXA_DDC_CLK
I6
64
VDDH[3V3]_5
TMDS2_RX0-
12
RXA_C-
13
63
RXC_C+
RXA_C+
14
62
RXC_C-
VDDH[3V3]_1
15
61
RXC_DDC_CLK
60
RXC_DDCC_DAT
RXA_D0+
16 17
59
RXC_5V
VSS_3
18
58
RXC_HPD
RXA_D1-
19
57
CEC
RXA_D1+
20
56
VSS_7
VDDH[3V3]_2
21
55
VDDS[3V3]
RXA_D2-
22
54
CDEC_STBY
RXA_D2+
23
53
INT/HP_CTRL
VDDH[1V8]_1
24
52
XTAL_OUT
51
XTAL_IN
NC
AL11
VSS_12
RXC_D2+
71
6
RXA_D0-
HDMI_POWER_1
HDMI_POWER_0
OPT
R688 0
GND 20
H23 H22
72
5
25
TMDS2_RXC+
I6 I7
TMDS2_RXCSCL_HDMI_2
I8;T4
SDA_HDMI_2
I8;T4
HDMI_HPD_2 I10 CEC_REMOTE H16;H26;I7;Y26
R635 0
HDMI2 R636 C619 0.1uF
JK600
AG7
4
50
TMDS1_RX2+
1
HDMI_HPD_0
VDDO[3V3] OUT_DDC_DAT
49
I28
C621 0.1uF 16V
12K
OUT_DDC_CLK
48
AG7
VSS_9
47
0
D2_GND D2+
VDDH[1V8]_2 R634 R12K
73
75
46
R673
TMDS1_RX2-
74
3
45
0
2
44
R672
1
43
D2-
C605 0.1uF 16V
VSS_1
42
0
R671
C628 0.1uF 16V
HDMI_POWER_2
OUT_C-
41
AF7
D1_GND D1+
C622 0.1uF 16V
C620 0.1uF 16V
OUT_C+
40
TMDS1_RX1+
HDMI_POWER_0
39
AF7
38
AF7
TMDS1_RX1-
37
TMDS1_RX0+
36
0
91
0
R670
35
R669
D1-
34
D0+
92
HDMI0
96
AE7
OUT_D0+
AE7
TMDS1_RX0-
97
TMDS1_RXC+
93
0
D0_GND
94
0
R668
CK_GND
95
R667
H26;I7;Y26;AL11 AE7
33
2
CK+ D0-
T8;AE7
CEC_REMOTE TMDS1_RXC-
32
3
0
31
5 4
0
R666
30
6
R665
98
8 7
CE_REMOTE CK-
T8;AD7
SCL_HDMI_1
99
9
+1.8V_HDMI SDA_HDMI_1
NC
29
10
GND
GND
28
11
R613 1.8K
27
12
0.1uF C626
0.1uF
OUT_D0-
13
C623 0.1uF 16V
R614 1.8K
100
14
DDC_DATA DDC_CLK
OPT
AD7
0.1uF C625
0.1uF C627
26
16 15
5V GND
OPT
18 17
3.6K R683
19
OPT R686 0
HDMI0_RX2-_BCM 11:F4 HDMI0_RX2+_BCM 11:F4
HDMI_HPD_1
20
HDMI0_RX1-_BCM 11:F4 HDMI0_RX1+_BCM 11:F4
OPT
R689 0
HDMI0_RX0-_BCM 11:F4 HDMI0_RX0+_BCM 11:F4
GND 20
R612
R695 47K
HDMI_SCL
0
+3.3V_VDDP_ST
HDMI0_RXC+_BCM 11:F4
+5.0V
9:G5;R10;AD6 HDMI_POWER_1
HP_DET
HDMI_SDA
HDMI2
HDMI0_RXC-_BCM 11:F4
GND
0 OPT
TMDS2_RXC+
AL12
R675
0
TMDS2_RX0-
AL13
D0+
R679
0
TMDS2_RX0+
AL13
D1-
R680
0
TMDS2_RX1-
AL13
SCL/SEL0
PD
0 MODE
0 R625
C611
D1_GND
TMDS1_RX2TMDS1_RX2+
HDMI_POWER_1
H13
HDMI_POWER_2
D0_GND
TMDS1_RX1+
I19
H14
D0-
SDA/SEL1
R622
VDDC[3V3]
VDDC[1V8]_2
CDEC_DDC
VSS_6
RXB_D2+
RXB_D2-
VDDH[3V3]_4
RXB_D1+
RXB_D1-
VSS_5
RXB_D0+
RXB_D0-
VDDH[3V3]_3
RXB_C+
RXB_C-
RXB_DDC_CLK
TEST
RXB_5V
RXB_HPD
HDMI_HPD_1
CK+
C618 0.1uF 16V
0
AL12
0
R624
TMDS2_RXC-
R674
VSS_4
R691 1K
0
RXB_DDC_DAT
VR602 10V
OPT
R678
CK_GND
C617 0.1uF 16V
+3.3V_HDMI R628 4.7K OPT
R623
R630 OPT R631 OPT
0
TMDS2_RX1+
AL13
D2-
R676
0
TMDS2_RX2-
AL14
TMDS2_RX2+
AL14
R653 47K
D2_GND R682
D2+
0
1
JK601 YKF45-7054V
R654 47K SDA_HDMI_2 SCL_HDMI_2
FLANGE
EDID Pull-up
GND
HDMI S/W For MSTAR Platform
@optio
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
HDMI1
SCL1_3.3V 9:I4;3:D3
R681
H13
0.1uF D1+
9:I4;3:D3 SDA1_3.3V
2
CK-
C606 0.1uF 16V
TMDS1_RX1-
4 3
0
C604 0.1uF 16V
H14
5
R677
OPT
C601 0.1uF 16V
TMDS1_RX0+
6
SCL_HDMI_1
H15
7
SDA_HDMI_1
TMDS1_RX0-
8
SDA_HDMI_0 SCL_HDMI_0
T4;AL12 SCL_HDMI_2 CEC_REMOTE H16;H26;Y26;AL11
CE_REMOTE
0 R632
+1.8V_HDMI
H15
9
47K
TMDS1_RXC+
10
T4;AL12
R629
H16
11
SDA_HDMI_2
NC
R604 47K
47K
SCL_HDMI_1
12
GND
R627
TMDS1_RXC-
13
R626 47K
GND
0
H16
14
C616 0.1uF 16V
C603 0.1uF
H17;T8 H17;T8
15
DDC_CLK
OPT
SDA_HDMI_1
16
GND DDC_DATA
OPT
17
3.6K R602
18
OPT R685 0
5V
OPT
HP_DET 19
OPT 10V VR608
For Only TDA9996 ES3
20
BCM (BRAZIL VENUS)
2008. 10.15
LEE GI YOUNG HDMI
2
15
IC503 D3.3V
AZ1117H-1.8TRE1(EH13A) INPUT
3
1
+1.8V_AMP
ADJ/GND
2 C548 22uF 16V
OUTPUT
C549 0.1uF 16V
GND
C551 0.1uF 16V
C552 22uF 16V
+24V_AMP
+24V
L511 MLB-201209-0120P-N2
SPK_L+
+24V_AMP R518 T_68uF_Capacitor
C511 R504 0
C508 0.1uF
PVDD1B_2
PVDD1B_1
OUT1B_2
OUT1B_1
PGND1B_2
PGND1B_1
BST1B
VDR1B
48
47
46
45
44
43
PVDD1A_1
49
PVDD1A_2
OUT1A_1
OUT1A_2
51 50
52
NC
41
VDR2A
3
40
BST2A
AD
4
39
PGND2A_2
DVSS_1
5
38
PGND2A_1
VSS_IO
6
37
OUT2A_2
CLK_I
7
36
OUT2A_1
IC501 NTP-3100L
C507 1000pF 50V
VDD_IO
8
35
PVDD2A_2
DGND_PLL
9
34
PVDD2A_1
3.3
SPEAKER_L
R528
1F C541 0.1uF 50V
R519
R524 4.7K
3.3 C545 0.01uF 50V
R503
AGND_PLL
C525 22000pF R520
50V
C533 1000pF 50V
10
33
PVDD2B_2
LFM
11
32
PVDD2B_1
R521
AVDD_PLL
12
31
OUT2B_2
5.6
DVDD_PLL
13
30
OUT2B_1
TEST0
14
29
PGND2B_2
C510 10uF 10V
SPK_L-
H3
SPK_R+
H3
28
C518 1uF 10V
C513 0.1uF 16V
1S
C546 C539 0.47uF 50V
C542
R525
0.1uF 50V
4.7K
0.01uF 50V R529
SPEAKER_R
3.3
1F
R530 C543
R526
0.1uF 50V
4.7K
3.3 C547 0.01uF 50V
SPK_R-
H3
+24V_AMP R522 3.3
PGND2B_1
27 BST2B
26 VDR2B
25 FAULT
24 MONITOR_2
23 MONITOR_1
22 MONITOR_0
21 SCL
20 SDA
19 BCK
18 WCK
+1.8V_AMP
17
C505 0.1uF 16V
EAN60664001
L505 AD-8770 EAP60684501 2S 2F
5.6
C534 1000pF 50V
15
C503 10uF 6.3V
PGND1A_1
42
2
3.3K
C502 0.1uF 16V
C523 16V1uF
1
RESET
16
100pF 50V
1S
R527
Change 22uH(L504,L505) TO 15uH/6.3mm After DV1
VDR1A
DVDD
C504
0.01uF 50V
C521 1uF 16V
BST1A
SDATA
C501 10uF 10V
10V
DVSS_2
L501
1uF
L502 R501 0
MLB-201209-0120P-N2
+1.8V_AMP
MLB-201209-0120P-N2
9:G6 +1.8V_AMP AUDIO_M_CLK
53
C506 1000pF 50V
C532 1000pF 50V
C526
4.7K
H3
C544 0.01uF 50V
L503 PGND1A_2
9:G7;9:I3;12:I4 AMP_RST
C553 68uF 35V @optio
C540 0.1uF 50V C538 0.47uF 50V
5.6
54
100
C531 1000pF 50V
R523
C519 22000pF 50V
55
R502
C522 0.1uF 50V
C520 0.1uF 50V
C514 22000pF 50V
D3.3V
56
MLB-201209-0120P-N2
C515 0.01uF 50V
L504 AD-8770 EAP60684501 2S 2F
5.6
R511 3.3
C527
C528
0.01uF 50V
0.1uF 50V
C530 0.1uF 50V
C529 68uF
C535 0.01uF 50V
WAFER-ANGLE
H5
SPK_L+
C524
4 L508 120-ohm
T_68uF_Capacitor
22000pF 50V
5
L507 120-ohm
H5
SPK_L-
H4
SPK_R+
H4
SPK_R-
3 L510 120-ohm
R513 AMP_MUTE 11:F7
BCM_I2S_DATA_OUT
11:F6
BCM_I2S_WORD_CLK
11:F7
BCM_I2S_BIT_CLK
9:I4;2:AH5 9:I4;2:AH5
SDA1_3.3V SCL1_3.3V
R505 R506
100
C517 33pF 50V
100
R507
100
R508
100
R509
100
2 L509 120-ohm
12:F3
100
1 P501
OPT
2A => 5A C512 33pF 50V
C509 33pF 50V
MCLK SDATA WCK BCK TP is necessory Monitor0_1_2 TP is necessory
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM (BRAZIL VENUS)
KIM JONG HYUN AUDIO
2008. 10.15
3
15
* FROM LIPS & POWER B/D -->Apply changed Pin Map +12V
+3.3V_ST
+5V_ST L806
GND
15
16
GND
24V
17
18
24V
A.Dim
21
22
Error_Out
N.C
23
24
PWM_Dim
C812 0.1uF 50V
C804 1uF 50V
C807 68uF 35V
R818 3.3K
R815 100 OPT R816 6.8K
C895 0.1uF 50V
C B
E Q806 2SC3052
OPT R826 10K
R824 10K
5
D2_2 D2_1
10uF 25V
C872 1uF
Q903 2SC3875S(ALY) OPT
MLB-201209-0120P-N2 L813
INPUT
ERROR_OUT 12:F6
C806 R802 0 0.1uF 16V OPT
3 1
D802 1N4148W 100V
C887
A1[RD] OPT R845 15K
50V
C835 1uF 25V
VCC
C1805 1uF 25V
16V 0.1uF
6.3V
C877
NC_3 R856 22K
C3007
5
VO
10uF
4
R855 12.4K 1%
6
6.3V
3
ADJ
C875
7
10uF
R846
1K OPT A1[RD] OPT
2
GND
C
33uF 10V C888 A2[GN]
6.3V
8
D805 SAM2333
G2
6
4
5
D2_1
22uF 16V
0.1uF
+3.3V_VDDP_ST +5V_ST
Q804 SI4925BDY
CB3216PA501E L801
* +12v -> PANEL_POWER
C1807
10uF 6.3V
0.01uF
C865
C861
4V
1.2K
R872
6.3V C854
10uF
330uF
D2_2
+12V
* +5v_ST to +3.3V_ST
+3.3V_ST
S1
1
8
D1_2
G1
2
7
D1_1
S2
3
6
D2_2
G2
4
5
D2_1
7:I5;7:I7 12V_TCON
OPT IC801 AZ1117D-3.3TRE1 INPUT
3
2
C803 0.1uF 16V
R812 47K
L8012 MLB-201209-0120P-N2
R810 22K
OUTPUT
1 C801 10uF 16V
ADJ/GND
C817 4.7uF 25V
1uF 25V
1uF 25V
C3009
C898
3
D1_1
3.3
7
R836
2
A1.2V
C833 22uF 25V
47K R813 OPT R806 10K
12:I5 PANEL_CTL
R805 10K B
2SC3052
C Q803 2SC3052
B C
E
22K
8
C870 0.1uF 16V
1
E
R811
7
S2
NC
SC4215ISTRT IC803
NC_2 C868 10uF 10V
Q802
9
G1
D1_2
470pF
6
DRV
8
C847
GND_1
10
1uF 25V
LDFB
5
C1800
LDOG
1
C844
S1
C852
DL
0.1uF
11
C839
4
470pF
2.2uH
GND_2 Q809 SI4804BDY
FB
GND 8
VIN
L821 MLB-201209-0120P-N2
L817
2K
12
PN
R842
13
3
D1.2V
200
2
DH
R847
COMP
14
1.5K
OCS
1
+5V_ST 0 R3033
BST
D801 1N4148W 100V
C1804
IC804 SC2621ASTRT
7
EN
* +5.0V to 1.2V
R848
1/8W
ADJ
2 R835 NC_1 1
MLB-201209-0120P-N2 L811
R833 390K
6
3
+5.0V
R852 10K
VO
EN
C858 33uF 10V
NC_1 L827 MLB-201209-0120P-N2
VIN 0
10uF 6.3V
R831 6.8K
NC_3 5
4
6.3V
C848 470pF
NC_2
+1.26V_MEMC
IC807 SC4215ISTRT
A2.5V
10uF
C837 1uF 25V
OPT C3022 0.1uF 50V
D2.5V
10uF
10uF 25V
600 mA
+1.8V_MEMC
C3011
D2_1
C3014
C825 220pF
R871 20K
* +1.26V Core for FRC
VOUT : 2.533V
C3010
5
C851
3.3
must be placed with pin#8,#10 as close as possible.
R814 15K 1%
COMP
16V
4
D2_2
470pF
0.1uF
6
R837
D3.3V
0.01uF
39K
3
D1_1
VCC
C832 1uF 25V
C815 2200pF
5
EN
C1808
10uF 16V
C894
R821 1.8K
C830 2200pF
C821 0.068uF
7
10uF 10uF 16V 16V
10V
8
S2
NC
2
C863
C1801
D1_2
33uF
9
7
G1
8
1.1K
6
DRV
1
C853 C860
R840
R853 300 R849 10K
DL
G2
GND_1
4
C859 0.1uF
C855 10uF 6.3V
* +1.8V_MEMC for FRC DDR
2.2uH
GND_2
C845
10
6
C846 330pF
L819
PN
R874
LDFB
5
3
C3021 10uF
LX_1
DH
S1
LDOG
50V
C841 10uF
7
+5.0V
0.1uF 50V
11
1000pF
C836
2
LX_2
12:A3;2:Y20;2:Z10;B3;C6;H5;7:A3;14:I7;14:J1
C1802
4
0.1uF
FB
8
12:A3;A6;B5;F7;G7;I2;14:B2
Q810 SI4804BDY
FB
AGND
Vout = (1+R2/R1)*1.25
1
R844 11K
C838 1uF 25V
VIN
R1
R2
18K
12
L812 MLB-201209-0120P-N2
C840
MLB-201209-0120P-N2 L824
3
PGND 0.1uF
1.8V_BCM3556
+12V
100uF 16V
COMP
13
1% R825 66.5
1% R857 56 R819 56 1%
L815 3.6uH
C822 330uF C818 4V
ADJ/GND
0.1uF
* +12V to +5.0V
400 mA + 600 mA
IC805 AOZ1073AIL
OUTPUT
2
C811
C876 100uF 16V
0 R3032
IC806 SC2621ASTRT
14
+1.8V_MEMC
IC802
12:A3;A6;C4;F7;G7;I2;14:B2
1/10W
C886
+5.0V
+12V
2
415 mA @85% efficiency
D1.8V 750 mA
D3.3V
R827 10K OPT
OPC_EN
R834 150K
C885
must be placed with pin#8,#10 as close as possible.
INV_ON/OFF 12:I5
OPT
0 OPT
1
1K R863
* D1.8V
R870 10K
B
R807
OCS
OPT
C879 470pF
AZ1085S-ADJTR/E1
C829 1uF 25V OPT
BST
470pF C880
SAM2333
25V
L826 BG2012B080TF
R832 3.3K
R861 3.3
0.1uF
4
D1_1
C
6
C1803
OPC_OUT1 7:I5
C1806 1uF 25V
OPT C3023 0.1uF 50V
7
3
R841
R822 0
VCC
R830 0
E
PWM_DIM 9:G7;9:I3;7:I5
8
2
+3.3V_ST
C
TruMotion_240Hz
Except_OPC R869 0
C856 6800pF
C802 68uF 35V
+5.0V
C808 16V 0.1uF OPT
9
7
S2 G2
R854 10K
25
6
G1
NC
C814 0.1uF 16V
C805 1uF 25V
Inverter_On
DRV
10
C3017 10uF 6.3V
D1_2
16V
L804 BG2012B080TF
4.7K R801
+24V
L805 CB4532UK121E
5
LDFB
GND_1
20
19
LDOG
8
LD1
12V
22uF 16V
1
0.1uF
GND
14
S1
R864 620
R862 5.6K
DL
11
33uF
12
13
4
C842
C819 22uF 16V
C899 100uF 16V
C827 100uF
10K
11
12V
JP1111
A_DIM 9:G6;9:I3
FB
GND
N.C
Q812 SI4804BDY
R843
5.2V
2.2uH
GND_2
0.01uF C884
5.2V
10
12
100uF 16V C883
8
9
3
10uF C882 6.3V
7
5.2V
COMP 220uF ==> 100uF*2 + 22uF for Depth
L807
10uF C881 6.3V
5.2V
CB4532UK121E
C3013
GND
L830 MLB-201209-0120P-N2
L828
PN
10uF 6.3V
6
13
+5V_ST
C878
5
14
2
A3.3V We’ll change SI4804 to KEC’s Product
0.1uF
4
GND
1
D803 1N4148W 100V DH
C1809
3
GND
OPT
BST
L829 MLB-201209-0120P-N2
+12V
C810
C826 47uF 25V
GND
10K OPT
OCS
GND
C828 0.1uF 50V
C896 22uF 16V
C824 0.1uF 50V OPT
POWER_ON
RL_ON 12:I5;14:E5
+3.3V_MEMC
C873 1uF 25V
22uF
L808 MLB-201209-0120P-N2
2
R828
B
C862 470pF
+12V
1
IC809 SC2621ASTRT
C
Q807 2SC3875S(ALY) E
N.C
1/10W
R829 0
RT1P141C-T112
P801 FM20020-24
D3.3V
MLB-201209-0120P-N2
R3025 0
R820 33K
R817 33K
L822
R859 330K
R873 3.3K
R823 1K
OPT
B
OPT
Q805 C820 15pF 50V
R3028 A2[GN]1K
E
C
MLB-201209-0120P-N2
FLASH, A1.2, +1.8_DDR_BCM3556, VTT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM (BRAZIL VENUS)
08.10.16
AN SO YOUNG POWER
4
15
D1.8V
C354 0.1uF
C353 0.1uF
C352 0.1uF
C335 470pF
C334 2700pF
C333 0.047uF
C332 0.01uF
C331 0.1uF
C330 10uF
C329 470pF
C328 2700pF
C327 0.047uF
C326 0.01uF
C325 0.1uF
C324 10uF
C323 100uF
C351 0.1uF
C350 0.1uF
C349 0.1uF
C317 470pF
C316 2700pF
C315 0.047uF
C314 0.01uF
C313 0.1uF
C312 10uF
C311 470pF
C310 2700pF
C309 0.047uF
C308 0.01uF
C307 0.1uF
C306 10uF
C305 100uF
D1.8V
A1.2V
IC100 BCM3556
DDR0_CLK DDR0_CLKB DDR1_CLK DDR1_CLKB DDR01_A00 DDR01_A01 DDR01_A02 DDR01_A03 DDR0_A04 DDR0_A05 DDR0_A06 DDR01_A07 DDR01_A08 DDR01_A09 DDR01_A10 DDR01_A11 DDR01_A12 DDR01_A13 DDR1_A04 DDR1_A05 DDR1_A06 DDR01_BA0 DDR01_BA1 DDR01_BA2 DDR01_CASB DDR0_DQ00 DDR0_DQ01 DDR0_DQ02 DDR0_DQ03 DDR0_DQ04 DDR0_DQ05 DDR0_DQ06 DDR0_DQ07 DDR0_DQ08 DDR0_DQ09 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR1_DQ00 DDR1_DQ01 DDR1_DQ02 DDR1_DQ03 DDR1_DQ04 DDR1_DQ05 DDR1_DQ06 DDR1_DQ07 DDR1_DQ08 DDR1_DQ09 DDR1_DQ10 DDR1_DQ11 DDR1_DQ12 DDR1_DQ13 DDR1_DQ14 DDR1_DQ15 DDR0_DM0 DDR0_DM1 DDR1_DM0 DDR1_DM1 DDR0_DQS0 DDR0_DQS0B DDR0_DQS1 DDR0_DQS1B DDR1_DQS0 DDR1_DQS0B DDR1_DQS1 DDR1_DQS1B DDR01_RASB DDR_VREF0 DDR_VREF1 DDR01_WEB DDR_VDDP1P8_1
DDR1_VREF0
Qimonda
B24 B23 B17 C22
Qimonda
IC300
F20 R312 0 OPT R313
R301 22
C300 DDR01_CKE
DDR0_DQ[0-15]
DDR01_ODT
B12
DDR0_CLK
E5
C12
DDR0_CLKb
E5
A13
DDR1_CLK
H5
A12
DDR1_CLKb
B15
DDR01_A[0]
E14
DDR01_A[1]
A15
DDR01_A[2]
D15
DDR01_A[3]
E13
DDR0_A[4]
DDR0_A[4-6]
B6;H2
H5 DDR01_A[0-3]
DDR0_A[4-6]
E6;H6;H2
D6;H2
DDR0_A[5]
F13
DDR0_A[6]
C14
DDR01_A[7]
F14
DDR01_A[8]
B14
DDR01_A[9]
D14
DDR01_A[10]
C13
DDR01_A[11]
D13
DDR01_A[12]
B13
DDR01_A[13]
F15
DDR1_A[4]
C15
DDR1_A[5]
D16
DDR1_A[6]
DDR01_A[7-13]
J2
DDR01_A[0]
A0
M8
DDR01_A[1]
A1
M3
DDR01_A[2]
A2
M7
DDR01_A[3] DDR0_A[4]
A3
N2
A4
N8
DDR0_A[5]
A5
N3
DDR0_A[6]
A6
N7
DDR01_A[7]
A7
P2
DDR01_A[8]
A8
P8
DDR01_A[9]
A9
P3
DDR01_A[10]
A10/AP
M2
DDR01_A[11]
A11
P7
DDR01_A[12]
A12
E6;H6;H2
DDR1_A[4-6]
BA0
L2
B5;H5;I1
DDR01_BA1
BA1
L3
B5;H5;I1
DDR01_BA2
BA2
L1
H6;H1
DDR01_BA1
E15
DDR01_BA2
A17
DDR01_CASb
A8
DDR0_DQ[0]
B11
DDR0_DQ[1]
B8
DDR0_DQ[2]
D11
DDR0_DQ[3]
E11
DDR0_DQ[4]
C8
DDR0_DQ[5]
C11
DDR0_DQ[6]
C9
DDR0_DQ[7]
DDR0_DQ[0-15]
J8
DQ1
DDR0_DQ[1]
H7
DQ2
DDR0_DQ[2]
H3
DQ3
DDR0_DQ[3]
H1
DQ4
DDR0_DQ[4]
H9
DQ5
F1
DQ6
DDR0_DQ[6]
F9
DQ7
DDR0_DQ[7]
C8
DQ8
C2
DQ9
D7
DQ10 DQ11
DDR0_DQ[11]
D1
DQ12
DDR0_DQ[12]
D9
DQ13
DDR0_DQ[13]
B1
DQ14
DDR0_DQ[14]
B9
DQ15
DDR0_DQ[15]
VDDQ5
IC300-*1
G1
VDDQ4
G3
VDDQ3
G7
VDDQ2
A3
N2
A4
N8
B3
A5
N3
A6
N7
DDR1_DQ[4] DDR1_DQ[5]
E3
VSS4
A8
J3
VSS3
N1
VSS2
B20
DDR1_DQ[6]
D18
DDR1_DQ[7]
E18
DDR1_DQ[8]
NC1
A2
NC2
E2
NC3 DDR1_DQ[0-15]
DDR1_DQ[9]
D21
P9
R8
J6 VSSDL
VSS5
E8
DDR1_DQ[2]
B18
J7
VSS1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
D8
VSSQ6
E7
VSSQ5
F2
VSSQ4
F18
DDR1_DQ[10]
F8
VSSQ3
E20
DDR1_DQ[11]
H2
VSSQ2
DDR1_DQ[12]
A22
VDDL
M8
F3
A18 C21
J2
A0
M3
A3
DDR1_DQ[3]
VDDQ1
VREF
M7
R3
H8
J1
VSSQ1
A7
P2
A8
P8
A9
P3
A10
M2
A11
P7
A12
R2
BA0
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
C8
DQ8
C2
DQ9
D7
DQ10
D3
DQ11
D1
DQ12
D9
DQ13
B1
DQ14
B9
DQ15
L3
BA2
L1
CK
J8
CK
K8
CKE
K2
DDR1_DQ[14]
E17
DDR1_DQ[15]
A10
DDR0_DM0
C10
A1
VDD_5
E1
VDD_4
J9
VDD_3
M9
VDD_2
R1
VDD_1
K9
A9
VDDQ_10
CS
L8
C1
VDDQ_9
RAS
K7
C3
VDDQ_8
CAS
L7
C7
VDDQ_7
WE
K3
C9
VDDQ_6
E9
VDDQ_5
G1
VDDQ_4
G3
VDDQ_3
G7
VDDQ_2
G9
VDDQ_1
LDQS
F7
UDQS
B7
LDM
F3
UDM
B3 A3
LDQS
E8
E3
VSS_4
UDQS
A8
J3
VSS_3
N1
VSS_2
P9
VSS_1
NC_5
R3
NC_6
R7
F19 B10 B9 F10 F9
E2
NC_3
R8
DDR1_DM0
H4
DDR1_DM1
H4
DDR0_DQS0
E4
DDR0_DQS0b
E4
DDR0_DQS1
E4
DDR0_DQS1b
E4
DDR1_DQS0
H4
C19
DDR1_DQS0b
H4
E19
DDR1_DQS1
H4
D19
DDR1_DQS1b
A1
VDD5
E1
VDD4
CK
K8
B6;E5;I2
DDR01_CKE
CKE
K2
B6;E5;I1
DDR01_ODT
ODT
K9
A9
VDDQ10
CS
L8
C1
VDDQ9
DDR01_RASb
RAS
K7
C3
VDDQ8
B5;E5;I1
DDR01_CASb
CAS
L7
C7
VDDQ7
B2;E5;I1
DDR01_WEb
WE
K3
C9
VDDQ6
E9
VDDQ5
G1
VDDQ4
B3
DDR1_DQS0
LDQS
B3
DDR1_DQS1
UDQS
F7 B7
J1
G3
VDDQ3
G7
VDDQ2
G9 B3 B3
B3 B3
DDR1_DM0
LDM
DDR1_DM1
UDM
DDR1_DQS0b
LDQS
DDR1_DQS1b
UDQS
B2
VSSQ_10
B8
VSSQ_9
A7
VSSQ_8
D2
VSSQ_7
D8
VSSQ_6
E7
VSSQ_5
F2
VSSQ_4
F8
VSSQ_3
H2
VSSQ_2
H8
VSSQ_1
DDR1_DQ[9]
DDR1_DQ[12]
ELPIDA IC301-*1 EDE1116ACBG-1J-E
VDDQ1
B3
E8 A8
R3
NC5
R7
NC1
A2
NC2
E2
VDDL
DDR1_DQ[8]
F3
NC4
NC3
A3
VSS5
E3
VSS4
J3
VSS3
P9
R8
J7
J1
VREF
J2
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
A11
P7
A12
VSS2
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
D8
VSSQ6
L2
BA1
L3
BA2
VSS1
VSSQ5
F2
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
L1
G8
DQ0
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
C8
DQ8
C2
DQ9
D7
DQ10
D3
DQ11
D1
DQ12
D9
DQ13
B1
DQ14
B9
DQ15
A1
VDD_5
E1
VDD_4
J9
VDD_3
CK
J8
M9
VDD_2
CK
K8
R1
VDD_1
CKE
K2
ODT
K9
A9
VDDQ_10
CS
L8
C1
VDDQ_9
RAS
K7
C3
VDDQ_8
CAS
L7
C7
VDDQ_7
WE
K3
C9
VDDQ_6
E9
VDDQ_5
G1
VDDQ_4
G3
VDDQ_3
G7
VDDQ_2
G9
VDDQ_1
A3
VSS_5
LDQS UDQS
E7
R2
BA0
F7 B7
LDM
F3
UDM
B3
LDQS
E8
E3
VSS_4
UDQS
A8
J3
VSS_3
N1
VSS_2
NC_5
P9
VSS_1
R3
NC_6
R7
NC_1
B2
VSSQ_10
A2
NC_2
B8
VSSQ_9
E2
A7
VSSQ_8
NC_3
R8
D2 D8
VSSDL
J7
E7 F2
VDDL
J1
VSSQ_7 VSSQ_6 VSSQ_5 VSSQ_4
F8
VSSQ_3
H2
VSSQ_2
H8
VSSQ_1
* DDR_VTT DDR_VTT DDR_VTT
DDR1_VREF0
D3.3V
A23 C17
DDR1_DQ[15]
DDR1_CLKb
H4 DDR0_VREF0
DDR01_RASb E5;H5;I1
A7
J7
E4
B19
C16
A2
NC_2
VDDL
A20
DDR1_CLK
VSSDL VSS_5
VSSDL
E4
DDR0_DM1
DQ15
N1
ODT
NC_1
B22
B9
DDR1_DQ[5]
D1.8V
L2
BA1
DDR1_DQ[13]
F17
DDR1_DQ[14]
EDE1116ACBG-1J-E
A1
R7
DDR1_DQ[13]
DQ14
B6
B2;E5;I1
A2
G9
NC5
DQ13
B1
VDD1
E9
DDR1_DQ[1]
DQ12
D9
VDD2
ELPIDA
C20
D1
VDD3
VDDQ6
NC4
DDR1_DQ[11]
R1
C9
DDR1_DQ[0]
L2
DQ11
M9
K3
C18
BA0
D3
J9
WE
DDR0_DQ[15]
DDR01_BA0
DDR1_DQ[10]
R1
DDR01_WEb
DDR0_DQ[14]
B5;E5;I1
DQ10
J8
B2;H5;I1
UDQS
R2
DQ9
D7
CK
VDDQ7
DDR0_DQS1b
A12
R303 100
C7
B3
P7
DQ8
C2
B6
L7
LDQS
M2
A11
C8
VDD1
CAS
DDR0_DQS0b
P3
A10/AP
DDR01_A[11]
DDR1_DQ[7]
VDD2
DDR01_CASb
B3
A9
DDR01_A[10]
DQ7
VDD3
B5;H5;I1
DDR0_DQ[13]
P8
DDR1_DQ[6]
F9
M9
VDDQ8
DDR0_DM1
N7 P2
A8
DQ6
J9
VDDQ9
B3
A6 A7
DDR01_A[8]
F1
E1
VDDQ10
UDM
DDR1_A[6] DDR01_A[7]
DQ5
L1
C3
LDM
N3
DDR1_DQ[4]
H9
L3
C1
DDR0_DM0
N8
A5
DQ4
BA2
A9
B3
A4
DDR1_A[5]
N2
DDR1_DQ[3]
H1
BA1
K7
B7
A3
DDR1_DQ[2]
DQ3
DDR01_BA2
L8
UDQS
DDR01_A[3] DDR1_A[4]
DDR1_DQ[1]
DQ2
H3
DDR01_BA1
K9
DDR0_DQS1
M7
DQ1
H7
B5;E5;I1
CS
B3
M3
A2
G2
B5;E5;I1
RAS
B3
A1
DDR1_DQ[0]
VDD4
ODT
G6
M8
DQ0
VDD5
DDR01_RASb
F7
A0
G8
A1
DDR01_ODT
LDQS
J2
DDR01_A[2]
DDR01_A[12]
B2;H5;I1
DDR0_DQS0
VREF
DDR01_A[1]
DDR01_A[9]
B6;H5;I1
E8
B21
DDR0_DQ[9]
K2
DDR0_DQ[12]
F8
DDR0_DQ[8]
CKE
K8
DDR01_A[0]
DDR1_A[4-6]
DDR0_DQ[10]
DDR01_CKE
F12 D10
B4
DDR01_A[0-3,7-13]
DDR0_DQ[5]
D3
DDR0_DQ[11]
F11
B5;H1
B6;H5;I2
DDR0_DQ[10]
E9
G2
B6;E6;H2;B5
DDR0_CLKb
DDR0_DQ[9]
E10
DDR0_DQ[0]
B6
DDR0_DQ[8]
D8
DQ0
CK
DDR01_BA0
B16
CK
G8
D1.8V
DDR0_CLK
B6
R300 100
F16
R2
DDR01_BA0
B5;H5;I1
DDR1_DQ[0-15]
HYB18TC1G160C2F-1.9
C322
470pF 0.1uF VREF
B6;H6;H2;B5 DDR01_A[0-3,7-13]
E5;H5;I1
C23
E12
C321
B4
470pF 0.1uF
240
E16
IC301
HYB18TC1G160C2F-1.9
C301
E5;H5;I2
DDR01_A[0-3,7-13] D1.8V
DDR01_WEb
C7 D22
DDR_VDDP1P8_2 C355 0.1uF
1uF 470pF 470pF
1uF
1uF 470pF 470pF
C361
DDR_EXT_CLK
DDR0_VREF0
C360
DDR_COMP DDR01_ODT
C346
C342
DDR01_CKE
C345
0.1uF
B7
C343
DDR_PLL_LDO
0.1uF
A24
C358
DDR_BVSS1 DDR_PLL_TEST
A6
C344
DDR_BVSS0
C359
DDR_BVDD1
C347
DDR_BVDD0
1uF
C869 100uF 16V
C874 10uF 10V
C864 0.1uF 16V
R304
DDR01_A[0]
75
EN
1
8
2
7
R305 VTT
75
C337 0.01uF
DDR01_A[3]
R306
C338 0.01uF
DDR01_A[7]
75
DDR0_A[5] DDR0_A[6]
VTT_IN
DDR1_VREF0
DDR01_A[8] VTTS
DDR0_VREF0 VREF
0
3
6
4
5
C336 0.01uF
DDR01_A[2]
D1.8V
DDR0_A[4] GND
R850
DDR1_A[4] DDR01_A[1]
DDR0_A[4-6]
IC808 BD35331F-E2
VCC
C339 0.01uF
DDR01_A[9]
VDDQ
DDR01_A[10]
R307
DDR01_A[11]
75
DDR01_A[12]
BCM recommends to remove this R
C340 0.01uF
DDR01_A[13]
1M R858
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
16V
C834 0.1uF 16V
0.1uF
C831 0.1uF 16V
0
C866
R851
C867 100uF 16V
C897 0.1uF 16V
C871 1uF 6.3V
B6;E5;H5
DDR01_CKE
OPT DDR1_A[5]
75
B5;E5;H5 B5;E5;H5
DDR1_A[4-6]
R310 R308
C341 0.01uF
75
DDR1_A[6] DDR01_BA1
C362 0.1uF
DDR01_BA2
B2;E5;H5
DDR01_RASb
R309
B5;E5;H5
DDR01_BA0
75
B5;E5;H5
DDR01_CASb
B2;E5;H5
DDR01_WEb
B6;E5;H5
DDR01_ODT
75
R311
BCM (BRAZIL VENUS)
HONG YEON HYUK DDR Memory
08.10.15
6
15
M_XTALI
M_XTALO
LVDS_TX_0_DATA0_P
LVDS_TX_0_DATA1_N
LVDS_TX_0_DATA0_N
LVDS_TX_0_DATA1_P
LVDS_TX_0_DATA2_P
LVDS_TX_0_CLK_N
LVDS_TX_0_DATA2_N
LVDS_TX_0_CLK_P
LVDS_TX_0_DATA3_N
A15
LVBCKP
URSA_BCKP
GPIO[12]
F3
A16
LVBCKM
URSA_BCKM URSA_B3P
GPIO[13]
G2
B16
LVB3P
GPIO[22]
M4
C16
LVB3M
URSA_B3M
GPIO[23]
M5
D15
LVB4P
URSA_B4P
GPIO[14]
G3
D16
LVB4M
URSA_B4M
GPIO[15]
E4
F9 G10
LVC0P
GPIO[18]
H4
E16
LVC0M
URSA_C1P
0.1uF
J4
E14
GPIO[20]
K4
F14
LVC1M
URSA_C1M
GPIO[21]
L4
F16
LVC2P
URSA_C2P URSA_C2M
J6
F15
LVC2M
GND_7
H9
G15
LVCCKP
URSA_CCKP
G16
LVCCKM
URSA_CCKM
G14
LVC3P
URSA_C3P
H14
LVC3M
URSA_C3M URSA_C4P
H3
J16
MDATA[22]
J1
J14
LVD1P
URSA_D1P
K14
LVD1M
URSA_DQ[27]
MDATA[27]
J2
URSA_DQ[28]
MDATA[28]
J3
G9
GND_3
URSA_DQ[25]
MDATA[25]
K1
L14
LVD2P
URSA_DQ[30]
MDATA[30]
K2
L15
LVD2M
AVDD_DDR_2
K6
L16
LVDCKP
URSA_DCKP
DQM[3]
K3
M16
LVDCKM
URSA_DCKM
DQM[2]
L1
F8
GND_10
J8
M15
LVD3P
L2
M14
LVD3M
L3
N16
LVD4P
AVDD_DDR_4
L6
N15
LVD4M
VDDP_3
L8 H10
H6
VDDC_5 GPIO[24]
N6 E12
GPIO[7]
L7
D14
GPIO[6]
MDATA[31]
M3
F12
GPIO[5]
MDATA[24]
N1
E13
GPIO[4]
GND_11
J9
F13
GPIO[3]
URSA_DQ[26]
MDATA[26]
N2
G13
GPIO[2]
URSA_DQ[29]
MDATA[29]
N3
H13
GPIO[1]
L10
J13
GPIO[0]
P1
K12
PWM0
L12
PWM1
K13
CSZ
M12
SDO
M13
SDI
L13
SCK
G7
N14
GPIO[30]
L9
N13
R2
MCLKZ[0]
P2
33 34 35 36 37 38 39 40
OPC_EN 0 R936
OPC_OUT1 PWM_DIM
42 43 44
0 R937 OPC_EN
45 46
+3.3V_MEMC 12V_TCON
47
49 50 51 52
R941
OPC_EN
R940
LVDS_SEL
0 OPC_EN 0
URSA_D4M
+3.3V_MEMC
R938
1
URSA_D4M URSA_D4P URSA_D3M URSA_D3P M_SPI_DO M_SPI_DI M_SPI_CK
3 4 5 6 7
M_SPI_CZ
GPIO[29] GPIO[28]
URSA_DCKM URSA_DCKP
8 9 10
URSA_D2M URSA_D2P URSA_D1M URSA_D1P URSA_D0M URSA_D0P
11 12 13 14 15 16
G6
17 18
VDDC_4
M11 RESET
N11 GND_17
N9
P16
N10 GPIO[27]
GPIO[26]
MCLKZ[1]
T16
R16 MCLK[1]
MDATA[5]
R15
T15
P15 MDATA[2]
MDATA[0]
MDATA[7]
P14 MDATA[13]
R14 MDATA[10]
T14 MDATA[8]
P13 MDATA[15]
R13 DQSB[1]
T13
URSA_D2M
2
URSA_C4M URSA_C4P URSA_C3M URSA_C3P
GPIO8
PWM1
PWM0
I2C
HIGH
LOW
HIGH
URSA_CCKM URSA_CCKP
EEPROM
HIGH
HIGH
LOW
SPI
HIGH
HIGH
HIGH
URSA_C2M URSA_C2P URSA_C1M URSA_C1P URSA_C0M URSA_C0P
19 20 21 22 23 24 25
C950
C951
0.1uF
27 28 29 30 31 32 33
+3.3V_MEMC
C939
C938
C936
C934
C932
+3.3V_MEMC 10K R913
DQS[1]
H11
J7 GND_9
VDDP_1
P12 DQSB[0]
R12 DQS[0]
T12
P11
DQM[0]
DQM[1]
J11
R11
T11 MDATA[9]
MDATA[14]
AVDD_DDR_1
R10
P10 MDATA[12]
MDATA[11]
K11
T10 MDATA[6]
AVDD_DDR_3
P9
R9
K7 GND_13
MDATA[1]
MDATA[3]
T9
F7 VDDC_3
MDATA[4]
C945
* SPI FLASH
32
URSA_A2M URSA_A2P URSA_A1M URSA_A1P URSA_A0M URSA_A0P
26
0.1uF
K10
P8
N8 MCLKE
GND_16
C941
MADR[3]
T8
P7
R8 MADR[7]
MADR[9]
MADR[12]
L11
T7
R7 MADR[5]
AVDD_DDR_7
MADR[10]
P6
R6
MADR[1]
P5
T6
BADR[0]
C922
WEZ
0.1uF
BADR[1]
T3
C921
RASZ
0.1uF
N4
R5
URSA_ODT
N12
N5 T5
ODT
[N4]
P4
MVREF
[N12]
[N5]
MADR[8]
GND_1
[L9]
MADR[6]
C925 0.1uF
[N13]
MADR[11]
URSA_MCLKZ
30
P904 TF05-41S
0.1uF
MCLK[0]
29
31
0.1uF
0.1uF
T2
28
URSA_D4P
M2
MDATA[21]
27
URSA_D3M C953
M1
URSA_DQ[21]
26
URSA_D3P
DQS[3]
T1
25
URSA_D2P 0.1uF
DQSB[3]
MDATA[18]
24
URSA_D1M
AVDD_DDR_5
URSA_DQ[18]
23
0
AVDD_33_1
DQS[2]
R1
22
C957
DQSB[2]
MDATA[16]
21
OPT R953
48
VDDP_2
URSA_DQ[16]
20
URSA_ACKM URSA_ACKP
URSA_C0M
LVC1P
LGE7329A
19
URSA_C0P
GPIO[19]
IC901
17
41
E15
F6
16
GND_4
G4
MDATA[23]
14
URSA_A4M URSA_A4P URSA_A3M URSA_A3P
C956
AVDD_33_2
GPIO[17]
AVDD_DDR_6
13
3.3K OPT
F4
URSA_DQ[23]
CB3216PA501E
L909
REXT D12
LVB1M C14
LVB0M
LVB0P
LVB1P C13
GPIO_4 D7
A13
B13
LVA4M
GPIO_6 D9
B12
LVA3M
LVA3P
LVA4P A12
C12
C11
LVACKP
LVACKM A11
B11
LVA2M B10
LVA2P A10
LVA1M C10
LVA0M
LVA0P
LVA1P C9
A9
F2
URSA_DQ[22]
0.1uF
1000pF 50V
C961
0.1uF
C949
0.1uF
C948 AVDD_PLL
B9
GPIO_8
GND_2 G8
F10
D11
GPIO_12
GPIO[25]
SCLM
SDAM
GPIO_9 D13
E11
N7
D6
D5
A14
GPIO_1
GPIO_2
XIN D3
B14
GPIO[11]
GND_8
0.1uF 50V C960
10uF C954
L908 10uF C952
BLM18PG121SN1D
URSA_B1M
URSA_B1P
URSA_B0M
URSA_B0P
URSA_A4P
URSA_A4M
URSA_A3P
URSA_A3M
URSA_A2M
URSA_ACKP
URSA_ACKM
URSA_A1M
URSA_A1P
URSA_A2P
URSA_A0M
URSA_A0P
BLM18PG121SN1D
1uF
0.1uF C944
L907
C943
0.1uF GPIO_14
GPIO_13
XOUT D4
K16
K15
AVDD_LVDS_2
GND_5 H7
G11
B8
RO0N
RO0P A8
C8
RO1N
RO2N
RO1P C7
A7
B7
RO2P
ROCKP
ROCKN B6
A6
C6
RO3N
RO3P C5
A5
RO4N
C942
0.1uF
C940 GND_6
RO4P B5
H8
F11
AVDD_LVDS_1
RE0P
RE0N B4
A4
C4
RE1N
RE1P C3
RE2P
RECKN
RE2N A3
B3
B2
A2
RECKP
RE3P
RE3N C2
C1
B15
URSA_D0M
URSA_MCLK
C908
0.1uF
E2
LVB2M
0.1uF
C906
ISP_TXD_TR
10uF
B6
RE4N
URSA_B2M
GPIO[10]
AVDD_MEMPLL
4
A1
URSA_B2P
J10
L902
LVB2P
URSA_D0P
+3.3V_MEMC BLM18PG121SN1D
C15
URSA_C4M
URSA_DQ[24]
2.2K R907 OPT
[D1]
LVD0M
C920
OPT
E5
LVD0P
URSA_DQ[31]
2.2K R908
VDDC_1
LVC4M
URSA_DQS3
B6
GPIO_3
D2
J15
URSA_DQSB3
3
E3
GPIO_10
H15
0.1uF
12
BIT_SEL
H16
C928
ISP_RXD_TR
GPIO_11
H2
0.1uF
2
E10
H1
* ISP Port for MEMC
1
D10
GPIO_7
MDATA[17]
URSA_DQS2
+5.0V
GPIO_5
MDATA[19]
URSA_DQSB2
P902
D8
URSA_DQ[17]
C919
8
18
0.1uF
URSA_DQ[19]
URSA_DQM2
7
11
URSA_B2M URSA_B2P URSA_B1M URSA_B1P URSA_B0M URSA_B0P
C955
[E1]
0.1uF
6
15
LVC4P
C918
5
URSA_BCKM URSA_BCKP
820
MDATA[20]
URSA_DQM3
TJC2508-4A
R931
GND_15 K9
C927
URSA_DQ[20]
4
10
K8
VDDC_2
3
9
GND_14
0.1uF 0.1uF
2
URSA_B4M URSA_B4P URSA_B3M URSA_B3P
G1
GND_12
BLM18PG121SN1D
10uF C909
10uF C907
0.1uF C3020
0.1uF
C901
C904
22uF/16 CST PROBLEM
10uF
L904
+1.8V_MEMC
URSA_DQ[0-31]
PI Result
100
R954
C930
100
1
3.3K
C913 0.1uF 16V
100 R928
D1 F1
R4
10uF
L903 10uF C911
C912 0.1uF 16V
1K
100 R922
P903 TF05-51S
GPIO[9]
GPIO[16]
R916 OPT
R927
R955
1K
100
R921
R948
R915
C910
BLM18PG121SN1D
+3.3V_MEMC
R926
100
499 OPC_EN
+3.3V_MEMC
100
R920
OPT R949
1/16W 5%
R925
100
+3.3V_MEMC
3.3K
9:G6;I5
R919
12V_TCON
+3.3V_MEMC
1K
R3029 0
LVDS_SEL
100
1K OPT
C929
100
1K R942
OPT
100 R924
1K R943
JP902
B1
RE4P
JP901
GPIO[8]
E1
R923
100 R918
OPT R939
R912
SCLS
T4
SCL3_3.3V
SDAS
100 100
MADR[4]
9:I4
R911
MADR[2]
SDA3_3.3V
0
P3
9:I4
R910
R3
ISP_TXD_TR
CASZ
A3
MADR[0]
ISP_RXD_TR
0.1uF
A3
0.1uF C937
PI Result
10uF C935
C926
L906
0.1uF
0.1uF
C923
C931
10uF C916
6.3V C3019 10uF
C915
10uF
C914 0.1uF
6.3V
22uF/16 CST PROBLEM
10uF 10V C933
L905
BLM18PG121SN1D
BLM18PG121SN1D
+3.3V_MEMC
0
LVDS_TX_0_DATA4_N
LVDS_TX_0_DATA4_P R917
+1.26V_MEMC
R909
LVDS_TX_0_DATA3_P
LVDS_TX_1_DATA0_N
LVDS_TX_1_DATA1_N
LVDS_TX_1_DATA1_P
LVDS_TX_1_DATA0_P
LVDS_TX_1_DATA2_N
LVDS_TX_1_DATA2_P
FRC_XTAL_20PF
FRC_XTAL_15PF
FRC_XTAL_20PF
C947-*1 20pF
15pF
LVDS_TX_1_CLK_N
C947
15pF
LVDS_TX_1_DATA3_P
M_XTALI 12MHz
C946 C946-*1 20pF
LVDS_TX_1_CLK_P
M_XTALO
LVDS_TX_1_DATA4_N
1M X901
LVDS_TX_1_DATA3_N
LVDS_TX_1_DATA4_P
R929
* XTAL
34 35 36 37
H3
4.7K R933
40 41
URSA_DQ[5]
H3
M_SPI_DI
URSA_DQ[2]
M_SPI_CK
URSA_DQ[0]
56
URSA_DQ[7]
56
R952
URSA_DQ[13]
R951
DIO
URSA_DQ[10]
CLK
0
R930
URSA_A[3]
URSA_A[7]
URSA_A[12]
URSA_A[9]
URSA_A[5]
URSA_A[10]
URSA_A[1]
URSA_A[11]
URSA_A[8]
URSA_A[6]
URSA_A[4]
URSA_A[2]
HOLD
URSA_DQ[8]
5
URSA_DQ[15]
6
4
URSA_DQ[14]
7
3
URSA_DQ[9]
2
URSA_DQ[12]
WP
39
42
URSA_DQ[11]
DO
GND
VCC
URSA_DQ[6]
10K
8
URSA_DQ[1]
56
R947
1
38
FRC_RESET URSA_DQ[3]
R946
CS
URSA_A[0]
56
0.1uF
URSA_DQ[4]
M_SPI_CZ M_SPI_DO
R945
C917
W25X20AVSNIG
C924 1uF
10K R914
IC902
0.1uF
C958
0.1uF
0.1uF 0.1uF 0.1uF 0.1uF
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
URSA_MCLKZ1
URSA_MCLK1
URSA_DQSB1
URSA_DQS1
URSA_DQSB0
URSA_DQS0
URSA_DQM0
URSA_DQM1
URSA_A[0-12]
URSA_MCLKE
URSA_BA0
URSA_BA1
URSA_WEZ
URSA_CASZ
URSA_RASZ
URSA_DQ[0-31]
BCM (BRAZIL VENUS)
PARK.S.W
LVDS / Mstar FRC
2008.10.15
7
15
DDR2 1.8V By CAP - Place these Caps near Memory +1.8V_MEMC
+1.8V_FRC_DDR +1.8V_FRC_DDR
+1.8V_FRC_DDR
C1021
0.1uF
0.1uF
0.1uF C1020
0.1uF C1019
0.1uF C1018
C1016
0.1uF C1017
0.1uF
0.1uF C1014
0.1uF C1015
0.1uF C1013
0.1uF C1012
10uF C1011
0.1uF C1010
0.1uF C1009
0.1uF C1008
0.1uF C1007
10uF C1006
10V
C1005
C1004
10uF
C1003
0.1uF
0.1uF
0.1uF
C1040
C1041
0.1uF
0.1uF
C1039
0.1uF
C1038
C1037
0.1uF
0.1uF
C1036
0.1uF C1024
10uF C1035
0.1uF
C1034
0.1uF
C1033
C1032
0.1uF
0.1uF
C1031
0.1uF
C1030
0.1uF
C1029
0.1uF
C1028
10uF
C1027
10V
C1026
C1025
10uF
0.1uF
C1042
0.1uF
0.1uF
C1045
0.1uF C1044
C1043
BLM18PG121SN1D L1002
PI Result
DDR_DQ[20]
DDR_DQ[18]
DQ2
H7
DDR_DQ[19]
DQ3
H3
DDR_DQ[20]
DQ4
H1
DDR_DQ[21]
DQ5
H9
DDR_DQ[22]
DQ6
F1
DDR_DQ[23]
DQ7
F9
DDR_DQ[24]
DQ8
C8
DDR_DQ[25]
DQ9
C2
DDR_DQ[16]
DDR_DQ[26]
DQ10
D7
DDR_DQ[18]
DDR_DQ[27]
DQ11
D3
DDR_DQ[21]
DDR_DQ[28]
DQ12
D1
DDR_DQ[29]
DQ13
DDR_DQ[26] DDR_DQ[29] AR1001
URSA_DQ[23] URSA_DQ[16] URSA_DQ[18]
G2
DDR_DQ[31]
56
DDR_DQ[23]
1K
1000pF
0.1uF C1023
1K C1022
1K 1%
R1003
DDR_DQ[13]
URSA_DQ[13] AR1017
DDR_DQ[0]
56
D9
DDR_DQ[30]
DQ14
B1
DDR_DQ[31]
DQ15
B9
+1.8V_FRC_DDR
J2
VREF
VREF
M8
A0
DDRB_A[0]
M3
A1
DDRB_A[1]
M7
A2
DDRB_A[2]
N2
A3
DDRB_A[3]
N8
A4
DDRB_A[4]
N3
A5
DDRB_A[5]
N7
A6
DDRB_A[6]
P2
A7
DDRB_A[7]
P8
A8
P3
A9
M2
A10/AP
DDRB_A[10]
P7
A11
DDRB_A[11]
R2
A12
DDRB_A[12]
L2
BA0
L3
BA1
DDRB_A[8]
DDRB_A[10]
AR1005
DDRB_A[1]
22
URSA_A[10]
A1
VDD4
E1
VDD3
J9
J8
CK
VDD2
M9
K8
CK
VDD1
R1
K2
CKE
K9
ODT
VDDQ10
A9
L8
CS
VDDQ9
C1
K7
RAS
VDDQ8
C3
L7
CAS
VDDQ7
C7
K3
WE
22
DDRB_A[12]
AR1006
DDRB_A[7]
22
DDRA_A[9]
URSA_A[12] AR1013
URSA_A[12]
URSA_A[7]
URSA_A[5]
URSA_A[5]
DDRA_A[5]
DDRB_A[0]
URSA_A[0]
URSA_A[2]
DDRA_A[2]
DDRB_A[2]
AR1007
URSA_A[2]
URSA_A[0]
AR1014
DDRA_A[0]
DDRB_A[4]
22
URSA_A[4]
URSA_A[6]
22
DDRA_A[6]
URSA_A[6]
URSA_A[4]
URSA_RASZ
B_URSA_RASZ
R1005
AR1011
URSA_CASZ URSA_A[8]
22
URSA_MCLK
URSA_MCLKZ
7:B3
DDRA_A[11]
22
URSA_ODT
R1015
URSA_ODT
7:B3;Q15
R17
A2
M7
DDRA_A[3]
A3
N2
DDRA_A[4]
A4
N8
DDRA_A[5]
A5
N3
DDRA_A[6]
A6
N7
A7
P2
A8
P8
A9
P3
DDRA_A[10]
A10/AP
M2
DDRA_A[11]
A11
P7
DDRA_A[12]
A12
R2
A_URSA_BA1 22
22
A_URSA_MCLKE
U10
7:B3;X15
B_URSA_RASZ
R1014
URSA_MCLKZ1
7:G1
DDRA_A[2]
A_URSA_BA0 R1013
URSA_MCLK1
T11
M3
A_URSA_CASZ DDRA_A[8]
22
7:G1
M8
A1
DDRA_A[9]
A_URSA_RASZ
URSA_A[11]
7:B3
A0
DDRA_A[1]
DDRA_A[8]
22 22
DDRA_A[0]
DDRA_A[7]
DDRA_A[4]
URSA_RASZ
URSA_CASZ URSA_A[11] URSA_A[8]
DDRB_A[8]
B_URSA_MCLKE
R1006
DDRA_A[7]
22
AR1008
B_URSA_BA1 R1004
DDRA_A[12]
URSA_A[7]
DDRB_A[5]
DDRB_A[6]
B_URSA_BA0
DDRA_A[3] DDRA_A[1] DDRA_A[10]
URSA_A[9]
URSA_A[9]
B_URSA_CASZ DDRB_A[11]
VDD5
AR1012
URSA_A[3]
DDRB_A[3] DDRB_A[9]
DDRB_A[9]
URSA_A[3] URSA_A[1] URSA_A[10]
URSA_A[1]
J2
X17
A_URSA_RASZ
B_URSA_CASZ
R17
X17
A_URSA_CASZ
B_URSA_WEZ
T11
U10
A_URSA_WEZ
22
BA0
L2
BA1
L3
CK
J8
CK
G8
DQ0
DDR_DQ[0]
G2
DQ1
DDR_DQ[1]
H7
DQ2
DDR_DQ[2]
H3
DQ3
DDR_DQ[3]
H1
DQ4
DDR_DQ[4]
H9
DQ5
DDR_DQ[5]
F1
DQ6
DDR_DQ[6]
F9
DQ7
DDR_DQ[7]
C8
DQ8
DDR_DQ[8]
C2
DQ9
DDR_DQ[9]
D7
DQ10
D3
DQ11
DDR_DQ[11]
D1
DQ12
DDR_DQ[12]
D9
DQ13
DDR_DQ[13]
B1
DQ14
DDR_DQ[14]
B9
DQ15
DDR_DQ[15]
A1
VDD5
E1
VDD4
J9
VDD3
K8
M9
VDD2
CKE
K2
R1
VDD1
ODT
K9
CS
L8
A9
VDDQ10
RAS
K7
C1
VDDQ9
CAS
L7
C3
VDDQ8
WE
K3
C7
VDDQ7
C9
C9
VDDQ6
VDDQ5
E9
E9
VDDQ5
VDDQ4
G1
G1
VDDQ4
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
VDDQ3
G3
VDDQ2
G7
VDDQ1
G9
LDQS
R1007
56
B7
UDQS
R1008
56
F3
LDM
B3
UDM
R1009 R1010
56 56
VSS5
A3
E8
LDQS
R1011
56
VSS4
E3
A8
UDQS
R1012
56
VSS3
J3
VSS2
N1
VSS1
P9
VSSQ10
B2
VSSQ9
B8
VSSQ8
A7
VSSQ7
D2
VSSQ6
D8
VSSQ5
E7
VSSQ4
L1
URSA_DQS2
NC5
R7
NC6
A2
NC1
E2
NC2
R8
NC3
URSA_DQS3
7:B4
7:F1
URSA_DQS1
URSA_DQM2
7:B4
7:F1
URSA_DQM0
7:B4
7:F1
URSA_DQM1
URSA_DQSB2
7:B4
7:F1
URSA_DQSB0
URSA_DQSB3
7:B4
7:F1
URSA_DQSB1
URSA_DQM3
F8
VSSQ2
H2
VSSQ1
H8
56
LDQS
F7
R1017
56
UDQS
B7
R1018
56
LDM
F3
R1019
56
UDM
B3
R1020
56
LDQS
E8
A3
VSS5
R1021
56
UDQS
A8
E3
VSS4
J3
VSS3
N1
VSS2
P9
VSS1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
NC4
B_URSA_BA0
URSA_BA0
B_URSA_BA1 Q16
B_URSA_MCLKE
Q14
B_URSA_WEZ
NC5
R3
NC6
R7
NC1
A2
NC2
E2
NC3
R8
URSA_BA1
7:D1;T10
URSA_MCLKE
7:E1;T10
URSA_WEZ
7:D1;T10
22
7:D1;U12
URSA_BA0
A_URSA_BA0
7:D1;U12
URSA_BA1
A_URSA_BA1
7:E1;U11 VSSDL
7:D1;U11
URSA_MCLKE URSA_WEZ
L1
7:D1;T11
AR1010 +1.8V_FRC_DDR
J1
R1016
AR1009
AA17 +1.8V_FRC_DDR
AA17
A_URSA_MCLKE
Z16
A_URSA_WEZ
X14
22
F2
VSSQ3
URSA_DQS0
7:F1
NC4
R3
J7
7:B4
D8 VSSDL
VDDL
VDDL
J7
J1
URSA_DQ[11] 56
URSA_DQ[12] URSA_DQ[9]
DDR_DQ[14]
URSA_DQ[14] AR1015
URSA_DQ[6] 56
URSA_DQ[1]
DDR_DQ[3]
URSA_DQ[3]
DDR_DQ[4]
URSA_DQ[4]
+1.8V_FRC_DDR
VDDQ6
F7
DDR_DQ[10]
DDR_DQ[12]
DDR_DQ[1]
URSA_DQ[7] URSA_DQ[0] URSA_DQ[2]
AR1016
DDR_DQ[9]
DDR_DQ[6]
7:G1;C22
URSA_DQ[5]
DDR_DQ[5] DDR_DQ[11]
URSA_DQ[0-31]
URSA_DQ[8] URSA_DQ[10]
DDR_DQ[7]
DDR_DQ[0-15]
56
URSA_DQ[29]
URSA_DQ[21]
G8
DQ1
DDR_DQ[24]
URSA_DQ[24] URSA_DQ[26]
DQ0
DDR_DQ[17]
150
AR1002
URSA_DQ[31]
DDR_DQ[16]
DDR_DQ[19]
R1024 OPT
URSA_DQ[20]
DDR_DQ[17]
DDRA_A[0-12]
56
URSA_DQ[15] 56
DDR_DQ[10]
DDR_DQ[2]
DDRB_A[0-12]
URSA_DQ[17]
IC1002 H5PS5162FFR-S6C
DDR_DQ[22]
150
AR1003
URSA_DQ[22] URSA_DQ[19]
IC1001 H5PS5162FFR-S6C
DDR_DQ[25] DDR_DQ[30]
OPT R1001
56
URSA_DQ[30]
DDR_DQ[16-31]
URSA_DQ[25]
0.1uF
DDR_DQ[28]
URSA_DQ[28]
C1001
DDR_DQ[27]
1000pF C1002
AR1004
AR1018 DDR_DQ[15] DDR_DQ[8]
R1023
7:G1;AM22
URSA_DQ[27]
R1022
URSA_A[0-12]
URSA_DQ[0-31]
+1.8V_FRC_DDR
1K 1%
R1002
+1.8V_FRC_DDR
VSSQ6
E7
VSSQ5
F2
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
resonance Compensation
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
0.1uF
C1053
0.1uF
0.1uF C1051
0.1uF C1052
C1049
0.1uF C1050
0.1uF
C1048
0.1uF
+1.8V_FRC_DDR
C1047
0.1uF
C1046
+1.8V_MEMC
BCM (BRAZIL VENUS)
HONG.Y.H
M-STAR FRC DDR
08.10.15
8
15
RESET
Hot Plug input pin should be feeded over 5mA. BCM Recommend
IC100 BCM3556
D3.3V P100 D3.3V
GIL-G-06-S3T2
2
BCM_AVC_DEBUG_RX1
3
H23
2
F26 H28 J26
G
H27
4
C400 10uF G5
5
BCM_AVC_DEBUG_TX2
R116
G26 J27 J28 F27
G5
G24
6
BCM_AVC_DEBUG_RX2
R117 33
H26 G27 G28 K23 G25
NAND_IO[0-7]
EBI_ADDR0
GPIO_04
EBI_ADDR5
GPIO_05
EBI_ADDR6
GPIO_06
EBI_ADDR8
GPIO_07
EBI_ADDR9
GPIO_08
EBI_ADDR13
GPIO_09
EBI_ADDR12
GPIO_10
EBI_ADDR11
GPIO_11
EBI_ADDR10
GPIO_12
EBI_ADDR7
GPIO_13
EBI_TAB
GPIO_14
EBI_WE1B
GPIO_15
EBI_CLK_IN
GPIO_16
EBI_CLK_OUT
GPIO_17
EBI_RWB
GPIO_18
EBI_CS0B
GPIO_19 GPIO_20
4.7K
4.7K R194
R192
R193
NAND_IO[0]
U24
NAND_IO[1]
T26
NAND_IO[2]
T27
NAND_IO[3]
U26
NAND_IO[4]
U27
NAND_IO[5]
V26
NAND_IO[6]
V27
NAND_IO[7]
V28
C3
NAND_CEb
T24
C2
NAND_ALE
R23
C3
NAND_REb
T23
C2
NAND_CLE
T25
C2 C3
NAND_WEb
R24
NAND_RBb
U25
IC403 AT24C512BW-SH-T
7
3
6
4
5
GPIO_24
NAND_DATA3
GPIO_25
NAND_DATA4
GPIO_26
NAND_DATA5
GPIO_27
NAND_DATA6
GPIO_28
NAND_DATA7
GPIO_29
NAND_CS0B
GPIO_30
NAND_ALE
GPIO_31
NAND_REB
GPIO_32
NAND_CLE
GPIO_33
NAND_WEB
GPIO_34
NAND_RBB
GPIO_35 GPIO_37
W24 V23
VCC
V24
C416 0.1uF
WP
SF_MISO
GPIO_38
SF_MOSI
GPIO_39
SF_SCK
GPIO_40
SF_CSB
GPIO_41 GPIO_42 GPIO_43
SCL
R411 22
SDA
R412 22
GPIO_44 SCL2_3.3V
GPIO_45
I4;12:F3
GPIO_46 GND
GPIO_47 SDA2_3.3V
I4;12:F3
GPIO_48 GPIO_49 GPIO_50 GPIO_51 GPIO_52 GPIO_53 GPIO_54 GPIO_55 GPIO_56 GPIO_57 SGPIO_00 SGPIO_01 SGPIO_02 SGPIO_03 SGPIO_04 SGPIO_05
* NAND FLASH MEMORY 1Gbit (128M)
Boot Strap D3.3V
100
AA26
AMP_RST VREG_CTRL PWM_DIM
I3;4:A5;7:I5
GAIN_SWITCH
L1
14:A6
DSUB_DET
L3
OPT
L2
0
R189
Y25
BCM_RX
Y26
BCM_TX
M27 AA25
RF_SWITCH
R25 N28
14:A6
SIDE_CVBS_DET
N27
R105 22
AH18 P23
0
M23
AUDIO_M_CLK
R195 OPT
AD19
100
R2008
A_DIM
3:C4 I3;4:A6
AE19 M4 M5
R2018 OPT 100
L23
R3030
OPT
100
Y28 Y27 G2
SF_SCK
0
R198
OPT
G3
SF_MISO
0
R196
OPT
G5
SF_MOSI
0
R197
OPT
G6
SF_CSB
0
R109
OPT
G4 L24
R161
0
P25 L5
R103
100
BIT_SEL LVDS_SEL BCM_AVC_DEBUG_TX1
C7
BCM_AVC_DEBUG_RX1
C7
AV1_CVBS_DET BLUETOOTH_RESET FRC_RESET
K4
14:A5 I3;14:I3 7:H2
K1 L27
BCM_AVC_DEBUG_RX2
M26
BCM_AVC_DEBUG_TX2
N23
C6 C7
R28 R27 R26 P28 P27 K6 K5
22
R2024
P26
22 22
R160
M3
DDC_SCL
I3;14:A6
DDC_SDA
I3;14:A6
D3.3V
R102
M2 M1 L4 L6 W27
HDMI_HPD_IN COMP1_DET
14:A6
COMP2_DET
14:A5 22
R186
W28
22
R174
W26
22
R175
W25
22
R178
J2
22
R179
J1
22
R181
K3
22
R182
K2
22
SGPIO_07
SCL0_3.3V
3:D3;2:AH5
SDA1_3.3V
3:D3;2:AH5 B5;12:F3 B5;12:F3
SCL3_3.3V
7:B6
SDA3_3.3V
7:B6
NC_3
R2040
NC_5
E5
NAND_RBb
E6
NAND_REb
E6
NAND_CEb
RB
Open Drain
E
OPT
NC_7 C3024 4700pF C114 0.1uF
R2030 2.7K
R321 2.7K
R
NC_8 VDD_1 VSS_1 NC_9 NC_10
E5 IF FUNDMENTAL IS USED => LOW IF DIP IS USED => HIGH
E6
CL
NAND_CLE
AL
NAND_ALE E5
W
NAND_WEb D3.3V
NAND_IO[1] : NAND Block 0 Write (DNS) 0 : Enable Block 0 Write 1 : Disable Block 0 Write NAND_IO[3:2] : NAND ECC (10) 00 : No ECC 01 : 1 ECC Bit 10 : 4 ECC Bit 11 : 8 ECC Bit
WP
4.7K
R136
NC_11 NC_12 NC_13 NC_14
C FLASH_WP_1
Q101 KRC103S
B
NC_15
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
NC_29
* I2C_0 : TUNER
NC_28
* I2C_1 : Audio amp, HDMI S/W
NC_27
G6;4:A6
PWM_DIM
BLUETOOTH_RESET
NAND_IO[0-7]
NC_26
A_DIM
G7;4:A5;7:I5
* I2C_2 : NVRAM,Micom
I/O7
NAND_IO[7]
I/O6
NAND_IO[6]
G7;12:I4;3:C5
* I2C_3 : FRC
I/O5
NAND_IO[5]
I/O4
NAND_IO[4]
AMP_RST VREG_CTRL HDMI_HPD_IN
G7;14:A6
TUNER_RESETb
NC_25 NC_24 D3.3V NC_23
C136
10uF 6.3V
VDD_2 VSS_2
C115 0.1uF
NC_22
NAND_IO[0-7]
2.7K
2.7K
NC_2
NC_4 R191
R2032 2.7K
OPT 2.7K
R317
OPT
R2029 2.7K R2033 2.7K R315
2.7K
E3;E6
OPT
14:A6
SCL1_3.3V
SDA2_3.3V
R185
14:A6
SDA0_3.3V
SCL2_3.3V
* I2C MAP NC_1
D3.3V
E3;E6 NAND_IO[6]
NAND_IO[5] R2031 2.7K
R2004
R2009
AA28
IC101 NAND01GW3A2CN6E
NAND_IO[2] E3;E6
D3.3V
NAND_IO[0] : Flash Select (1) 0 : Boot From Serial Flash 1 : Boot From NAND Flash
100
AA27
D3.3V
NC_6
NAND_IO[4] E3;E6
K25
D3.3V
2.7K
R316
2.7K
R314
E3;E6 NAND_IO[3]
E3;E6
100 OPT R2005
K26
D3.3V
D3.3V
NAND_IO[0]
SGPIO_06
OPT
OPT
2.7K
2
NAND_DATA2
K24
R131
A2
8
GPIO_23
22 22
R2001 R2002
K28
OPT
R2010 2.7K
A1 R3016 4.7K
1
GPIO_22
NAND_DATA1
GPIO_36
U23 A0
GPIO_21 NAND_DATA0
K27
I3;14:A6
22
R199
R2016 2.7K
4.7K
4.7K
R422
R419
NVRAM
D3.3V
4.7K
D3.3V
L25
R2015 2.7K
10:I2;12:I5
G6
D3.3V
TUNER_RESETb
N25
4.7K R170
BCM_AVC_DEBUG_TX1
L26
4.7K R171
SYS_RESETb 10:E4
GPIO_03
4.7K R176
O
GPIO_02
EBI_ADDR1
R2014 2.7K
3
EBI_ADDR2
R2013 2.7K
1
4.7K
I
GPIO_01
4.7K R177
G6
J25
R408 330 RESET
GPIO_00
EBI_ADDR4
4.7K R180
H24
EBI_ADDR3
R2011 2.7K
IC400 KIA7029AF
H25
4.7K R183
J24 1 R410 10K
R409 910
POWER_DET 12:B3;12:I4
N26
J23
OPT OPT
4.7K R184
R2003 0 R2025 0
4.7K R187
D3.3V
NC_21 NC_20 I/O3
NAND_IO[3]
I/O2
NAND_IO[2]
I/O1
NAND_IO[1]
I/O0
NAND_IO[0]
NC_19 NC_18 NC_17 NC_16
E
NAND_IO[4] : CPU Endian (0) 0 : Little Endian 1 : Big Endian NAND_IO[6:5] : Xtal Bias Control (1, DNS) 00 : 1.2mA 01 : 1.8mA 10 : 2.4mA (Recommand) 11 : 3.0mA
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM (BRAZIL VENUS)
2008.10.15
JANG.J.H BCM3556 & NAND FLASH
9
15
When usding FUNDMENTAl then series R = 0 ohm and CL = 8 pF
IC100 BCM3556
54MHz X-TAL
D23
B4
D24 C25 E27 E26 D28 D27 D26 E23 E24 F25 C27 C26 B28 B27 A27 F24 F23 E25 C28
POD2CHIP_MDI2
LVDS_TX_0_CLK_N
POD2CHIP_MDI3
LVDS_TX_1_DATA0_P
POD2CHIP_MDI4
LVDS_TX_1_DATA0_N
POD2CHIP_MDI5
LVDS_TX_1_DATA1_P
POD2CHIP_MDI6
LVDS_TX_1_DATA1_N
POD2CHIP_MDI7
LVDS_TX_1_DATA2_P
POD2CHIP_MISTRT
LVDS_TX_1_DATA2_N
POD2CHIP_MIVAL
LVDS_TX_1_DATA3_P
CHIP2POD_MCLKO
LVDS_TX_1_DATA3_N
CHIP2POD_MDO0
LVDS_TX_1_DATA4_P
CHIP2POD_MDO1
LVDS_TX_1_DATA4_N
CHIP2POD_MDO2
LVDS_TX_1_CLK_P
CHIP2POD_MDO3
LVDS_TX_1_CLK_N
CHIP2POD_MDO4
LVDS_PLL_VREG
CHIP2POD_MDO5
LVDS_TX_AVDDC1P2
CHIP2POD_MDO6
LVDS_TX_AVDD2P5_1
CHIP2POD_MDO7
LVDS_TX_AVDD2P5_2 LVDS_TX_AVSS_1
CHIP2POD_MOVAL
LVDS_TX_AVSS_2
0
CHIP2POD_MOSTRT
AG21
VDAC_AVDD2P5
LVDS_TX_AVSS_5
VDAC_AVDD1P2
LVDS_TX_AVSS_6
VDAC_AVDD3P3_1
LVDS_TX_AVSS_7
VDAC_AVDD3P3_2
LVDS_TX_AVSS_8 LVDS_TX_AVSS_9 LVDS_TX_AVSS_10
AF19 VDAC_AVSS_1
AD20
VDAC_AVSS_3
AH20 AG19
CLK54_AVDD1P2
VDAC_1
CLK54_AVDD2P5
VDAC_2
CLK54_AVSS CLK54_XTAL_N CLK54_XTAL_P CLK54_MONITOR
BSC_S_SDA VCXO_AGND_2 USB_AVSS_1
T6 R7 A1.2V
T7
A2.5V
The INCM trace ends at the same point where the connector ground connects to the board ground (thru-hole connector pin).
4.7uF
0.1uF
0.1uF
0.1uF
0.1uF
U1 U2 T5
C209
C208
C207
C203
C202
V2
USB_DP2
D3.3V R210 120
V1
USB_DP1 USB_DM2
2.7K
R2 T2
USB_CTL1
RESETB NMIB
USB_AVDD2P5REF
TMODE_0
USB_AVDD3P3
TMODE_1
USB_RREF
TMODE_2
USB_DM1
TMODE_3
USB_DP1
SPI_S_MISO
USB_DM2
POR_OTP_VDD2P5
USB_DP2
POR_VDD1P2
T1
EJTAG_TCK
USB_PWRFLT_1
EJTAG_TDI
USB_PWRFLT_2
EJTAG_TDO
USB_PWRON_1
EJTAG_TMS
USB_PWRON_2
EJTAG_TRSTB EJTAG_CE0
R218 240
P5
EPHY_RDAC
P2 A2.5V
N3 N2 P1 P4 N4
PLL_MAIN_AVDD1P2
EPHY_RDP
PLL_MAIN_AGND
EPHY_TDN
PLL_MAIN_MIPS_EREF_TESTOUT
EPHY_TDP
PLL_RAP_AVD_TESTOUT
EPHY_AVDD1P2
PLL_RAP_AVD_AVDD1P2
EPHY_AVDD2P5
PLL_RAP_AVD_AGND
EPHY_AGND_2
P7
EPHY_AGND_3
14:A5
AV1_R_IN
14:A5 14:A6
AV1_INCM COMP1_L_IN
14:A6
COMP1_R_IN
14:A6 14:A5
COMP1_INCM COMP2_L_IN
14:A5
COMP2_R_IN
14:A5 14:A4
COMP2_INCM SIDE_L_IN
14:A4
SIDE_R_IN
14:A4
SIDE_INCM PC_L_IN
0.015uF
C210
0.015uF
AD7
R215
51
C211
0.015uF
AH4
R228
51
C232
0.015uF
BYP_DS_CLK
AG5
R229
51
C220
0.015uF
AG6
R230
51
C221
0.015uF
AF7
51
C224
0.015uF
AH5
R232
51
C225
0.015uF
AG7
R233
51
C226
0.015uF
AD8
R234
51
C227
0.015uF
AF8
AUDMX_INCM2
E6 D7 E7 F7 G7 A1.2V
H7
A2.5V
AD28 AD26 AC26 AC27 AE25
54MHz_XTAL_N
I2
54MHz_XTAL_P
I2
Y23
A1.2V
AB24 AC24
L203 BLM18PG121SN1D
AF25 AF24
C233 0.1uF
C235 4.7uF
F6
SYS_RESETb 4.7K
N24
A2.5V
J4 J6 J3 V25 AH3
9:B7
R221
J5
L201 BLM18PG121SN1D C231 10uF
A1.2V
C234 0.1uF
AB8 D3.3V H3
OPT R224 4.7K
H2 H1
OPT R225 4.7K
G1 H6
CONNECT NEAR BCM CHIP
H5 A1.2V L204 BLM18PG121SN1D
AC25 AB27 M6 N6
R226 4.7K
R227 4.7K
INCM
R240 A1.2V L207 BLM18PG121SN1D
390 OPT
N7
C4001
0.1uF
TU_CVBS_INCM 3:T25
5.1 R4009
C4002
Y24 AE24
1K
R222
AD25
1K
R223
0.1uF
SIDE_CVBS_INCM 3:T19
0.15uF C4010
SIDE_INCM 3:T18 0.47uF C4014
5.1 AV1_INCM 3:T20 R4011
C4003
0.1uF
0.15uF C4011
0.47uF C4015
AV1_CVBS_INCM 3:T19 5.1 R4012
0.15uF C4008
COMP1_INCM 3:T24 C4016 0.47uF
AUDMX_INCM4 C4004
AUDMX_LEFT5
0.1uF
COMP1_VID_INCM 3:T23
AUDMX_RIGHT5
5.1 R4010
AUDMX_INCM5 AUDMX_LEFT6 AUDMX_RIGHT6 AUDMX_INCM6 AUDMX_AVSS_1
C4005
0.1uF
C4000
0.1uF
C4006
0.1uF
C4007
0.1uF
R4008
AUDMX_AVSS_4 AUDMX_AVSS_5
AB11
COMP2_INCM 3:T22 0.47uF C4013
5.1
AUDMX_AVSS_3
AA11
0.15uF C4009
COMP2_VID_INCM 3:T21
AUDMX_AVSS_2
AB10
R_VID_INCM 3:T15
0.15uF C4012
PC_INCM 3:T14 0.47uF C4017
AUDMX_AVSS_6
AC8
AUDMX_LDO_CAP
AE5
AUDMX_AVDD2P5
R4002 34
C2010 0.047uF
C2009 0.047uF
C2008 0.047uF
C2007 0.047uF
0.047uF
0.047uF
0.047uF C299
C298
C296
0.047uF C279
0.047uF C277
E5
AUDMX_RIGHT4
AB9
C260
A5
AUDMX_LEFT4
AA10
C222 0.1uF
C4
AUDMX_INCM3
AF5 0.015uF
F3
AUDMX_RIGHT3
AG8
0.047uF
R203 51
C1
AUDMX_LEFT3
AH8
C205
SPK_P SPK_INCM
AUDMX_RIGHT2
AH7
C274
14:D5
F2
AUDMX_LEFT2
AE8 OPT 0.015uF C204
12pF C229
A1.2V A2.5V
AUDMX_INCM1
AH6
PC_INCM
7:E7
AUDMX_RIGHT1
AE7 R231
7:E7
LVDS_TX_0_CLK_P
AUDMX_LEFT1
AG4
51 R202 OPT
14:F4
BYP_SYS175_CLK
AF6
0.047uF
14:A3
PC_R_IN
C206
51
0.047uF
14:A3
51
R214
C273
14:A3
R204
LVDS_TX_0_CLK_N
22 R211
AA24 BYP_CPU_CLK BYP_SYS216_CLK
AV1_L_IN
7:E7
AB26
EPHY_RDN
EPHY_AGND_1
N5
14:A5
7:E7
LVDS_TX_0_DATA0_P
F4
EPHY_PLL_VDD1P2
N1
AE6
7:E7
LVDS_TX_0_DATA0_N
EPHY_VREF
P3
A1.2V
7:E7
LVDS_TX_0_DATA1_P
EJTAG_CE1
P6 1K R219
7:E7
LVDS_TX_0_DATA1_N
H4
USB_MONPLL
R1
USB_OCD1
R235
7:E7
LVDS_TX_0_DATA2_P
D3.3V RESET_OUTB
USB_MONCDR
R5
Place test points, resistors near audio connector. Connect the other side of the resistor to GND as close as possible to the ground connection of the associated audio connector.
F1
OPT
C228 10uF
7:E7
LVDS_TX_0_DATA2_N
P24
USB_AVDD2P5
T3 U4
R209 3.9K
VCXO_PLL_AUDIO_TESTOUT
USB_AVDD1P2PLL
T4 R4
C201 100pF
VCXO_AVDD1P2
USB_AVSS_3
USB_AVDD1P2
U3
USB_DM1
VCXO_AGND_3
USB_AVSS_2
USB_AVSS_5
R3
Route INCM between associated left and right signals of same channel
F5
LVDS_TX_0_DATA3_P
54MHz_XTAL_P
USB_AVSS_4
T8
L200 BLM18PG121SN1D
D4
7:E7
AA23 VCXO_AGND_1
A3.3V
D3
LVDS_TX_0_DATA3_N
54MHz_XTAL_N
BSC_S_SCL
3
4
E4
7:E7
R4006 34
R6
E3
7:E7
LVDS_TX_0_DATA4_P
R4007 34
JP203
E2
7:D7
LVDS_TX_0_DATA4_N
R4004 34
M24
E1
7:D7
LVDS_TX_1_CLK_P
PM_OVERRIDE
M25
JP202
D2
AD27
VDAC_RBIAS
VDAC_VREG
2
D1
LVDS_TX_AVSS_11
AH21
R242 0 OPT
C3
7:D7
LVDS_TX_1_CLK_N
R4005 34
R201 1.5K
R200 1.5K
JP201
C200 4.7uF
1
MNT OUT FOR BCM
C2
VDAC_AVSS_2
AE20 560AH22
R241 0 OPT
C213 0.01uF
JP200
B2
7:D7
LVDS_TX_1_DATA0_P
R4000 34
TJC2508-4A
R220
B1
7:D7
LVDS_TX_1_DATA0_N
R4001 34
R220 : BCM recommened resistor 562 ohm C215 0.1uF
P200
B5
7:D7
LVDS_TX_1_DATA1_P
R4003 34
D3.3V
C5
7:D7
LVDS_TX_1_DATA1_N
2
LVDS_TX_0_CLK_P
LVDS_TX_AVSS_4
C223
0.1uF
0.1uF
C219
0.1uF
C214
4.7uF
POD2CHIP_MDI1
AC18 AG20
C212
LVDS_TX_0_DATA4_N
LVDS_TX_AVSS_3
AF20
BROAD BAND STUDIO
POD2CHIP_MDI0
D6
LVDS_TX_1_DATA2_P
4.7uF
L202 BLM18PG121SN1D
R237
R236
0
A28
LVDS_TX_0_DATA4_P
D5
0.1uF C240
A3.3V A1.2V A2.5V
POD2CHIP_MCLKI
A2
3
D25
A1
C230 12pF
22 R212
X903 54MHz
LVDS_TX_0_DATA3_N
7:D7
1
LVDS_TX_0_DATA3_P
7:D7
LVDS_TX_1_DATA2_N
C3012
LVDS_TX_0_DATA2_N
7:D7
LVDS_TX_1_DATA3_P
L8014
RMX0_SYNC
G23
A3
7:D7
LVDS_TX_1_DATA3_N
1008LS-272XJLC 33pF
LVDS_TX_0_DATA2_P
B3
7:D7
LVDS_TX_1_DATA4_P
R3027 604
RMX0_DATA
B6
LVDS_TX_1_DATA4_N
0.1uF
LVDS_TX_0_DATA1_N
C6
C2002
JP209
RMX0_CLK
A4
C237
A26
LVDS_TX_0_DATA1_P
4.7uF
JP208
LVDS_TX_0_DATA0_N
PKT0_SYNC
C236 0.1uF
B25
LVDS_TX_0_DATA0_P
PKT0_DATA
C239 0.1uF C242 4.7uF C295 0.1uF C2000 4.7uF
A25
JP207
PKT0_CLK
C2001 0.1uF
B26
JP206
C241
C24
JP205
0.1uF
JP204
TU_SYNC
C238
TU_SCLK TU_SDATA
When usding Dip-type X-tal then series R = 22 ohm and CL = 12 pF
G_VID_INCM 3:T15 B_VID_INCM 3:T15
A2.5V
C217 10uF
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM (BRAZIL VENUS)
JANG.J.H
BCM3556 AUD_IN/LVDS
2008.10.15
10
15
IC100 BCM3556
AB19 AB25
C122 4.7uF
EDSAFE_AVDD2P5
AUD_LEFT0_P
EDSAFE_DVDD1P2
AUD_AVDD2P5_0
EDSAFE_IF_N
AUD_AVSS_0_1
EDSAFE_IF_P
AUD_AVSS_0_2
PLL_DS_AGND
AUD_AVSS_0_3
PLL_DS_AVDD1P2
AUD_AVSS_0_4
PLL_DS_TESTOUT
AUD_AVSS_0_5 AUD_RIGHT0_N
A2.5V
AUD_RIGHT0_P
AB18 BLM18PG121SN1D
C112 0.1uF
C111 0.1uF
AC17 AB17
C123 0.01uF
L104 C120 1000pF BLM18PG121SN1D
AD14 AD16 AB15
L105 C117 1000pF
AC15 AD13
C118 0.01uF
AE13 AC13 AB14 AC14
14:A4
DSUB_R
AC12
14:A4
R_VID_INCM DSUB_G
AD12 AA14
14:A3
G_VID_INCM DSUB_B
14:A3
B_VID_INCM
AD11
14:A4 14:A3
AB13 AC11
10pF
C103
10pF R119 75
C102
10pF R118 75
C101
R115
C127
0.1uF
C128
0.1uF
AD10 AC10 AE9 AF9
0.1uF
C129
R129 91
R120 91
14:A6 COMP1_VID_INCM
OPT
14:A6
COMP1_Pb_IN
10pF R127 91
COMP1_Y_IN COMP1_Pr_IN
C104
14:A6 14:A5
75
AB12
AH9 AG9
C130
0.1uF
AG15
C131
0.1uF
AE15
C132
0.1uF
AF15 AH15
COMP2_Y_IN
14:A5
COMP2_Pr_IN
14:A5
COMP2_Pb_IN
0.1uF
AG16
C134
0.1uF
AF16
C135
0.1uF
R143 R141
OPT 0 OPT 0
R140 91
R138 91
10pF
OPT C105
R135 91
R142
OPT R145
TU_CVBS_IN
14:A5 14:A5
AV1_CVBS_IN
34
R147 AG14 R148 AE14
OPT 0
R149 AF14
C126 OPT 0
0.1uF AH14
OPT 0
R151 AG10
R150 AH10
C107 0.1uF AE10 OPT 0 R154 AE11 OPT 0 R155 AF11
91
C108 0.1uF AH11 OPT 0 R156 AH13 OPT 0 R159 AE12
91 75
OPT C109 C110
OPT 14:A6
AH17 AH16
14:A5 COMP2_VID_INCM
OPT
14:A5
C133
SIDE_CVBS_IN
0.1uF 0.1uF
AF12 AD9
C124
0.1uF
AG11
C125
0.1uF
AG12 AF13
14:A6
TU_CVBS_INCM
AC9
14:A5
AV1_CVBS_INCM
AF10
14:A5
SIDE_CVBS_INCM
A2.5V
A2.5V
AH12 AG13 AF17
R137 10K
14:A6
TU_SIF
R128 0
R4020 10K
0.1uF C106
AG17 AD15 AE16
A1.2V L106 BLM18PG121SN1D
R3055 240
R139 12K
C121 0.1uF
C140 4.7uF
AE17 AB16 AA15 AC16
C4020 0.1uF
12K R4021
120 R3056
AG3 AF4
SD_V5_AVDD1P2 SD_V5_AVDD2P5
AUD_LEFT1_N AUD_LEFT1_P
SD_V5_AVSS
AUD_RIGHT1_N
SD_V1_AVDD1P2
AUD_RIGHT1_P
SD_V1_AVDD2P5
AUD_AVDD2P5_1
SD_V1_AVSS_1
AUD_AVSS_1_1
SD_V1_AVSS_2
AUD_AVSS_1_2
SD_V2_AVDD1P2
AUD_AVSS_1_3
SD_V2_AVDD2P5
AUD_LEFT2_N
SD_V2_AVSS_1
AUD_LEFT2_P
SD_V2_AVSS_2
AUD_RIGHT2_N
SD_V2_AVSS_3
AUD_RIGHT2_P
SD_V3_AVDD1P2
AUD_AVDD2P5_2
SD_V3_AVDD2P5
AUD_AVSS_2_1
SD_V3_AVSS_1
AUD_AVSS_2_2
SD_V3_AVSS_2
AUD_SPDIF
SD_V4_AVDD1P2
SPDIF_AVDD2P5
SD_V4_AVDD2P5
SPDIF_AVSS
SD_V4_AVSS
SPDIF_IN_N
SD_R
SPDIF_IN_P
SD_G
OPT
BCM_I2S_WORD_CLK
0
R165
HDMI_RX_0_CEC_DAT
SD_B
HDMI_RX_0_HTPLG_IN
SD_INCM_B
HDMI_RX_0_HTPLG_OUT
SD_Y1
HDMI_RX_0_DDC_SCL
SD_PR1
HDMI_RX_0_DDC_SDA
SD_PB1
HDMI_RX_0_RESREF
SD_INCM_COMP1 SD_Y2
HDMI_RX_0_CLK_N HDMI_RX_0_CLK_P
SD_PR2
HDMI_RX_0_DATA0_N
SD_PB2
HDMI_RX_0_DATA0_P
SD_INCM_COMP2
HDMI_RX_0_DATA1_N
SD_Y3
HDMI_RX_0_DATA1_P
SD_PR3
HDMI_RX_0_DATA2_N
SD_PB3
HDMI_RX_0_DATA2_P
SD_INCM_COMP3
HDMI_RX_0_VDD3P3
SD_L1
HDMI_RX_0_VDD1P2
SD_C1
HDMI_RX_0_VDD2P5
SD_INCM_LC1
HDMI_RX_0_AVSS_1
SD_L2
HDMI_RX_0_AVSS_2
SD_C2
HDMI_RX_0_AVSS_3
SD_INCM_LC2
HDMI_RX_0_AVSS_4
SD_L3
HDMI_RX_0_AVSS_5
SD_C3
HDMI_RX_0_AVSS_6
SD_INCM_LC3
HDMI_RX_0_PLL_AVSS
SD_CVBS1
HDMI_RX_0_PLL_DVDD1P2
SD_CVBS2
HDMI_RX_0_PLL_DVSS
OPT
AF23 AA20 AB21
HDMI_RX_1_CEC_DAT
SD_INCM_CVBS2 HDMI_RX_1_HTPLG_IN SD_INCM_CVBS3 HDMI_RX_1_HTPLG_OUT
SD_INCM_CVBS4
HDMI_RX_1_DDC_SCL
SD_SIF1
HDMI_RX_1_DDC_SDA
SD_INCM_SIF1
HDMI_RX_1_RESREF
SD_FB
HDMI_RX_1_CLK_N
SD_FS
HDMI_RX_1_CLK_P
SD_FS2
HDMI_RX_1_DATA0_N HDMI_RX_1_DATA0_P PLL_VAFE_AVDD1P2 PLL_VAFE_AVSS HDMI_RX_1_DATA1_N HDMI_RX_1_DATA1_P PLL_VAFE_TESTOUT RGB_HSYNC HDMI_RX_1_DATA2_N RGB_VSYNC
HDMI_RX_1_DATA2_P HDMI_RX_1_VDD3P3 HDMI_RX_1_VDD1P2
14:A3
RGB_HSYNC
HDMI_RX_1_AVSS_2
14:A3
RGB_VSYNC
HDMI_RX_1_AVSS_3 HDMI_RX_1_AVSS_4 HDMI_RX_1_AVSS_5 HDMI_RX_1_AVSS_6 HDMI_RX_1_AVSS_7 HDMI_RX_1_AVSS_8 HDMI_RX_1_AVSS_9 HDMI_RX_1_PLL_AVSS HDMI_RX_1_PLL_DVDD1P2 HDMI_RX_1_PLL_DVSS
C155 0.1uF
C162 10uF
C148 0.01uF
C156 0.1uF
C163 10uF
AC23 AD23 AH25
R168
AG25 AH23
R166
AG23 AG24
0 OPT 0
OPT R167
AH24
0 OPT
AE22 AB20 AC21 AE23 AF21
R169
0
AE21
OPT R172
AF22 AG22
0 OPT
AD21 C149 0.01uF
AC20 AD22
C157 0.1uF
A2.5V
C164 10uF
AH2 SPDIF_OUT14:A3
AC6 AE4
C150 0.1uF
AF3
+5.0V
AH1
R2036 1K
AA5
R188
C HDMI_HPD_IN_5MA
10K
Y6 499
Q906 ISA1530AC1
G5
B
HDMI_HPD_IN
9:G4;9:I3
A2.5V
AB3 AC4
A2.5V
HDMI_HPD_IN_5MA
AA6 0
R157
0
R158
E
R152
AC1
HDMI_SCL
2:AA19
HDMI_SDA
2:AA19
HDMI0_RXC-_BCM
AC2 AD1 AD2 AE2 AF1 AF2 AD3
C3006 0.1uF 16V
2:AA18
HDMI0_RXC+_BCM
2:AB18
HDMI0_RX0-_BCM
2:AB18
HDMI0_RX0+_BCM
AE1
2:AB18
HDMI0_RX1-_BCM
2:AC18
HDMI0_RX1+_BCM
2:AC18
HDMI0_RX2-_BCM
2:AC18
HDMI0_RX2+_BCM
2:AD18
A3.3V
BLM18PG121SN1D L109 A1.2V
A2.5V
AE3 AC3 C145 4.7uF
AD4 AB5
C153 0.1uF
C160 0.1uF BLM18PG121SN1D L107
AB6 AG2 AB4 AA7 Y8
C158 1000pF
AC5
C151 0.01uF
C165 10uF
W8
AA3
SD_INCM_CVBS1
C147 0.01uF
AC22
SD_CVBS3 SD_CVBS4
3:D3 A2.5V
AH26
AG1
SD_INCM_G
HDMI_RX_1_AVSS_1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
AG26
SD_INCM_R
HDMI_RX_1_VDD2P5
CONNECT NEAR BCM CHIP
AG18
3:D3
270
C119 0.1uF
AD24
AUD_LEFT0_N
3:D3
BCM_I2S_DATA_OUT
0
470
BLM18PG121SN1D A1.2V
AE27
C144 0.1uF
I2S_LR_OUT
EDSAFE_AVSS_5
OPT R164
OPT R3041
C116 4.7uF
I2S_LR_IN
EDSAFE_AVSS_4
BCM_I2S_BIT_CLK 0
OPT
AE28 C113 0.1uF L103
A1.2V
EDSAFE_AVSS_3
AH19 AD18
0 OPT
R163
R3042
AE26
I2S_DATA_OUT
AD17
V4 U6 V5
10K
AG27
EDSAFE_AVSS_2
R162
AF18
R2039
AF28
I2S_DATA_IN
10K
AF27
A1.2V BLM18PG121SN1D L102
I2S_CLK_OUT
EDSAFE_AVSS_1
10K
AF26
I2S_CLK_IN
DS_AGCT_CTL
R146
AB22
A2.5V
AE18 DS_AGCI_CTL
R2038
AA21
R2037 OPT 10K
AH28
R2035 0
AG28
D3.3V
V3 W4
499
R153
W2 W3 Y1 Y2
A3.3V
AA2 AA1 AB1
BLM18PG121SN1D L110
Y3
A1.2V
AB2
A2.5V
Y4 W5 W1 U5 W6
C146 4.7uF
C154 0.1uF
C161 0.1uF BLM18PG121SN1D L108
U7 V7 W7 U8 V8 Y5 V6 AA4 Y7
C159 1000pF
C152 0.01uF
C166 10uF
BRAZIL VENUS
JANG.J.H.
BCM3556 VIDEO IN
2008. 10. 15
11
15
14:E5
4:C5 ERROR_OUT
LED_POWER_ON
14:E6
14:E5 LED_WARM_STBY
14:E7
UCOM_SDA_3.3V
9:A7;B3
UCOM_SCL_3.3V
POWER_DET
OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R435
R439
0
0
P5.3
+5.0V
R472 4.7K
6.8K
22 P6.4
P6.3
P6.2
P6.1
P6.0/CLKO1
VSS
P4.0/AD0
X1
OPT
R428
100 OPT
100
9:C1
9:G7;9:I3;3:C5
OPT
EDID_WP
14:A4
C GND
Q907 RT1N141C-T112-1
B
+3.3V_ST R459 4.7K
E
4.7K R455 4.7K
OPT R452 47K
GND R462 100 KEY2
14:E6
KEY1
14:E6
A2
VSS
0
0
R445
R446
4
5
OPT
6
22
22
SCL GND SDA
GND
1K R453
22 R443
3
C406 0.1uF WP 16V
C409 22pF 50V
GND OPT
100 R441
7
C408 22pF 50V
R436
2
VCC
R434
8
READY FO 1.2V BCM ENABLE
R483 0
R449 R450
C412 0.1uF
R447
OPC_EN
R486 0
100
OPT
C414 0.1uF 16V
C413 0.1uF
GND
7:I5
GND
P6.6
OPT
AMP_MUTE
3 1
34
P6.5
21
23 20
11 19
ISCL/P7.5
18
22
17
R425
16
P6.7
15
25 24
R429 OPT
R469
FLASH_WP_1
10
C3016 0.1uF 16V
9:A7
OPT
AMP_RST
ISDA/P3.4/T0
SCL2_3.3V
2
OPT
100
OPT
P5.2
9
P3.3/INT1
RESET
22
9:B5;9:I4
R487 100K OPT
A1
1
OPT
VCC
35
P7.2/HCLAMP
SDA2_3.3V
NCP803SN293 RESET
36
26
9:B5;9:I4
A0
R413
E
4.7K
8
OPT
IC1003
4.7K
2SC3052
OPT
R3024 0
E R480 2.2K OPT
R444
P7.1/VBLANK
X401 24MHz R415
1K Q404
R442
27
MTV416GMF
4:C5 4:C7;14:E5
RL_ON
100
R431
GND
4.7K
C
P5.1
7
P3.2/INT0
22
R456 100
R432 47K
OPT R3031 0 B
P5.0
HSDA1/P3.1/TXD
24LC16BT-I/SN
Q405 2SC3052
37
P4.1/AD1
C
B
VDD
P7.0/HBLANK
28
100 INV_ON/OFF
R467
R484 30K
R482 30K OPT
R3026 5.1K
OPT 15K
R477 6.8K
OPT
38
29
IC406
4:H1
PANEL_CTL
100
R468
6
+3.3V_ST
IC405
9:A7;I4
0
OPT R479
R476
R485 10K
POWER_DET
R478 10K
100
P5.7/CLKO2
3:E3
OPT R481
+12V
100
30
15K +3.3V_ST
R440
4
GND
+5.0V
R474
P5.6
5
OPT
R418 4.7K
POWER DETECT
P4.2/AD2
31
P4.3/AD3
R404 220
+5V_ST +24V
P1.0/ET2
3
RST
R424
OPT
UCOM_TX
39
P1.7/SOGI HSCL1/P3.0/RXD
4.7K
R423
UCOM_RX
40
R466
14
R405 220
41
R465OPT 100
P5.5
68K
R421
IR
42
P5.4
32
OPT
22
R420
43
33
2
X2
R3018 4.7K
22
R417
44 1
VSYNC/P1.6
13
DDC_SDA
14:I1
HSYNC/P1.5
12
9:G7;14:A4
R3017 4.7K
4.7K
DDC_SCL
14:H2
GND
HSCL2/P7.3
OPT
OPT
R402
R406 GND
14:A3;14:E6
0
C411 100uF 16V
16V
R461
0 R416
C410 0.1uF
R460
4.7K R427
R401 1K
GND
+3.3V_ST
R430 100
+3.3V_ST
9:G7;14:A4
100
+3.3V_ST
OPT M5V_ON R403
R471
GND
C403 0.1uF 16V
GND
GND
P1.1/DA0
GND
E
G
C402 0.1uF 16V
100
P1.4/DA3
C407 Q401 OPT OPT 2SC3875S(ALY)
2
HSDA2/P7.4
C B
O
3
R2023 33K
1
+3.3V_ST
R414 10K
R407 47K
KIA7029AF I
R470
R3010 6.8K
P1.2/DA1
IC402
R435 : READY FO 1.2V BCM ENABLE
R475 2K 100
R451
D3.3V
R464
2K
P1.3/DA2
+3.3V_ST
+3.3V_ST
R454
HDMI_CEC
2:AD26
1K
+3.3V_ST
BCM (BRAZIL VENUS)
LIM.K.R
MICOM
2008.10.15
12
15
D1.2V
C243 0.1uF
C249 4.7uF
C251 0.01uF
C250 1000pF
C253 10uF
C252 0.1uF
C254 10uF
C286 33uF
C287 33uF
IC100 BCM3556 D1.2V
D1.2V
IC100 BCM3556
AD5 AD6 J7 K7
H8 C244 1000pF
C246 0.01uF
C256 0.1uF
C258 4.7uF
C259 1000pF
C262 0.01uF
C265 0.1uF
C266 4.7uF
C288 1000pF
C290 0.01uF
J8 K8 L8 M8 N8 P8 R8 AA8
D3.3V
H9 H10 H11 H12
C245 4.7uF
C255 1000pF
C257 0.01uF
C264 1000pF
C263 4.7uF
C261 0.1uF
C267 0.01uF
C289 0.1uF
C291 10uF
H13 H14 H15 H16 H17 H18 H19 H21
D3.3V
J21 K21 L21 M21 C216 0.1uF
C268 1000pF
C269 0.01uF
C271 4.7uF
C270 0.1uF
C292 1000pF
C293 0.01uF
C294 0.1uF
N21 P21 R21 T21 A3.3V
U21 V21 W21
R205 20
D1.8V
Y21
VDDC_1
L7
VDDC_2
M7
VDDC_3
AB7
VDDC_4
AC7
VDDC_5
G8
VDDC_6
D9
VDDC_7
AA9
VDDC_8
G10
VDDC_9
A11
VDDC_10
L11
VDDC_11
M11
VDDC_12
N11
VDDC_13
P11
VDDC_14
R11
VDDC_15
T11
VDDC_16
U11
VDDC_17
V11
VDDC_18
D12
VDDC_19
G12
VDDC_20
L12
VDDC_21
M12
VDDC_22
N12
VDDC_23
P12
VDDC_24
R12
VDDC_25
T12
VDDC_26
U12
VDDC_27
V12
VDDC_28
L13
VDDC_29
M13
VDDC_30
N13
VDDC_31
P13
VDDC_32
R13
VDDC_33
T13 U13 V13
AH27 AGC_VDDO
D3.3V C247 0.1uF
C272 0.1uF
C276 0.1uF
C275 0.1uF
C278 4.7uF
C280 4.7uF
C297 4.7uF
C2003 0.1uF
C2004 33uF
L14 M14
AA12 AA13 AA18 AA19 E28 L28 U28 AB28
D1.8V
VDDO_1
N14
VDDO_2
P14
VDDO_3
R14
VDDO_4
T14
VDDO_5
U14
VDDO_6
V14
VDDO_7
L15
VDDO_8
M15
D1.8V
N15 P15
A9 G9 C248 1000pF
C281 1000pF
C282 1000pF
C283 1000pF
C284 0.01uF
C285 0.01uF
C2005 0.01uF
G11
C2006 0.01uF
G14
G13 A14 G15 G17 A19 G19
DDRV_1
R15
DDRV_2
T15
DDRV_3
U15
DDRV_4
V15
DDRV_5
A16
DDRV_6
G16
DDRV_7
L16
DDRV_8
M16
DDRV_9
N16
P16 DVSS_1
DVSS_62
DVSS_2
DVSS_63
DVSS_3
DVSS_64
DVSS_4
DVSS_65
DVSS_5
DVSS_66
DVSS_6
DVSS_67
DVSS_7
DVSS_68
DVSS_8
DVSS_69
DVSS_9
DVSS_70
DVSS_10
DVSS_71
DVSS_11
DVSS_72
DVSS_12
DVSS_73
DVSS_13
DVSS_74
DVSS_14
DVSS_75
DVSS_15
DVSS_76
DVSS_16
DVSS_77
DVSS_17
DVSS_78
DVSS_18
DVSS_79
DVSS_19
DVSS_80
DVSS_20
DVSS_81
DVSS_21
DVSS_82
DVSS_22
DVSS_83
DVSS_23
DVSS_84
DVSS_24
DVSS_85
DVSS_25
DVSS_86
DVSS_26
DVSS_87
DVSS_27
DVSS_88
DVSS_28
DVSS_89
DVSS_29
DVSS_90
DVSS_30
DVSS_91
DVSS_31
DVSS_92
DVSS_32
DVSS_93
DVSS_33
DVSS_94
DVSS_34
DVSS_95
DVSS_35
DVSS_96
DVSS_36
DVSS_97
DVSS_37
DVSS_98
DVSS_38
DVSS_99
DVSS_39
DVSS_100
DVSS_40
DVSS_101
DVSS_41
DVSS_102
DVSS_42
DVSS_103
DVSS_43
DVSS_104
DVSS_44
DVSS_105
DVSS_45
DVSS_106
DVSS_46
DVSS_107
DVSS_47
DVSS_108
DVSS_48
DVSS_109
DVSS_49
DVSS_110
DVSS_50
DVSS_111
DVSS_51
DVSS_112
DVSS_52
DVSS_113
DVSS_53
DVSS_114
DVSS_54
DVSS_115
DVSS_55
DVSS_116
DVSS_56
DVSS_117
R16 T16 U16 V16 AA16 D17 L17 M17 N17 P17 R17 T17 U17 V17 AA17 AC19 G18 L18 M18 N18 P18 R18 T18 U18 V18 D20 G20 H20 A21 E21 F21 G21 E22 F22 G22 H22 J22 K22 L22 M22 N22 P22 R22 T22 U22 V22 W22 Y22 AA22 W23 AB23 F28 M28 T28 AC28
DVSS_57 DVSS_58 DVSS_59 DVSS_60 DVSS_61
D1.8V
C365 0.1uF 16V
C364 0.1uF 16V
C363 0.1uF 16V
C357 10uF 10V
C356 0.1uF 16V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
C348 0.1uF 16V
C320 0.1uF 16V
C319 0.1uF 16V
C318 0.1uF 16V
C304 0.1uF 16V
BRAZIL DVR DV
JANG.J.H
BCM3549 POWER
2008.10.15
13
15
USB JACK & USB +5V Current Protection D3.3V
R713 2.7K
R712 2.7K
IC701 MIC2009YM6-TR
USB_POWER_OUT_2
MLB-201209-0120P-N2
+5.0V
BCM Tolerance
L701
* CONTROL IR & LED
P701 GF05C-96S
VOUT
6
1
5
2
4
3
VIN
P1101
R707
0
9
R703
0
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
59
59
60
60
61
61
62
62
63
63
64
64
65
65
66
66
67
67
68
68
69
69
70
70
71
71
72
72
73
73
74
74
75
75
76
76
77
77
78
78
79
79
80
80
81
81
82
82
83
83
84
84
85
85
86
86
87
87
88
88
89
89
90
90
91
91
92
92
93
93
94
94
95
95
96
96
R704
TUNER_RESETb9:G7;9:I3 11:B4 TU_CVBS_IN
3
0
4 0
R4051
R706
0 0 R4052
R4053
R4054
GAIN_SWITCH
9:G7
0
RF_SWITCH
9:G6
6
COMP1_L_IN
10:C6
COMP1_R_IN
10:C6
7
USB_CTL1 10:D5
12:F6 R711 USB_OCD1 10:D4 47
L1103 BG2012B080TF
KEY1
USB_POWER_OUT_2 KEY1
L1104 BG2012B080TF
KEY2
P704
12:H3
Make this trace minimum 12 mil
KJA-UB-0-0037
L703 KEY2
12:H3 BLM18PG121SN1D
1
5V_ST
+5V_ST
9:G4
COMP1_DET COMP1_Y_IN
11:B5
COMP1_Pb_IN
11:B5
COMP1_Pr_IN
11:B5
8
10
11
10:C6
COMP2_Y_IN
11:C4
COMP2_Pb_IN
11:C4
COMP2_Pr_IN
11:C4
AV1_L_IN
10:C5
AV1_R_IN
10:C5
AV1_CVBS_IN
11:B4
13
14
AV1_CVBS_DET
3.3V_ST
POWER_ON
GND
SIDE_CVBS_DET
USB_DP2 10:D4
4
C1109 1000pF 50V
C2017 0.1uF 16V
R3036 0
C Q904 2SC3052 OPT
D701 D702 CDS3C05GTA CDS3C05GTA 5.6V 5.6V OPT OPT
B
R2021 0 LED_WARM_STBY OPT
E
+3.3V_ST
AUDIO_OUT R1102 0
15 ZD1105 OPT
9:G5
C1105 0.1uF 16V OPT
SPK_P 10:C6
C3015 0.1uF 16V
OPT
OPT
R3038 0
R3039 0
R3034 4.7K
R3040 0
RL_ON C B
* Blue Tooth LED_POWER_ON
11:B3 JP1112
9:G6
SIDE_L_IN
10:C6
SIDE_R_IN
10:C6
C3018 100uF 16V
Not enough space
+3.3V_ST
Q905 2SC3052 SIDE_CVBS_IN
USB_DM2 10:D4
3 12:D4;A3
+3.3V_ST
WARM_ST
0
0
L1105 CB3216PA501E
C1103 100pF
ZD1104
2
C705 100uF
L1102 BG2012B080TF IR
GND
0
R4057 0
CB3216PA501E L1101
C1101 0.1uF
IR
9:G4
COMP2_DET
12
R4056
ZD1101
C1104 0.1uF
OPT 9
10:C6
COMP2_R_IN
C1102 0.1uF
GND ZD1103
0
R4055 0
R4059
ZD1107
UCOM_SDA_3.3V
OPT C2020 1000pF 50V
0
COMP2_L_IN
R4058
ZD1106
11:B3
TU_SIF
5 R705
GND
OPT C2019 1000pF 50V
D3.3V
E
L702 D1.2V
C1108
0.47uF
11
10:C6
JP703
SPK_INCM 10 DDC_SCL
9:G7;12:D5
DDC_SDA
9:G7;12:D4
+5V_ST
C703 100uF 16V
9
R3022 27
JP702 8
PCB Path(SPK_INCM) go along The SPK_N/P
D703 CDS3C05GTA 5.6V OPT
7
EDID_WP
D704 CDS3C05GTA 5.6V OPT
11:B5
DSUB_R
10:D4
USB_DP1
10:D4
R3023 27
9:G7 6
R4050 0
USB_DM1
JP704
12:I4
DSUB_DET
5 0
DSUB_G
11:B5
R4061 0
DSUB_B
11:B5
R4060
R2022 0 BLUETOOTH_RESET
4
3 RGB_HSYNC
11:D2
RGB_VSYNC
11:D2 D3.3V
R2019 0 VREG_CTRL
2
R4062 0 PC_L_IN
10:C6
PC_R_IN
10:C6
1
12507WR-10L P705 SPDIF_OUT RS232C_RxD RS232C_TxD IR
11:E5 I2
D2.5V
I2 12:D4;E6
+12V
RS232_SWITCHING R512 0 RS232_BYPASS
IC502 MC14053BDR2G 0ISTL00024A R510 0 9:G6
Y1
BCM_RX Y0
97 97
12:D4 UCOM_RX
1
16
2
15
+5V_ST L506 MLB-201209-0120P-N2
VDD
C536
A3 RS232C_RxD
Y
16V Z1
Z
Z0
INH
VEE
VSS
3
14
4
13
5
12
6
11
7
10
8
9
X
X1
RS232C_TxD
C537 47uF 16V
BCM_TX
A3
9:G6
+5.0V
X0 UCOM_TX R517 4.7K
A
B
C
0.1uF
RS232_BYPASS R514 0
R516 0
12
R4063 0
SDA
180
5.1
11
11
2
ENABLE
R702
12:F6
R1105
10
9:I4
UCOM_SCL_3.3V
CB3216PA501E
8
9
SDA0_3.3V
SCL
5
8 10
FAULT/ 1
9:I4
C701 0.1uF 16V
GND
OPT
7
10:D1
SCL0_3.3V
R3037 120K
7
TU_SYNC
R2020 10K
6
6
R3035 10K
5
C1107 0.1uF
4
5
10:D1 10:D1
5.6V ZD1102
4
TU_SCLK TU_SDATA
CDS3C05HDMI1
3
3
CDS3C05HDMI1
2
8.2V
1
2
ZD1108
1
ILIMIT
12507WR-14L
0
CDS3C05HDMI1
R701
R515 100K
12:D4
R_RS232_SWITCHING
RS-232 SET ON PROBLEM R517-*1 2.7K R515-*1 4.7K RS-232 SET ON PROBLEM
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BRAZIL VENUS
2008.10.15
DO.J.G ETC SUB BOARD I/F
14
15
10K R202 5.1V ZD233
C A2
5.1V ZD227
ZD228 5.1V
5.1V ZD202
COMP2_Pr_IN
DDC_SCL 3:T17 SDA
2
1 D0A
Q0
D0B
3
4 D1A
5
7
6 Q1
D1B
D230 ADMC5M03200L 5.6V
C244 47pF 50V
L209-*1
0
D231 ADMC5M03200L 5.6V
BG1608B121F RGB-BEAD
11
C220 100pF
3:T20 SIDE_R_IN
0
1uF R208 25V 470K
5.1V ZD220
ZD222 5.1V
L209 0
C218 100pF
RS-232C
JK208 KCN-DS-1-0089
16
5.1V ZD218
ZD219 5.1V
0
R220 5.1V ZD225
DSUB_DET 3:T16 C280 100pF 50V
3:T20 SIDE_L_IN
R218
C211
ZD226 5.1V
1K R264
0
3:T16 DSUB_R C245 47pF 50V
R212 470K
L208-*1 BG1608B121F RGB_BEAD
1K
1uF 25V
R262 10K
3:T19 SIDE_CVBS_DET
R214 C205 0.1uF 16V
C212 1uF 25V
R209 470K
3:T15 DSUB_G
+3.3V
5.1V ZD243
ZD235 5.1V
5.1V ZD236 5.1V ZD223
ZD224 5.1V
R213 470K
+5V L208 0
R290
ZD217 5.1V
C216 47pF 50V
R291
[RD]CONTACT-S_2
15
3H
5
6R
OPT
[RD]CONTACT-L_2
RGB_BEAD
3:T19 SIDE_CVBS_IN
14
[RD]O-SPRING-S_2
10
4H
L207-*1 BG1608B121F
4
5R
L207 0
13
R207 470K
C243 47pF 50V R203 15
[RD]O-SPRING-L_2
3:T15 DSUB_B
9
[RD]E-LUG_3
C267 100pF 50V
3
[WH]C-LUG-S_2
9R
1uF 25V
COMP2_R_IN 3:T23
12
8G
0 R216
8
[WH]E-LUG_2
R206 470K
[YL]CONTACT-S
9Q
D222 ADUC30S03010L 30V D221 ADUC30S03010L 30V
7
7Q
3F
5.1V ZD214
6P
5.1V ZD216
5.1V ZD208
[YL]CONTACT-L
PC AUDIO
3
+5V_ST JK206 PEJ024-01
KCN-DS-1-0088
3:T12
T_TERMINAL1
7A
B_TERMINAL1
R286 0 RS232C_TxD C1+
C2+
4
13
RIN1
C2-
5
12
ROUT1
V-
6
11
DIN1
R254 100 OPT
50V
7
7B
B_TERMINAL2
6B
T_TERMINAL2
3 5.1V ZD240
DOUT1
5.1V ZD238
14
R278 220
ZD239 5.1V
3
T_SPRING
8 50V 47pF C270
C246
R249 PC_R_IN
1uF 25V
0
3:T13
6 2
ZD237 5.1V
C1-
R256 100 OPT
220pF
GND
C250
15
50V
2
5
1
3:T12
VCC R279 220
V+
R_SPRING
SHIELD_PLATE
C247
R250 PC_L_IN
1uF 25V
0
3:T13
8
50V 47pF C271
4 9 5 10
R283 100
R287 10K 3:T11
R284 100
1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
IR
C Q202 2SC3052
B
OPT OPT
E
JK204 +5V
JST1223-001 GND
Q201 2SC3052 US_Commercial
B
R201 VCC
1K
E
DO JAE GEUN
1
+3.3V C
Fiber Optic
R288 0
US_Commercial R265 100K
VINPUT
SPDIF_OUT G4;3:T12
2
ROUT2
SPDIF OPTIC JACK
3
9
US_Commercial
8
100K R266
RIN2
+5V_ST
DIN2
US_Commercial
10
R289 3.3K
7
OPT
DOUT2
3.3K R263
+5V_ST
4
C251 0.47uF 25V
16
220pF
C255 0.47uF 25V
1
C249
C258 0.1uF 50V
4
5.1V ZD253
RS232C_RxD
5.1V ZD242
C257 0.47uF 25V
R285 0
E_SPRING
6A
R246 470K
R251 4.7K
JK207
ZD241 5.1V
IC203 MAX3232CDR
C259 0.1uF 50V
R245 470K
3 R252 4.7K
ZD251 5.1V
L211 BLM18PG121SN1D
2
DDC_SDA 3:T17 R259 22
BCM Reference
C207
C209
4 C219 100pF
5
2
[YL]O-SPRING-S
C210 1uF 25V
R221 0
4
EDID_WP 3:T16
SCL
6
[YL]E-LUG
4F
5P
R210 10K
ZD254 5.1V
C206 0.1uF 16V
AV1_R_IN 3:T18
6
50V
R260 0
WC
1
[RD]CONTACT-S_1
9P
R211 10K
C221 100pF
3
R248 22
RGB_HSYNC 3:T14
5.1V ZD250
3E
5.1V ZD221
+3.3V
R215 1K
AV1_L_IN 3:T18
ZD231 5.1V
C217 47pF 50V
R219 0
7
5.1V ZD248
6N
COMP2_L_IN 3:T23
5.1V ZD246
[RD]CONTACT-L_1
C266 100pF 50V
0 R217
1uF 25V
ZD249 5.1V
[RD]O-SPRING-S_1
R204 15
AV1_CVBS_DET 3:T18
2
VCC
D226 ADMC5M03200L 5.6V
ZD247 5.1V
4E
[WH]C-LUG-L_2
AV1_CVBS_IN 3:T18
8
R257 22
ZD245 5.1V
5N
5.1V ZD210
[RD]O-SPRING-L_1
ZD213 5.1V
7M
ZD215 5.1V
ZD207 5.1V
5.1V ZD212
470K R234 470K R233
1uF 25V
ZD211 5.1V
5
3:T22
50V 27pF C215
1
C254 4700pF
0.1uF 50V
C208
1uF 25V
[YL]O-SPRING-L C269 100pF 50V
VCC
[RD]E-LUG_2
R297 15
50V 27pF C204
C253 R258 10K OPT
74F08D IC201
[WH]C-LUG-S_1
9N
D3B
8D
14
[WH]E-LUG_1
D3A
[RD]C-LUG-S
9M
7L
13
8C
[RD]C-LUG_L
Q3
[RD]E-LUG_1
L217 CM2012FR27KT
12
[BL]C-LUG-S
9L
D2B
8B
7K
VSS 11
[BL]E-LUG
E1
E2 D2A
[GN]CONTACT-S
9K
50V 27pF C214
R247 22
10
3A
C231
0 R235
IC202 M24C02-RMN6T
+5V
RGB_VSYNC 3:T14 Q2
6J
COMP2_Pb_IN 3:T22
9
[GN]CONTACT-L
[WH]C-LUG-L_1
COMP1_R_IN 3:T21
C242 0.1uF
R296 15
50V 27pF C203
C232
0 R236
C268 100pF 50V
COMP2_Y_IN 3:T23
50V 27pF C213
8
[GN]O-SPRING-S
5.1V ZD229
ZD209 5.1V
4A
[BL]C-LUG-L
50V 27pF C230
COMP1_L_IN 3:T22
R295 15
50V 27pF C202
GND
ZD230 5.1V
50V 27pF C235
[GN]E-LUG
5J
J
BCM RECOMMAND
5.1V ZD244
3:T20
9J [GN]O-SPRING-L
ZD252 5.1V
L214 CM2012FR27KT
R294 15
50V 27pF C229
COMP1_Pr_IN
6
COMP2_DET 3:T23 C279 100pF 50V
JK209 PPJ225-01
I
D227 ENKMC2838-T112 A1
E0
5.1V ZD206
ZD205 5.1V
50V 27pF C234
H
+5V_ST
L216 CM2012FR27KT
5.1V ZD204
R293 15
ZD203 5.1V
50V 27pF L213 C228 CM2012FR27KT
G
R205 1K
L215 CM2012FR27KT
50V 27pF C233
F R,G,B PC&DDC
L212 CM2012FR27KT
R292 15
COMP1_Pb_IN 3:T21
ZD232 5.1V
C278 100pF 50V
5.1V ZD141
COMP1_DET 3:T21
7
E
+3.3V
+3.3V
ZD234 5.1V
R232 1K
COMP1_Y_IN 3:T21
D
R231 10K
COMPONENT1/2,AV1/2
C
R255 4.7K
B
R253 4.7K
A
ZD201 OPT 5.6B
BRAZIL VENUS IN.OUT
C201 0.1uF 50V
FIX_POLE
08.11.14 1
3
A
B
C
D
E
F
G
H
I
J
7
TUNER
6
+5V +3.3V GND2
TP129
21 22
4
23
9
B4[1.2V]
10
RESET[SYRSTN]
11
SDA
12
SCL
13
RSEORF
14
SBYTE
15
SPBVAL
16
SRDT
17
SRCK
18 C272 22pF 50V
24 SHIELD
LGIT
C273 22pF 50V
C125 0.1uF 16V
OPT
VC
VIN
TP132
VOUT
R101 100
TP122
L101 MLB-201209-0120P-N2
TP137
INPUT
Place close to Pin
1
3
C127 4.7uF 10V OPT
C130 100uF 16V
OUTPUT
TP115
SIF
0
GND
TP127
R103
L104
C112 0.1uF
C110 22uF
VIDEO
B3 B4
A1[RD]
D1.2V
C
A2[GN]
C101 0.1uF 50V
C102 100uF 16V
C103 0.33uF 16V
C108 0.1uF 50V
C111 47uF 16V
C113 0.1uF 50V
C115 0.01uF 50V
R104 R105 R106
22 22
TUNER_RESETb
22uF
SDA0_3.3V
3:T26
SCL0_3.3V
3:T26
22
R107
22
R108
22
R109
+3.3V
SAM2333 D102
TP140
TU_SYNC
330 TP151
C122 0.1uF
C121
3:T26
R125
D101 SAM2333
TP139
22
SCL
SPBVAL
22uF
L105
SDA
SBYTE
C119 0.1uF
C277 100uF 16V
TP136
RESET
RSEORF
C276 0.1uF 16V
TP135
C114 TP128
B2
2
+3.3V
L102
R122 1K
A1[RD]
C
TP152
A2[GN]
3:T27
0
TU_+5.0V
R111
TU_SDATA
3:T27
TU_SCLK
3:T27
L109
19 SHIELD
LGIT
C123 0.01uF
L103
OPT
C128 0.01uF
TU_SIF
3:T25
E
R121 10K C117 0.1uF
IC103
OPT
2SA1530A-T112-1R Q101 C TP146
FMS6400CS1X YIN
1
8
R118 56
YOUT
C274 91pF 50V OPT
OPT
7
3
6
4
5
CVOUT
OPT 0
TP119
3:T25
TP131
OPT R116 0 16V
C107 0.1uF OPT
COUT
TU_CVBS_IN
GND R117
CIN
TP138
TP134
GND
2
VCC
TP130
ASEL
R119 56
10uF 16V
OPT
TP120
OPT C105
TP121
R110 4.7K
TP116
OPT
R102 82
L210 OPT
FI-C3216-103KJT
R123 0
B
TP123
OPT
TU_+5.0V
3
L108 MLB-201209-0120P-N2
TP118
AFT
SRCK
5 GND1
TP124
R115 4.7K
TP113 TP114
D2.5V
4
TP126
AS7809DTRE1 22uF 0.1uF
B1
SRDT
3
IC101
C118 C120
C116 0.01uF
TP147
8
2
+12V
TP142
BB
C129 100uF 16V
TP150
19 20
LGIT
B3[3.3V]
1
L106
TP144
18
B2[2.5V]
7
R112
TP145
17
6 R282 0
TU_+5.0V
TP143
16
AIF
3:T24
R124 470
15
NC_3
GAIN_SWITCH
R120 12K
14
5
GAIN_SW
OPT C126 4.7uF 10V
TU_+5.0V
GAIN_SWITCH
TP141
13
4
NC_2
RF_SWITCH
R113 0
C124 0.1uF 16V
3:T24
TP133
12
3
VIDEO_OUT
KIA78R05F
C106 2200pF 50V
TP117
11
SIF
RF_SW
TP106
10
2
TP109
5
1
NC_1
TP110
9
B1[+5V]
TP111
8
TU101 VA1G5BF8005
TP102
TDYR-H071F
R281 0 LGIT
TP103
7
R280 0 LGIT
RF_AGC
C134 0.1uF 50V LGIT
IC102
6
RF_SWITCH
TP112
6 TU102
VTU
16V 22uF C275 LGIT
TP107
5
B0[+5V]
TP108
4 LGIT
C104 2200pF 50V
RF-GAIN_SW
TP104
3
0
TP105
2
CTR
TP125
LGIT 1
L112
+3.3V C104-*1 0.1uF 50V LGIT
L107 MLB-201209-0120P-N2
NC
TU_+5.0V
10uF C109
2
1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
HA JAE MIN
BRAZIL VENUS TNER
08.11.14 2
3
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
AA
AB
AC
AD
AE
AF
AG
AH
AI
AJ
AK
AL
AM
AN
AO
29
97
28 97
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
TU_SCLK
96
96
95
95
94
94
93
93
92
92
91
91
90
90
89
89
88
88
87
87
86
86
85
85
84
84
83
83
82
82
81
81
80
80
79
79
78
78
77
77
76
76
75
75
74
74
73
73
72
72
71
71
70
70
69
69
68
68
67
67
66
66
65
65
64
64
63
63
62
62
61
61
60
60
59
59
58
58
57
57
56
56
55
55
54
54
53
53
52
52
51
51
50
50
49
49
TU_SDATA
2:C4 2:C4
TU_SYNC
2:C4
SCL0_3.3V
2:C4
SDA0_3.3V
2:C4
TUNER_RESETb
2:C4
TU_CVBS_IN
2:D3
TU_SIF
2:E4
GAIN_SWITCH
2:C5
RF_SWITCH
2:C6
COMP1_L_IN
1:E3
COMP1_R_IN
1:E3
COMP1_DET
1:E4
COMP1_Y_IN
1:E4
COMP1_Pb_IN
1:E4
COMP1_Pr_IN
1:E3
COMP2_L_IN
R114
1:A3
COMP2_R_IN
1:A3
COMP2_DET
1:A4
COMP2_Y_IN
1:A4
COMP2_Pb_IN
1:A4
COMP2_Pr_IN
1:A3
AV1_L_IN
1:E2
AV1_R_IN
1:E1
AV1_CVBS_IN
1:E3
AV1_CVBS_DET
1:E2
SIDE_CVBS_IN
1:A2
SIDE_CVBS_DET
1:A2
SIDE_L_IN
1:A2
SIDE_R_IN
1:A1 D1.2V
48
48
47
47
46
46
DDC_SCL
1:I4
45
45
DDC_SDA
1:I4
44
44
43
43
42
42
41
41
40
40
39
39
38
38
37
37
36
36
35
35
34
34
33
33
32
32
31
31
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
EDID_WP
1:I4
DSUB_DET
1:J3
DSUB_R
1:G3
DSUB_G
1:G3
DSUB_B
1:G3
RGB_HSYNC
1:F4
RGB_VSYNC
1:F4
PC_L_IN
1:H2
PC_R_IN
1:H2
SPDIF_OUT
+5V_ST
+3.3V
1:A7;1:G4
RS232C_RxD
1:H6
RS232C_TxD IR
1:H6 1:J6
D2.5V +12V
MAYBE WILL BE ADDED.
GF05C-96S P203
6
JACK INTERFACE SIGNAL
5 4 3 2 1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BRAZIL VENUS
08.11.14
YUN GWI SEOB BOARD INTERFACE
3
3
AP